Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Copyright (c) 2013 Linaro Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  * Copyright (c) 2013 Hisilicon Limited.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) #include <linux/bitops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #include <linux/bitfield.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/mfd/syscon.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/mmc/host.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/pm_runtime.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <linux/regulator/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #include "dw_mmc.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #include "dw_mmc-pltfm.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23)  * hi6220 sd only support io voltage 1.8v and 3v
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24)  * Also need config AO_SCTRL_SEL18 accordingly
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define AO_SCTRL_SEL18		BIT(10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #define AO_SCTRL_CTRL3		0x40C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define DWMMC_SDIO_ID 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define SOC_SCTRL_SCPERCTRL5    (0x314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define SDCARD_IO_SEL18         BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define SDCARD_RD_THRESHOLD  (512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define GENCLK_DIV (7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define GPIO_CLK_ENABLE                   BIT(16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #define GPIO_CLK_DIV_MASK                 GENMASK(11, 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #define GPIO_USE_SAMPLE_DLY_MASK          GENMASK(13, 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #define UHS_REG_EXT_SAMPLE_PHASE_MASK     GENMASK(20, 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #define UHS_REG_EXT_SAMPLE_DRVPHASE_MASK  GENMASK(25, 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #define UHS_REG_EXT_SAMPLE_DLY_MASK       GENMASK(30, 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) #define TIMING_MODE     3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) #define TIMING_CFG_NUM 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) #define NUM_PHASES (40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) #define ENABLE_SHIFT_MIN_SMPL (4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) #define ENABLE_SHIFT_MAX_SMPL (12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) #define USE_DLY_MIN_SMPL (11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) #define USE_DLY_MAX_SMPL (14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) struct k3_priv {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 	int ctrl_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 	u32 cur_speed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 	struct regmap	*reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) static unsigned long dw_mci_hi6220_caps[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	MMC_CAP_CMD23,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 	MMC_CAP_CMD23,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) struct hs_timing {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	u32 drv_phase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	u32 smpl_dly;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	u32 smpl_phase_max;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	u32 smpl_phase_min;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) static struct hs_timing hs_timing_cfg[TIMING_MODE][TIMING_CFG_NUM] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	{ /* reserved */ },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	{ /* SD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 		{7, 0, 15, 15,},  /* 0: LEGACY 400k */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 		{6, 0,  4,  4,},  /* 1: MMC_HS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 		{6, 0,  3,  3,},  /* 2: SD_HS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 		{6, 0, 15, 15,},  /* 3: SDR12 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 		{6, 0,  2,  2,},  /* 4: SDR25 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 		{4, 0, 11,  0,},  /* 5: SDR50 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 		{6, 4, 15,  0,},  /* 6: SDR104 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 		{0},              /* 7: DDR50 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 		{0},              /* 8: DDR52 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 		{0},              /* 9: HS200 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	{ /* SDIO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 		{7, 0, 15, 15,},  /* 0: LEGACY 400k */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 		{0},              /* 1: MMC_HS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 		{6, 0, 15, 15,},  /* 2: SD_HS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 		{6, 0, 15, 15,},  /* 3: SDR12 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 		{6, 0,  0,  0,},  /* 4: SDR25 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 		{4, 0, 12,  0,},  /* 5: SDR50 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 		{5, 4, 15,  0,},  /* 6: SDR104 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 		{0},              /* 7: DDR50 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 		{0},              /* 8: DDR52 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 		{0},              /* 9: HS200 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) static void dw_mci_k3_set_ios(struct dw_mci *host, struct mmc_ios *ios)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	ret = clk_set_rate(host->ciu_clk, ios->clock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 		dev_warn(host->dev, "failed to set rate %uHz\n", ios->clock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	host->bus_hz = clk_get_rate(host->ciu_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) static const struct dw_mci_drv_data k3_drv_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	.set_ios		= dw_mci_k3_set_ios,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) static int dw_mci_hi6220_parse_dt(struct dw_mci *host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	struct k3_priv *priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	priv = devm_kzalloc(host->dev, sizeof(*priv), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	if (!priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	priv->reg = syscon_regmap_lookup_by_phandle(host->dev->of_node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 					 "hisilicon,peripheral-syscon");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	if (IS_ERR(priv->reg))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 		priv->reg = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	priv->ctrl_id = of_alias_get_id(host->dev->of_node, "mshc");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	if (priv->ctrl_id < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 		priv->ctrl_id = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	if (priv->ctrl_id >= TIMING_MODE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	host->priv = priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) static int dw_mci_hi6220_switch_voltage(struct mmc_host *mmc, struct mmc_ios *ios)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	struct dw_mci_slot *slot = mmc_priv(mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	struct k3_priv *priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	struct dw_mci *host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	int min_uv, max_uv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	host = slot->host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	priv = host->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	if (!priv || !priv->reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_330) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 		ret = regmap_update_bits(priv->reg, AO_SCTRL_CTRL3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 					 AO_SCTRL_SEL18, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 		min_uv = 3000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 		max_uv = 3000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	} else if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_180) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 		ret = regmap_update_bits(priv->reg, AO_SCTRL_CTRL3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 					 AO_SCTRL_SEL18, AO_SCTRL_SEL18);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 		min_uv = 1800000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 		max_uv = 1800000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 		dev_dbg(host->dev, "voltage not supported\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 		dev_dbg(host->dev, "switch voltage failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	if (IS_ERR_OR_NULL(mmc->supply.vqmmc))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	ret = regulator_set_voltage(mmc->supply.vqmmc, min_uv, max_uv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 		dev_dbg(host->dev, "Regulator set error %d: %d - %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 				 ret, min_uv, max_uv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) static void dw_mci_hi6220_set_ios(struct dw_mci *host, struct mmc_ios *ios)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	unsigned int clock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	clock = (ios->clock <= 25000000) ? 25000000 : ios->clock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	ret = clk_set_rate(host->biu_clk, clock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 		dev_warn(host->dev, "failed to set rate %uHz\n", clock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	host->bus_hz = clk_get_rate(host->biu_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) static int dw_mci_hi6220_execute_tuning(struct dw_mci_slot *slot, u32 opcode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) static const struct dw_mci_drv_data hi6220_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 	.caps			= dw_mci_hi6220_caps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	.num_caps		= ARRAY_SIZE(dw_mci_hi6220_caps),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	.switch_voltage		= dw_mci_hi6220_switch_voltage,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	.set_ios		= dw_mci_hi6220_set_ios,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	.parse_dt		= dw_mci_hi6220_parse_dt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	.execute_tuning		= dw_mci_hi6220_execute_tuning,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) static void dw_mci_hs_set_timing(struct dw_mci *host, int timing,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 				     int smpl_phase)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	u32 drv_phase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	u32 smpl_dly;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	u32 use_smpl_dly = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 	u32 enable_shift = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 	u32 reg_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 	int ctrl_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 	struct k3_priv *priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 	priv = host->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 	ctrl_id = priv->ctrl_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 	drv_phase = hs_timing_cfg[ctrl_id][timing].drv_phase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 	smpl_dly   = hs_timing_cfg[ctrl_id][timing].smpl_dly;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 	if (smpl_phase == -1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 		smpl_phase = (hs_timing_cfg[ctrl_id][timing].smpl_phase_max +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 			     hs_timing_cfg[ctrl_id][timing].smpl_phase_min) / 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 	switch (timing) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 	case MMC_TIMING_UHS_SDR104:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 		if (smpl_phase >= USE_DLY_MIN_SMPL &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 				smpl_phase <= USE_DLY_MAX_SMPL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 			use_smpl_dly = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 		fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 	case MMC_TIMING_UHS_SDR50:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 		if (smpl_phase >= ENABLE_SHIFT_MIN_SMPL &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 				smpl_phase <= ENABLE_SHIFT_MAX_SMPL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 			enable_shift = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 	mci_writel(host, GPIO, 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 	usleep_range(5, 10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 	reg_value = FIELD_PREP(UHS_REG_EXT_SAMPLE_PHASE_MASK, smpl_phase) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 		    FIELD_PREP(UHS_REG_EXT_SAMPLE_DLY_MASK, smpl_dly) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 		    FIELD_PREP(UHS_REG_EXT_SAMPLE_DRVPHASE_MASK, drv_phase);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 	mci_writel(host, UHS_REG_EXT, reg_value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 	mci_writel(host, ENABLE_SHIFT, enable_shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 	reg_value = FIELD_PREP(GPIO_CLK_DIV_MASK, GENCLK_DIV) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 			     FIELD_PREP(GPIO_USE_SAMPLE_DLY_MASK, use_smpl_dly);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 	mci_writel(host, GPIO, (unsigned int)reg_value | GPIO_CLK_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 	/* We should delay 1ms wait for timing setting finished. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 	usleep_range(1000, 2000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) static int dw_mci_hi3660_init(struct dw_mci *host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 	mci_writel(host, CDTHRCTL, SDMMC_SET_THLD(SDCARD_RD_THRESHOLD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 		    SDMMC_CARD_RD_THR_EN));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 	dw_mci_hs_set_timing(host, MMC_TIMING_LEGACY, -1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 	host->bus_hz /= (GENCLK_DIV + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) static int dw_mci_set_sel18(struct dw_mci *host, bool set)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 	unsigned int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 	struct k3_priv *priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 	priv = host->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 	val = set ? SDCARD_IO_SEL18 : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 	ret = regmap_update_bits(priv->reg, SOC_SCTRL_SCPERCTRL5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 				 SDCARD_IO_SEL18, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 		dev_err(host->dev, "sel18 %u error\n", val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) static void dw_mci_hi3660_set_ios(struct dw_mci *host, struct mmc_ios *ios)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 	unsigned long wanted;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 	unsigned long actual;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 	struct k3_priv *priv = host->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 	if (!ios->clock || ios->clock == priv->cur_speed)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 	wanted = ios->clock * (GENCLK_DIV + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 	ret = clk_set_rate(host->ciu_clk, wanted);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 		dev_err(host->dev, "failed to set rate %luHz\n", wanted);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 	actual = clk_get_rate(host->ciu_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 	dw_mci_hs_set_timing(host, ios->timing, -1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 	host->bus_hz = actual / (GENCLK_DIV + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 	host->current_speed = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 	priv->cur_speed = host->bus_hz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) static int dw_mci_get_best_clksmpl(unsigned int sample_flag)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 	int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 	int interval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 	unsigned int v;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 	unsigned int len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 	unsigned int range_start = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 	unsigned int range_length = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 	unsigned int middle_range = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 	if (!sample_flag)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 		return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 	if (~sample_flag == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 	i = ffs(sample_flag) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 	* A clock cycle is divided into 32 phases,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 	* each of which is represented by a bit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 	* finding the optimal phase.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 	*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 	while (i < 32) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 		v = ror32(sample_flag, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 		len = ffs(~v) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 		if (len > range_length) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 			range_length = len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 			range_start = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 		interval = ffs(v >> len) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) 		if (interval < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 		i += len + interval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) 	middle_range = range_start + range_length / 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) 	if (middle_range >= 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) 		middle_range %= 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) 	return middle_range;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) static int dw_mci_hi3660_execute_tuning(struct dw_mci_slot *slot, u32 opcode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) 	int i = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) 	struct dw_mci *host = slot->host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) 	struct mmc_host *mmc = slot->mmc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) 	int smpl_phase = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) 	u32 tuning_sample_flag = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) 	int best_clksmpl = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) 	for (i = 0; i < NUM_PHASES; ++i, ++smpl_phase) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) 		smpl_phase %= 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) 		mci_writel(host, TMOUT, ~0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) 		dw_mci_hs_set_timing(host, mmc->ios.timing, smpl_phase);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) 		if (!mmc_send_tuning(mmc, opcode, NULL))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) 			tuning_sample_flag |= (1 << smpl_phase);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) 		else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) 			tuning_sample_flag &= ~(1 << smpl_phase);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) 	best_clksmpl = dw_mci_get_best_clksmpl(tuning_sample_flag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) 	if (best_clksmpl < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) 		dev_err(host->dev, "All phases bad!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) 		return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) 	dw_mci_hs_set_timing(host, mmc->ios.timing, best_clksmpl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) 	dev_info(host->dev, "tuning ok best_clksmpl %u tuning_sample_flag %x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) 		 best_clksmpl, tuning_sample_flag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) static int dw_mci_hi3660_switch_voltage(struct mmc_host *mmc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) 					struct mmc_ios *ios)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) 	int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) 	struct dw_mci_slot *slot = mmc_priv(mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) 	struct k3_priv *priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) 	struct dw_mci *host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) 	host = slot->host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) 	priv = host->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) 	if (!priv || !priv->reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) 	if (priv->ctrl_id == DWMMC_SDIO_ID)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) 	if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) 		ret = dw_mci_set_sel18(host, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) 	else if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) 		ret = dw_mci_set_sel18(host, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) 	if (!IS_ERR(mmc->supply.vqmmc)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) 		ret = mmc_regulator_set_vqmmc(mmc, ios);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) 		if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) 			dev_err(host->dev, "Regulator set error %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) 			return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) static const struct dw_mci_drv_data hi3660_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) 	.init = dw_mci_hi3660_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) 	.set_ios = dw_mci_hi3660_set_ios,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) 	.parse_dt = dw_mci_hi6220_parse_dt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) 	.execute_tuning = dw_mci_hi3660_execute_tuning,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) 	.switch_voltage  = dw_mci_hi3660_switch_voltage,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) static const struct of_device_id dw_mci_k3_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) 	{ .compatible = "hisilicon,hi3660-dw-mshc", .data = &hi3660_data, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) 	{ .compatible = "hisilicon,hi4511-dw-mshc", .data = &k3_drv_data, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) 	{ .compatible = "hisilicon,hi6220-dw-mshc", .data = &hi6220_data, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) 	{},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) MODULE_DEVICE_TABLE(of, dw_mci_k3_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) static int dw_mci_k3_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) 	const struct dw_mci_drv_data *drv_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) 	const struct of_device_id *match;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) 	match = of_match_node(dw_mci_k3_match, pdev->dev.of_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) 	drv_data = match->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) 	return dw_mci_pltfm_register(pdev, drv_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) static const struct dev_pm_ops dw_mci_k3_dev_pm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) 	SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) 				pm_runtime_force_resume)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) 	SET_RUNTIME_PM_OPS(dw_mci_runtime_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) 			   dw_mci_runtime_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) 			   NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) static struct platform_driver dw_mci_k3_pltfm_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) 	.probe		= dw_mci_k3_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) 	.remove		= dw_mci_pltfm_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) 	.driver		= {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) 		.name		= "dwmmc_k3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) 		.probe_type	= PROBE_PREFER_ASYNCHRONOUS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) 		.of_match_table	= dw_mci_k3_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) 		.pm		= &dw_mci_k3_dev_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) module_platform_driver(dw_mci_k3_pltfm_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) MODULE_DESCRIPTION("K3 Specific DW-MSHC Driver Extension");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) MODULE_LICENSE("GPL v2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) MODULE_ALIAS("platform:dwmmc_k3");