^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2018 HiSilicon Technologies Co., Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/mfd/syscon.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/mmc/host.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/pm_runtime.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/regulator/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include "dw_mmc.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include "dw_mmc-pltfm.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define ALL_INT_CLR 0x1ffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) struct hi3798cv200_priv {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) struct clk *sample_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) struct clk *drive_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) static unsigned long dw_mci_hi3798cv200_caps[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) MMC_CAP_CMD23,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) MMC_CAP_CMD23,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) MMC_CAP_CMD23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) static void dw_mci_hi3798cv200_set_ios(struct dw_mci *host, struct mmc_ios *ios)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) struct hi3798cv200_priv *priv = host->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) val = mci_readl(host, UHS_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) if (ios->timing == MMC_TIMING_MMC_DDR52 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) ios->timing == MMC_TIMING_UHS_DDR50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) val |= SDMMC_UHS_DDR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) val &= ~SDMMC_UHS_DDR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) mci_writel(host, UHS_REG, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) val = mci_readl(host, ENABLE_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) if (ios->timing == MMC_TIMING_MMC_DDR52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) val |= SDMMC_ENABLE_PHASE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) val &= ~SDMMC_ENABLE_PHASE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) mci_writel(host, ENABLE_SHIFT, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) val = mci_readl(host, DDR_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) if (ios->timing == MMC_TIMING_MMC_HS400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) val |= SDMMC_DDR_HS400;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) val &= ~SDMMC_DDR_HS400;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) mci_writel(host, DDR_REG, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) if (ios->timing == MMC_TIMING_MMC_HS ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) ios->timing == MMC_TIMING_LEGACY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) clk_set_phase(priv->drive_clk, 180);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) else if (ios->timing == MMC_TIMING_MMC_HS200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) clk_set_phase(priv->drive_clk, 135);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) static int dw_mci_hi3798cv200_execute_tuning(struct dw_mci_slot *slot,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) u32 opcode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) static const int degrees[] = { 0, 45, 90, 135, 180, 225, 270, 315 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) struct dw_mci *host = slot->host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) struct hi3798cv200_priv *priv = host->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) int raise_point = -1, fall_point = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) int err, prev_err = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) int found = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) for (i = 0; i < ARRAY_SIZE(degrees); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) clk_set_phase(priv->sample_clk, degrees[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) mci_writel(host, RINTSTS, ALL_INT_CLR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) err = mmc_send_tuning(slot->mmc, opcode, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) if (!err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) found = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) if (i > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) if (err && !prev_err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) fall_point = i - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) if (!err && prev_err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) raise_point = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) if (raise_point != -1 && fall_point != -1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) goto tuning_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) prev_err = err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) err = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) tuning_out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) if (found) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) if (raise_point == -1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) raise_point = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) if (fall_point == -1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) fall_point = ARRAY_SIZE(degrees) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) if (fall_point < raise_point) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) if ((raise_point + fall_point) >
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) (ARRAY_SIZE(degrees) - 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) i = fall_point / 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) i = (raise_point + ARRAY_SIZE(degrees) - 1) / 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) i = (raise_point + fall_point) / 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) clk_set_phase(priv->sample_clk, degrees[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) dev_dbg(host->dev, "Tuning clk_sample[%d, %d], set[%d]\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) raise_point, fall_point, degrees[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) dev_err(host->dev, "No valid clk_sample shift! use default\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) err = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) mci_writel(host, RINTSTS, ALL_INT_CLR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) static int dw_mci_hi3798cv200_init(struct dw_mci *host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) struct hi3798cv200_priv *priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) priv = devm_kzalloc(host->dev, sizeof(*priv), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) if (!priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) priv->sample_clk = devm_clk_get(host->dev, "ciu-sample");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) if (IS_ERR(priv->sample_clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) dev_err(host->dev, "failed to get ciu-sample clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) return PTR_ERR(priv->sample_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) priv->drive_clk = devm_clk_get(host->dev, "ciu-drive");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) if (IS_ERR(priv->drive_clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) dev_err(host->dev, "failed to get ciu-drive clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) return PTR_ERR(priv->drive_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) ret = clk_prepare_enable(priv->sample_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) dev_err(host->dev, "failed to enable ciu-sample clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) ret = clk_prepare_enable(priv->drive_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) dev_err(host->dev, "failed to enable ciu-drive clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) goto disable_sample_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) host->priv = priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) disable_sample_clk:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) clk_disable_unprepare(priv->sample_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) static const struct dw_mci_drv_data hi3798cv200_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) .caps = dw_mci_hi3798cv200_caps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) .num_caps = ARRAY_SIZE(dw_mci_hi3798cv200_caps),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) .init = dw_mci_hi3798cv200_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) .set_ios = dw_mci_hi3798cv200_set_ios,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) .execute_tuning = dw_mci_hi3798cv200_execute_tuning,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) static int dw_mci_hi3798cv200_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) return dw_mci_pltfm_register(pdev, &hi3798cv200_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) static int dw_mci_hi3798cv200_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) struct dw_mci *host = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) struct hi3798cv200_priv *priv = host->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) clk_disable_unprepare(priv->drive_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) clk_disable_unprepare(priv->sample_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) return dw_mci_pltfm_remove(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) static const struct of_device_id dw_mci_hi3798cv200_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) { .compatible = "hisilicon,hi3798cv200-dw-mshc", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) MODULE_DEVICE_TABLE(of, dw_mci_hi3798cv200_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) static struct platform_driver dw_mci_hi3798cv200_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) .probe = dw_mci_hi3798cv200_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) .remove = dw_mci_hi3798cv200_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) .name = "dwmmc_hi3798cv200",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) .probe_type = PROBE_PREFER_ASYNCHRONOUS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) .of_match_table = dw_mci_hi3798cv200_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) module_platform_driver(dw_mci_hi3798cv200_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) MODULE_DESCRIPTION("HiSilicon Hi3798CV200 Specific DW-MSHC Driver Extension");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) MODULE_LICENSE("GPL v2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) MODULE_ALIAS("platform:dwmmc_hi3798cv200");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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