^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-or-later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Exynos Specific Extensions for Synopsys DW Multimedia Card Interface driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2012-2014 Samsung Electronics Co., Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #ifndef _DW_MMC_EXYNOS_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #define _DW_MMC_EXYNOS_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define SDMMC_CLKSEL 0x09C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define SDMMC_CLKSEL64 0x0A8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) /* Extended Register's Offset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define SDMMC_HS400_DQS_EN 0x180
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define SDMMC_HS400_ASYNC_FIFO_CTRL 0x184
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define SDMMC_HS400_DLINE_CTRL 0x188
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) /* CLKSEL register defines */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define SDMMC_CLKSEL_CCLK_SAMPLE(x) (((x) & 7) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define SDMMC_CLKSEL_CCLK_DRIVE(x) (((x) & 7) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define SDMMC_CLKSEL_CCLK_DIVIDER(x) (((x) & 7) << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define SDMMC_CLKSEL_GET_DRV_WD3(x) (((x) >> 16) & 0x7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define SDMMC_CLKSEL_GET_DIV(x) (((x) >> 24) & 0x7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define SDMMC_CLKSEL_UP_SAMPLE(x, y) (((x) & ~SDMMC_CLKSEL_CCLK_SAMPLE(7)) |\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) SDMMC_CLKSEL_CCLK_SAMPLE(y))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define SDMMC_CLKSEL_TIMING(x, y, z) (SDMMC_CLKSEL_CCLK_SAMPLE(x) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) SDMMC_CLKSEL_CCLK_DRIVE(y) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) SDMMC_CLKSEL_CCLK_DIVIDER(z))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define SDMMC_CLKSEL_TIMING_MASK SDMMC_CLKSEL_TIMING(0x7, 0x7, 0x7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define SDMMC_CLKSEL_WAKEUP_INT BIT(11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) /* RCLK_EN register defines */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define DATA_STROBE_EN BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define AXI_NON_BLOCKING_WR BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) /* DLINE_CTRL register defines */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define DQS_CTRL_RD_DELAY(x, y) (((x) & ~0x3FF) | ((y) & 0x3FF))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define DQS_CTRL_GET_RD_DELAY(x) ((x) & 0x3FF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) /* Protector Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define SDMMC_EMMCP_BASE 0x1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define SDMMC_MPSECURITY (SDMMC_EMMCP_BASE + 0x0010)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define SDMMC_MPSBEGIN0 (SDMMC_EMMCP_BASE + 0x0200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define SDMMC_MPSEND0 (SDMMC_EMMCP_BASE + 0x0204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define SDMMC_MPSCTRL0 (SDMMC_EMMCP_BASE + 0x020C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) /* SMU control defines */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define SDMMC_MPSCTRL_SECURE_READ_BIT BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define SDMMC_MPSCTRL_SECURE_WRITE_BIT BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define SDMMC_MPSCTRL_NON_SECURE_READ_BIT BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define SDMMC_MPSCTRL_NON_SECURE_WRITE_BIT BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define SDMMC_MPSCTRL_USE_FUSE_KEY BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define SDMMC_MPSCTRL_ECB_MODE BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define SDMMC_MPSCTRL_ENCRYPTION BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define SDMMC_MPSCTRL_VALID BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) /* Maximum number of Ending sector */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define SDMMC_ENDING_SEC_NR_MAX 0xFFFFFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) /* Fixed clock divider */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define EXYNOS4210_FIXED_CIU_CLK_DIV 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define EXYNOS4412_FIXED_CIU_CLK_DIV 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define HS400_FIXED_CIU_CLK_DIV 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) /* Minimal required clock frequency for cclkin, unit: HZ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define EXYNOS_CCLKIN_MIN 50000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #endif /* _DW_MMC_EXYNOS_H_ */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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