^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * davinci_mmc.c - TI DaVinci MMC/SD/SDIO driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2006 Texas Instruments.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Original author: Purushotam Kumar
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Copyright (C) 2009 David Brownell
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/ioport.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/cpufreq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/mmc/host.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/dmaengine.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/dma-mapping.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/mmc/mmc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/mmc/slot-gpio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <linux/platform_data/mmc-davinci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) * Register Definitions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define DAVINCI_MMCCTL 0x00 /* Control Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define DAVINCI_MMCCLK 0x04 /* Memory Clock Control Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define DAVINCI_MMCST0 0x08 /* Status Register 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define DAVINCI_MMCST1 0x0C /* Status Register 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define DAVINCI_MMCIM 0x10 /* Interrupt Mask Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define DAVINCI_MMCTOR 0x14 /* Response Time-Out Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define DAVINCI_MMCTOD 0x18 /* Data Read Time-Out Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define DAVINCI_MMCBLEN 0x1C /* Block Length Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define DAVINCI_MMCNBLK 0x20 /* Number of Blocks Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define DAVINCI_MMCNBLC 0x24 /* Number of Blocks Counter Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define DAVINCI_MMCDRR 0x28 /* Data Receive Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define DAVINCI_MMCDXR 0x2C /* Data Transmit Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define DAVINCI_MMCCMD 0x30 /* Command Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define DAVINCI_MMCARGHL 0x34 /* Argument Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define DAVINCI_MMCRSP01 0x38 /* Response Register 0 and 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define DAVINCI_MMCRSP23 0x3C /* Response Register 0 and 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define DAVINCI_MMCRSP45 0x40 /* Response Register 0 and 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define DAVINCI_MMCRSP67 0x44 /* Response Register 0 and 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define DAVINCI_MMCDRSP 0x48 /* Data Response Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define DAVINCI_MMCETOK 0x4C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define DAVINCI_MMCCIDX 0x50 /* Command Index Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define DAVINCI_MMCCKC 0x54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define DAVINCI_MMCTORC 0x58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define DAVINCI_MMCTODC 0x5C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define DAVINCI_MMCBLNC 0x60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define DAVINCI_SDIOCTL 0x64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define DAVINCI_SDIOST0 0x68
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define DAVINCI_SDIOIEN 0x6C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define DAVINCI_SDIOIST 0x70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define DAVINCI_MMCFIFOCTL 0x74 /* FIFO Control Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) /* DAVINCI_MMCCTL definitions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define MMCCTL_DATRST (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define MMCCTL_CMDRST (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define MMCCTL_WIDTH_8_BIT (1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define MMCCTL_WIDTH_4_BIT (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define MMCCTL_DATEG_DISABLED (0 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define MMCCTL_DATEG_RISING (1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define MMCCTL_DATEG_FALLING (2 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define MMCCTL_DATEG_BOTH (3 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define MMCCTL_PERMDR_LE (0 << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define MMCCTL_PERMDR_BE (1 << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define MMCCTL_PERMDX_LE (0 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define MMCCTL_PERMDX_BE (1 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) /* DAVINCI_MMCCLK definitions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define MMCCLK_CLKEN (1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define MMCCLK_CLKRT_MASK (0xFF << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) /* IRQ bit definitions, for DAVINCI_MMCST0 and DAVINCI_MMCIM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define MMCST0_DATDNE BIT(0) /* data done */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define MMCST0_BSYDNE BIT(1) /* busy done */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define MMCST0_RSPDNE BIT(2) /* command done */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define MMCST0_TOUTRD BIT(3) /* data read timeout */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define MMCST0_TOUTRS BIT(4) /* command response timeout */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define MMCST0_CRCWR BIT(5) /* data write CRC error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define MMCST0_CRCRD BIT(6) /* data read CRC error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define MMCST0_CRCRS BIT(7) /* command response CRC error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define MMCST0_DXRDY BIT(9) /* data transmit ready (fifo empty) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define MMCST0_DRRDY BIT(10) /* data receive ready (data in fifo)*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define MMCST0_DATED BIT(11) /* DAT3 edge detect */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define MMCST0_TRNDNE BIT(12) /* transfer done */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) /* DAVINCI_MMCST1 definitions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define MMCST1_BUSY (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) /* DAVINCI_MMCCMD definitions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define MMCCMD_CMD_MASK (0x3F << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define MMCCMD_PPLEN (1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define MMCCMD_BSYEXP (1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define MMCCMD_RSPFMT_MASK (3 << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define MMCCMD_RSPFMT_NONE (0 << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define MMCCMD_RSPFMT_R1456 (1 << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define MMCCMD_RSPFMT_R2 (2 << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define MMCCMD_RSPFMT_R3 (3 << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define MMCCMD_DTRW (1 << 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define MMCCMD_STRMTP (1 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define MMCCMD_WDATX (1 << 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define MMCCMD_INITCK (1 << 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define MMCCMD_DCLR (1 << 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define MMCCMD_DMATRIG (1 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) /* DAVINCI_MMCFIFOCTL definitions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define MMCFIFOCTL_FIFORST (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define MMCFIFOCTL_FIFODIR_WR (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define MMCFIFOCTL_FIFODIR_RD (0 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define MMCFIFOCTL_FIFOLEV (1 << 2) /* 0 = 128 bits, 1 = 256 bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define MMCFIFOCTL_ACCWD_4 (0 << 3) /* access width of 4 bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define MMCFIFOCTL_ACCWD_3 (1 << 3) /* access width of 3 bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define MMCFIFOCTL_ACCWD_2 (2 << 3) /* access width of 2 bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define MMCFIFOCTL_ACCWD_1 (3 << 3) /* access width of 1 byte */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) /* DAVINCI_SDIOST0 definitions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define SDIOST0_DAT1_HI BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) /* DAVINCI_SDIOIEN definitions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define SDIOIEN_IOINTEN BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) /* DAVINCI_SDIOIST definitions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define SDIOIST_IOINT BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) /* MMCSD Init clock in Hz in opendrain mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define MMCSD_INIT_CLOCK 200000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) * One scatterlist dma "segment" is at most MAX_CCNT rw_threshold units,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) * and we handle up to MAX_NR_SG segments. MMC_BLOCK_BOUNCE kicks in only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) * for drivers with max_segs == 1, making the segments bigger (64KB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) * than the page or two that's otherwise typical. nr_sg (passed from
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) * platform data) == 16 gives at least the same throughput boost, using
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) * EDMA transfer linkage instead of spending CPU time copying pages.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define MAX_CCNT ((1 << 16) - 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define MAX_NR_SG 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) static unsigned rw_threshold = 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) module_param(rw_threshold, uint, S_IRUGO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) MODULE_PARM_DESC(rw_threshold,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) "Read/Write threshold. Default = 32");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) static unsigned poll_threshold = 128;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) module_param(poll_threshold, uint, S_IRUGO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) MODULE_PARM_DESC(poll_threshold,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) "Polling transaction size threshold. Default = 128");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) static unsigned poll_loopcount = 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) module_param(poll_loopcount, uint, S_IRUGO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) MODULE_PARM_DESC(poll_loopcount,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) "Maximum polling loop count. Default = 32");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) static unsigned use_dma = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) module_param(use_dma, uint, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) MODULE_PARM_DESC(use_dma, "Whether to use DMA or not. Default = 1");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) struct mmc_davinci_host {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) struct mmc_command *cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) struct mmc_data *data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) struct mmc_host *mmc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) unsigned int mmc_input_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) struct resource *mem_res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) int mmc_irq, sdio_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) unsigned char bus_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define DAVINCI_MMC_DATADIR_NONE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define DAVINCI_MMC_DATADIR_READ 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define DAVINCI_MMC_DATADIR_WRITE 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) unsigned char data_dir;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) /* buffer is used during PIO of one scatterlist segment, and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) * is updated along with buffer_bytes_left. bytes_left applies
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) * to all N blocks of the PIO transfer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) u8 *buffer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) u32 buffer_bytes_left;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) u32 bytes_left;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) struct dma_chan *dma_tx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) struct dma_chan *dma_rx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) bool use_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) bool do_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) bool sdio_int;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) bool active_request;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) /* For PIO we walk scatterlists one segment at a time. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) unsigned int sg_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) struct scatterlist *sg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) /* Version of the MMC/SD controller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) u8 version;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) /* for ns in one cycle calculation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) unsigned ns_in_one_cycle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) /* Number of sg segments */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) u8 nr_sg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #ifdef CONFIG_CPU_FREQ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) struct notifier_block freq_transition;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) static irqreturn_t mmc_davinci_irq(int irq, void *dev_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) /* PIO only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) static void mmc_davinci_sg_to_buf(struct mmc_davinci_host *host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) host->buffer_bytes_left = sg_dma_len(host->sg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) host->buffer = sg_virt(host->sg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) if (host->buffer_bytes_left > host->bytes_left)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) host->buffer_bytes_left = host->bytes_left;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) static void davinci_fifo_data_trans(struct mmc_davinci_host *host,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) unsigned int n)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) u8 *p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) if (host->buffer_bytes_left == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) host->sg = sg_next(host->data->sg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) mmc_davinci_sg_to_buf(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) p = host->buffer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) if (n > host->buffer_bytes_left)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) n = host->buffer_bytes_left;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) host->buffer_bytes_left -= n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) host->bytes_left -= n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) /* NOTE: we never transfer more than rw_threshold bytes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) * to/from the fifo here; there's no I/O overlap.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) * This also assumes that access width( i.e. ACCWD) is 4 bytes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) if (host->data_dir == DAVINCI_MMC_DATADIR_WRITE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) for (i = 0; i < (n >> 2); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) writel(*((u32 *)p), host->base + DAVINCI_MMCDXR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) p = p + 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) if (n & 3) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) iowrite8_rep(host->base + DAVINCI_MMCDXR, p, (n & 3));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) p = p + (n & 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) for (i = 0; i < (n >> 2); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) *((u32 *)p) = readl(host->base + DAVINCI_MMCDRR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) p = p + 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) if (n & 3) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) ioread8_rep(host->base + DAVINCI_MMCDRR, p, (n & 3));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) p = p + (n & 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) host->buffer = p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) static void mmc_davinci_start_command(struct mmc_davinci_host *host,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) struct mmc_command *cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) u32 cmd_reg = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) u32 im_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) dev_dbg(mmc_dev(host->mmc), "CMD%d, arg 0x%08x%s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) cmd->opcode, cmd->arg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) ({ char *s;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) switch (mmc_resp_type(cmd)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) case MMC_RSP_R1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) s = ", R1/R5/R6/R7 response";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) case MMC_RSP_R1B:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) s = ", R1b response";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) case MMC_RSP_R2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) s = ", R2 response";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) case MMC_RSP_R3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) s = ", R3/R4 response";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) s = ", (R? response)";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) }; s; }));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) host->cmd = cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) switch (mmc_resp_type(cmd)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) case MMC_RSP_R1B:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) /* There's some spec confusion about when R1B is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) * allowed, but if the card doesn't issue a BUSY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) * then it's harmless for us to allow it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) cmd_reg |= MMCCMD_BSYEXP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) case MMC_RSP_R1: /* 48 bits, CRC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) cmd_reg |= MMCCMD_RSPFMT_R1456;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) case MMC_RSP_R2: /* 136 bits, CRC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) cmd_reg |= MMCCMD_RSPFMT_R2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) case MMC_RSP_R3: /* 48 bits, no CRC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) cmd_reg |= MMCCMD_RSPFMT_R3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) cmd_reg |= MMCCMD_RSPFMT_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) dev_dbg(mmc_dev(host->mmc), "unknown resp_type %04x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) mmc_resp_type(cmd));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) /* Set command index */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) cmd_reg |= cmd->opcode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) /* Enable EDMA transfer triggers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) if (host->do_dma)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) cmd_reg |= MMCCMD_DMATRIG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) if (host->version == MMC_CTLR_VERSION_2 && host->data != NULL &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) host->data_dir == DAVINCI_MMC_DATADIR_READ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) cmd_reg |= MMCCMD_DMATRIG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) /* Setting whether command involves data transfer or not */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) if (cmd->data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) cmd_reg |= MMCCMD_WDATX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) /* Setting whether data read or write */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) if (host->data_dir == DAVINCI_MMC_DATADIR_WRITE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) cmd_reg |= MMCCMD_DTRW;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) if (host->bus_mode == MMC_BUSMODE_PUSHPULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) cmd_reg |= MMCCMD_PPLEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) /* set Command timeout */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) writel(0x1FFF, host->base + DAVINCI_MMCTOR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) /* Enable interrupt (calculate here, defer until FIFO is stuffed). */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) im_val = MMCST0_RSPDNE | MMCST0_CRCRS | MMCST0_TOUTRS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) if (host->data_dir == DAVINCI_MMC_DATADIR_WRITE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) im_val |= MMCST0_DATDNE | MMCST0_CRCWR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) if (!host->do_dma)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) im_val |= MMCST0_DXRDY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) } else if (host->data_dir == DAVINCI_MMC_DATADIR_READ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) im_val |= MMCST0_DATDNE | MMCST0_CRCRD | MMCST0_TOUTRD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) if (!host->do_dma)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) im_val |= MMCST0_DRRDY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) * Before non-DMA WRITE commands the controller needs priming:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) * FIFO should be populated with 32 bytes i.e. whatever is the FIFO size
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) if (!host->do_dma && (host->data_dir == DAVINCI_MMC_DATADIR_WRITE))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) davinci_fifo_data_trans(host, rw_threshold);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) writel(cmd->arg, host->base + DAVINCI_MMCARGHL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) writel(cmd_reg, host->base + DAVINCI_MMCCMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) host->active_request = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) if (!host->do_dma && host->bytes_left <= poll_threshold) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) u32 count = poll_loopcount;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) while (host->active_request && count--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) mmc_davinci_irq(0, host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) cpu_relax();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) if (host->active_request)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) writel(im_val, host->base + DAVINCI_MMCIM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) /*----------------------------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) /* DMA infrastructure */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) static void davinci_abort_dma(struct mmc_davinci_host *host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) struct dma_chan *sync_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) if (host->data_dir == DAVINCI_MMC_DATADIR_READ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) sync_dev = host->dma_rx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) sync_dev = host->dma_tx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) dmaengine_terminate_all(sync_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) static int mmc_davinci_send_dma_request(struct mmc_davinci_host *host,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) struct mmc_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) struct dma_chan *chan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) struct dma_async_tx_descriptor *desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) if (host->data_dir == DAVINCI_MMC_DATADIR_WRITE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) struct dma_slave_config dma_tx_conf = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) .direction = DMA_MEM_TO_DEV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) .dst_addr = host->mem_res->start + DAVINCI_MMCDXR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) .dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) .dst_maxburst =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) rw_threshold / DMA_SLAVE_BUSWIDTH_4_BYTES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) chan = host->dma_tx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) dmaengine_slave_config(host->dma_tx, &dma_tx_conf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) desc = dmaengine_prep_slave_sg(host->dma_tx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) data->sg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) host->sg_len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) DMA_MEM_TO_DEV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) if (!desc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) dev_dbg(mmc_dev(host->mmc),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) "failed to allocate DMA TX descriptor");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) ret = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) struct dma_slave_config dma_rx_conf = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) .direction = DMA_DEV_TO_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) .src_addr = host->mem_res->start + DAVINCI_MMCDRR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) .src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) .src_maxburst =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) rw_threshold / DMA_SLAVE_BUSWIDTH_4_BYTES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) chan = host->dma_rx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) dmaengine_slave_config(host->dma_rx, &dma_rx_conf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) desc = dmaengine_prep_slave_sg(host->dma_rx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) data->sg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) host->sg_len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) DMA_DEV_TO_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) if (!desc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) dev_dbg(mmc_dev(host->mmc),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) "failed to allocate DMA RX descriptor");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) ret = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) dmaengine_submit(desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) dma_async_issue_pending(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) static int mmc_davinci_start_dma_transfer(struct mmc_davinci_host *host,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) struct mmc_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) int mask = rw_threshold - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) host->sg_len = dma_map_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) mmc_get_dma_dir(data));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) /* no individual DMA segment should need a partial FIFO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) for (i = 0; i < host->sg_len; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) if (sg_dma_len(data->sg + i) & mask) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) dma_unmap_sg(mmc_dev(host->mmc),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) data->sg, data->sg_len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) mmc_get_dma_dir(data));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) host->do_dma = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) ret = mmc_davinci_send_dma_request(host, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) static void davinci_release_dma_channels(struct mmc_davinci_host *host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) if (!host->use_dma)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) dma_release_channel(host->dma_tx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) dma_release_channel(host->dma_rx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) static int davinci_acquire_dma_channels(struct mmc_davinci_host *host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) host->dma_tx = dma_request_chan(mmc_dev(host->mmc), "tx");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) if (IS_ERR(host->dma_tx)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) dev_err(mmc_dev(host->mmc), "Can't get dma_tx channel\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) return PTR_ERR(host->dma_tx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) host->dma_rx = dma_request_chan(mmc_dev(host->mmc), "rx");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) if (IS_ERR(host->dma_rx)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) dev_err(mmc_dev(host->mmc), "Can't get dma_rx channel\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) dma_release_channel(host->dma_tx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) return PTR_ERR(host->dma_rx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) /*----------------------------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) mmc_davinci_prepare_data(struct mmc_davinci_host *host, struct mmc_request *req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) int fifo_lev = (rw_threshold == 32) ? MMCFIFOCTL_FIFOLEV : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) int timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) struct mmc_data *data = req->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) if (host->version == MMC_CTLR_VERSION_2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) fifo_lev = (rw_threshold == 64) ? MMCFIFOCTL_FIFOLEV : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) host->data = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) if (data == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) host->data_dir = DAVINCI_MMC_DATADIR_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) writel(0, host->base + DAVINCI_MMCBLEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) writel(0, host->base + DAVINCI_MMCNBLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) dev_dbg(mmc_dev(host->mmc), "%s, %d blocks of %d bytes\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) (data->flags & MMC_DATA_WRITE) ? "write" : "read",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) data->blocks, data->blksz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) dev_dbg(mmc_dev(host->mmc), " DTO %d cycles + %d ns\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) data->timeout_clks, data->timeout_ns);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) timeout = data->timeout_clks +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) (data->timeout_ns / host->ns_in_one_cycle);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) if (timeout > 0xffff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) timeout = 0xffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) writel(timeout, host->base + DAVINCI_MMCTOD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) writel(data->blocks, host->base + DAVINCI_MMCNBLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) writel(data->blksz, host->base + DAVINCI_MMCBLEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) /* Configure the FIFO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) if (data->flags & MMC_DATA_WRITE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) host->data_dir = DAVINCI_MMC_DATADIR_WRITE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) writel(fifo_lev | MMCFIFOCTL_FIFODIR_WR | MMCFIFOCTL_FIFORST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) host->base + DAVINCI_MMCFIFOCTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) writel(fifo_lev | MMCFIFOCTL_FIFODIR_WR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) host->base + DAVINCI_MMCFIFOCTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) host->data_dir = DAVINCI_MMC_DATADIR_READ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) writel(fifo_lev | MMCFIFOCTL_FIFODIR_RD | MMCFIFOCTL_FIFORST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) host->base + DAVINCI_MMCFIFOCTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) writel(fifo_lev | MMCFIFOCTL_FIFODIR_RD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) host->base + DAVINCI_MMCFIFOCTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) host->buffer = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) host->bytes_left = data->blocks * data->blksz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) /* For now we try to use DMA whenever we won't need partial FIFO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) * reads or writes, either for the whole transfer (as tested here)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) * or for any individual scatterlist segment (tested when we call
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) * start_dma_transfer).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) * While we *could* change that, unusual block sizes are rarely
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) * used. The occasional fallback to PIO should't hurt.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) if (host->use_dma && (host->bytes_left & (rw_threshold - 1)) == 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) && mmc_davinci_start_dma_transfer(host, data) == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) /* zero this to ensure we take no PIO paths */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) host->bytes_left = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) /* Revert to CPU Copy */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) host->sg_len = data->sg_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) host->sg = host->data->sg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) mmc_davinci_sg_to_buf(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) static void mmc_davinci_request(struct mmc_host *mmc, struct mmc_request *req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) struct mmc_davinci_host *host = mmc_priv(mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) unsigned long timeout = jiffies + msecs_to_jiffies(900);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) u32 mmcst1 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) /* Card may still be sending BUSY after a previous operation,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) * typically some kind of write. If so, we can't proceed yet.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) while (time_before(jiffies, timeout)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) mmcst1 = readl(host->base + DAVINCI_MMCST1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) if (!(mmcst1 & MMCST1_BUSY))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) cpu_relax();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) if (mmcst1 & MMCST1_BUSY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) dev_err(mmc_dev(host->mmc), "still BUSY? bad ... \n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) req->cmd->error = -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) mmc_request_done(mmc, req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) host->do_dma = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) mmc_davinci_prepare_data(host, req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) mmc_davinci_start_command(host, req->cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) static unsigned int calculate_freq_for_card(struct mmc_davinci_host *host,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) unsigned int mmc_req_freq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) unsigned int mmc_freq = 0, mmc_pclk = 0, mmc_push_pull_divisor = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) mmc_pclk = host->mmc_input_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) if (mmc_req_freq && mmc_pclk > (2 * mmc_req_freq))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) mmc_push_pull_divisor = ((unsigned int)mmc_pclk
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) / (2 * mmc_req_freq)) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) mmc_push_pull_divisor = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) mmc_freq = (unsigned int)mmc_pclk
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) / (2 * (mmc_push_pull_divisor + 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) if (mmc_freq > mmc_req_freq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) mmc_push_pull_divisor = mmc_push_pull_divisor + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) /* Convert ns to clock cycles */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) if (mmc_req_freq <= 400000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) host->ns_in_one_cycle = (1000000) / (((mmc_pclk
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) / (2 * (mmc_push_pull_divisor + 1)))/1000));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) host->ns_in_one_cycle = (1000000) / (((mmc_pclk
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) / (2 * (mmc_push_pull_divisor + 1)))/1000000));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) return mmc_push_pull_divisor;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) static void calculate_clk_divider(struct mmc_host *mmc, struct mmc_ios *ios)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) unsigned int open_drain_freq = 0, mmc_pclk = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) unsigned int mmc_push_pull_freq = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) struct mmc_davinci_host *host = mmc_priv(mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) u32 temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) /* Ignoring the init clock value passed for fixing the inter
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) * operability with different cards.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) open_drain_freq = ((unsigned int)mmc_pclk
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) / (2 * MMCSD_INIT_CLOCK)) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) if (open_drain_freq > 0xFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) open_drain_freq = 0xFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) temp = readl(host->base + DAVINCI_MMCCLK) & ~MMCCLK_CLKRT_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) temp |= open_drain_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) writel(temp, host->base + DAVINCI_MMCCLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) /* Convert ns to clock cycles */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) host->ns_in_one_cycle = (1000000) / (MMCSD_INIT_CLOCK/1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) u32 temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) mmc_push_pull_freq = calculate_freq_for_card(host, ios->clock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) if (mmc_push_pull_freq > 0xFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) mmc_push_pull_freq = 0xFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) temp = readl(host->base + DAVINCI_MMCCLK) & ~MMCCLK_CLKEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) writel(temp, host->base + DAVINCI_MMCCLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) udelay(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) temp = readl(host->base + DAVINCI_MMCCLK) & ~MMCCLK_CLKRT_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) temp |= mmc_push_pull_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) writel(temp, host->base + DAVINCI_MMCCLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) writel(temp | MMCCLK_CLKEN, host->base + DAVINCI_MMCCLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) udelay(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) static void mmc_davinci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) struct mmc_davinci_host *host = mmc_priv(mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) struct platform_device *pdev = to_platform_device(mmc->parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) struct davinci_mmc_config *config = pdev->dev.platform_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) dev_dbg(mmc_dev(host->mmc),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) "clock %dHz busmode %d powermode %d Vdd %04x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) ios->clock, ios->bus_mode, ios->power_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) ios->vdd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) switch (ios->power_mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) case MMC_POWER_OFF:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) if (config && config->set_power)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) config->set_power(pdev->id, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) case MMC_POWER_UP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) if (config && config->set_power)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) config->set_power(pdev->id, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) switch (ios->bus_width) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) case MMC_BUS_WIDTH_8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) dev_dbg(mmc_dev(host->mmc), "Enabling 8 bit mode\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) writel((readl(host->base + DAVINCI_MMCCTL) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) ~MMCCTL_WIDTH_4_BIT) | MMCCTL_WIDTH_8_BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) host->base + DAVINCI_MMCCTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) case MMC_BUS_WIDTH_4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) dev_dbg(mmc_dev(host->mmc), "Enabling 4 bit mode\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) if (host->version == MMC_CTLR_VERSION_2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) writel((readl(host->base + DAVINCI_MMCCTL) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) ~MMCCTL_WIDTH_8_BIT) | MMCCTL_WIDTH_4_BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) host->base + DAVINCI_MMCCTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) writel(readl(host->base + DAVINCI_MMCCTL) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) MMCCTL_WIDTH_4_BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) host->base + DAVINCI_MMCCTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) case MMC_BUS_WIDTH_1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) dev_dbg(mmc_dev(host->mmc), "Enabling 1 bit mode\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) if (host->version == MMC_CTLR_VERSION_2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) writel(readl(host->base + DAVINCI_MMCCTL) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) ~(MMCCTL_WIDTH_8_BIT | MMCCTL_WIDTH_4_BIT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) host->base + DAVINCI_MMCCTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) writel(readl(host->base + DAVINCI_MMCCTL) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) ~MMCCTL_WIDTH_4_BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) host->base + DAVINCI_MMCCTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) calculate_clk_divider(mmc, ios);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) host->bus_mode = ios->bus_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) if (ios->power_mode == MMC_POWER_UP) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) unsigned long timeout = jiffies + msecs_to_jiffies(50);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) bool lose = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) /* Send clock cycles, poll completion */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) writel(0, host->base + DAVINCI_MMCARGHL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) writel(MMCCMD_INITCK, host->base + DAVINCI_MMCCMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) while (time_before(jiffies, timeout)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) u32 tmp = readl(host->base + DAVINCI_MMCST0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) if (tmp & MMCST0_RSPDNE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) lose = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) cpu_relax();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) if (lose)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) dev_warn(mmc_dev(host->mmc), "powerup timeout\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) /* FIXME on power OFF, reset things ... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) mmc_davinci_xfer_done(struct mmc_davinci_host *host, struct mmc_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) host->data = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) if (host->mmc->caps & MMC_CAP_SDIO_IRQ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) * SDIO Interrupt Detection work-around as suggested by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) * Davinci Errata (TMS320DM355 Silicon Revision 1.1 Errata
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) * 2.1.6): Signal SDIO interrupt only if it is enabled by core
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) if (host->sdio_int && !(readl(host->base + DAVINCI_SDIOST0) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) SDIOST0_DAT1_HI)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) writel(SDIOIST_IOINT, host->base + DAVINCI_SDIOIST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) mmc_signal_sdio_irq(host->mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) if (host->do_dma) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) davinci_abort_dma(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) mmc_get_dma_dir(data));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) host->do_dma = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) host->data_dir = DAVINCI_MMC_DATADIR_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) if (!data->stop || (host->cmd && host->cmd->error)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) mmc_request_done(host->mmc, data->mrq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) writel(0, host->base + DAVINCI_MMCIM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) host->active_request = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) mmc_davinci_start_command(host, data->stop);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) static void mmc_davinci_cmd_done(struct mmc_davinci_host *host,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) struct mmc_command *cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) host->cmd = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) if (cmd->flags & MMC_RSP_PRESENT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) if (cmd->flags & MMC_RSP_136) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) /* response type 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) cmd->resp[3] = readl(host->base + DAVINCI_MMCRSP01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) cmd->resp[2] = readl(host->base + DAVINCI_MMCRSP23);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) cmd->resp[1] = readl(host->base + DAVINCI_MMCRSP45);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) cmd->resp[0] = readl(host->base + DAVINCI_MMCRSP67);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) /* response types 1, 1b, 3, 4, 5, 6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) cmd->resp[0] = readl(host->base + DAVINCI_MMCRSP67);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) if (host->data == NULL || cmd->error) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) if (cmd->error == -ETIMEDOUT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) cmd->mrq->cmd->retries = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) mmc_request_done(host->mmc, cmd->mrq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) writel(0, host->base + DAVINCI_MMCIM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) host->active_request = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) static inline void mmc_davinci_reset_ctrl(struct mmc_davinci_host *host,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) int val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) u32 temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) temp = readl(host->base + DAVINCI_MMCCTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) if (val) /* reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) temp |= MMCCTL_CMDRST | MMCCTL_DATRST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) else /* enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) temp &= ~(MMCCTL_CMDRST | MMCCTL_DATRST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) writel(temp, host->base + DAVINCI_MMCCTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) udelay(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) davinci_abort_data(struct mmc_davinci_host *host, struct mmc_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) mmc_davinci_reset_ctrl(host, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) mmc_davinci_reset_ctrl(host, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) static irqreturn_t mmc_davinci_sdio_irq(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) struct mmc_davinci_host *host = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) unsigned int status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) status = readl(host->base + DAVINCI_SDIOIST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) if (status & SDIOIST_IOINT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) dev_dbg(mmc_dev(host->mmc),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) "SDIO interrupt status %x\n", status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) writel(status | SDIOIST_IOINT, host->base + DAVINCI_SDIOIST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) mmc_signal_sdio_irq(host->mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) static irqreturn_t mmc_davinci_irq(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) struct mmc_davinci_host *host = (struct mmc_davinci_host *)dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) unsigned int status, qstatus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) int end_command = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) int end_transfer = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) struct mmc_data *data = host->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) if (host->cmd == NULL && host->data == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) status = readl(host->base + DAVINCI_MMCST0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) dev_dbg(mmc_dev(host->mmc),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) "Spurious interrupt 0x%04x\n", status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) /* Disable the interrupt from mmcsd */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) writel(0, host->base + DAVINCI_MMCIM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) status = readl(host->base + DAVINCI_MMCST0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) qstatus = status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) /* handle FIFO first when using PIO for data.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) * bytes_left will decrease to zero as I/O progress and status will
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) * read zero over iteration because this controller status
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) * register(MMCST0) reports any status only once and it is cleared
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) * by read. So, it is not unbouned loop even in the case of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) * non-dma.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) if (host->bytes_left && (status & (MMCST0_DXRDY | MMCST0_DRRDY))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) unsigned long im_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) * If interrupts fire during the following loop, they will be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) * handled by the handler, but the PIC will still buffer these.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) * As a result, the handler will be called again to serve these
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) * needlessly. In order to avoid these spurious interrupts,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) * keep interrupts masked during the loop.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) im_val = readl(host->base + DAVINCI_MMCIM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) writel(0, host->base + DAVINCI_MMCIM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) davinci_fifo_data_trans(host, rw_threshold);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) status = readl(host->base + DAVINCI_MMCST0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) qstatus |= status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) } while (host->bytes_left &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) (status & (MMCST0_DXRDY | MMCST0_DRRDY)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) * If an interrupt is pending, it is assumed it will fire when
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) * it is unmasked. This assumption is also taken when the MMCIM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) * is first set. Otherwise, writing to MMCIM after reading the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) * status is race-prone.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) writel(im_val, host->base + DAVINCI_MMCIM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) if (qstatus & MMCST0_DATDNE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) /* All blocks sent/received, and CRC checks passed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) if (data != NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) if ((host->do_dma == 0) && (host->bytes_left > 0)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) /* if datasize < rw_threshold
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) * no RX ints are generated
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) davinci_fifo_data_trans(host, host->bytes_left);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) end_transfer = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) data->bytes_xfered = data->blocks * data->blksz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) dev_err(mmc_dev(host->mmc),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) "DATDNE with no host->data\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) if (qstatus & MMCST0_TOUTRD) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) /* Read data timeout */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) data->error = -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) end_transfer = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) dev_dbg(mmc_dev(host->mmc),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) "read data timeout, status %x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) qstatus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) davinci_abort_data(host, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) if (qstatus & (MMCST0_CRCWR | MMCST0_CRCRD)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) /* Data CRC error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) data->error = -EILSEQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) end_transfer = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) /* NOTE: this controller uses CRCWR to report both CRC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) * errors and timeouts (on writes). MMCDRSP values are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) * only weakly documented, but 0x9f was clearly a timeout
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) * case and the two three-bit patterns in various SD specs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) * (101, 010) aren't part of it ...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) if (qstatus & MMCST0_CRCWR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) u32 temp = readb(host->base + DAVINCI_MMCDRSP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) if (temp == 0x9f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) data->error = -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) dev_dbg(mmc_dev(host->mmc), "data %s %s error\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) (qstatus & MMCST0_CRCWR) ? "write" : "read",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) (data->error == -ETIMEDOUT) ? "timeout" : "CRC");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) davinci_abort_data(host, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) if (qstatus & MMCST0_TOUTRS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) /* Command timeout */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) if (host->cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) dev_dbg(mmc_dev(host->mmc),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) "CMD%d timeout, status %x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) host->cmd->opcode, qstatus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) host->cmd->error = -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) if (data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) end_transfer = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) davinci_abort_data(host, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) end_command = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) if (qstatus & MMCST0_CRCRS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) /* Command CRC error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) dev_dbg(mmc_dev(host->mmc), "Command CRC error\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) if (host->cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) host->cmd->error = -EILSEQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) end_command = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) if (qstatus & MMCST0_RSPDNE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) /* End of command phase */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) end_command = host->cmd ? 1 : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) if (end_command)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) mmc_davinci_cmd_done(host, host->cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) if (end_transfer)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) mmc_davinci_xfer_done(host, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) static int mmc_davinci_get_cd(struct mmc_host *mmc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) struct platform_device *pdev = to_platform_device(mmc->parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) struct davinci_mmc_config *config = pdev->dev.platform_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) if (config && config->get_cd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) return config->get_cd(pdev->id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) return mmc_gpio_get_cd(mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) static int mmc_davinci_get_ro(struct mmc_host *mmc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) struct platform_device *pdev = to_platform_device(mmc->parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) struct davinci_mmc_config *config = pdev->dev.platform_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) if (config && config->get_ro)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) return config->get_ro(pdev->id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) return mmc_gpio_get_ro(mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) static void mmc_davinci_enable_sdio_irq(struct mmc_host *mmc, int enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) struct mmc_davinci_host *host = mmc_priv(mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) if (enable) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) if (!(readl(host->base + DAVINCI_SDIOST0) & SDIOST0_DAT1_HI)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) writel(SDIOIST_IOINT, host->base + DAVINCI_SDIOIST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) mmc_signal_sdio_irq(host->mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) host->sdio_int = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) writel(readl(host->base + DAVINCI_SDIOIEN) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) SDIOIEN_IOINTEN, host->base + DAVINCI_SDIOIEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) host->sdio_int = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) writel(readl(host->base + DAVINCI_SDIOIEN) & ~SDIOIEN_IOINTEN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) host->base + DAVINCI_SDIOIEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) static const struct mmc_host_ops mmc_davinci_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) .request = mmc_davinci_request,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) .set_ios = mmc_davinci_set_ios,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) .get_cd = mmc_davinci_get_cd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) .get_ro = mmc_davinci_get_ro,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) .enable_sdio_irq = mmc_davinci_enable_sdio_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) /*----------------------------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) #ifdef CONFIG_CPU_FREQ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) static int mmc_davinci_cpufreq_transition(struct notifier_block *nb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) unsigned long val, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) struct mmc_davinci_host *host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) unsigned int mmc_pclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) struct mmc_host *mmc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) host = container_of(nb, struct mmc_davinci_host, freq_transition);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) mmc = host->mmc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) mmc_pclk = clk_get_rate(host->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) if (val == CPUFREQ_POSTCHANGE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) spin_lock_irqsave(&mmc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) host->mmc_input_clk = mmc_pclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) calculate_clk_divider(mmc, &mmc->ios);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) spin_unlock_irqrestore(&mmc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) static inline int mmc_davinci_cpufreq_register(struct mmc_davinci_host *host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) host->freq_transition.notifier_call = mmc_davinci_cpufreq_transition;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) return cpufreq_register_notifier(&host->freq_transition,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) CPUFREQ_TRANSITION_NOTIFIER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) static inline void mmc_davinci_cpufreq_deregister(struct mmc_davinci_host *host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) cpufreq_unregister_notifier(&host->freq_transition,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) CPUFREQ_TRANSITION_NOTIFIER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) static inline int mmc_davinci_cpufreq_register(struct mmc_davinci_host *host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) static inline void mmc_davinci_cpufreq_deregister(struct mmc_davinci_host *host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) static void init_mmcsd_host(struct mmc_davinci_host *host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) mmc_davinci_reset_ctrl(host, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) writel(0, host->base + DAVINCI_MMCCLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) writel(MMCCLK_CLKEN, host->base + DAVINCI_MMCCLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) writel(0x1FFF, host->base + DAVINCI_MMCTOR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) writel(0xFFFF, host->base + DAVINCI_MMCTOD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) mmc_davinci_reset_ctrl(host, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) static const struct platform_device_id davinci_mmc_devtype[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) .name = "dm6441-mmc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) .driver_data = MMC_CTLR_VERSION_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) .name = "da830-mmc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) .driver_data = MMC_CTLR_VERSION_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) MODULE_DEVICE_TABLE(platform, davinci_mmc_devtype);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) static const struct of_device_id davinci_mmc_dt_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) .compatible = "ti,dm6441-mmc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) .data = &davinci_mmc_devtype[MMC_CTLR_VERSION_1],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) .compatible = "ti,da830-mmc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) .data = &davinci_mmc_devtype[MMC_CTLR_VERSION_2],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) MODULE_DEVICE_TABLE(of, davinci_mmc_dt_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) static int mmc_davinci_parse_pdata(struct mmc_host *mmc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) struct platform_device *pdev = to_platform_device(mmc->parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) struct davinci_mmc_config *pdata = pdev->dev.platform_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) struct mmc_davinci_host *host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) if (!pdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) host = mmc_priv(mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) if (!host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) if (pdata && pdata->nr_sg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) host->nr_sg = pdata->nr_sg - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) if (pdata && (pdata->wires == 4 || pdata->wires == 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) mmc->caps |= MMC_CAP_4_BIT_DATA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) if (pdata && (pdata->wires == 8))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) mmc->caps |= (MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) mmc->f_min = 312500;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) mmc->f_max = 25000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) if (pdata && pdata->max_freq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) mmc->f_max = pdata->max_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) if (pdata && pdata->caps)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) mmc->caps |= pdata->caps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) /* Register a cd gpio, if there is not one, enable polling */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) ret = mmc_gpiod_request_cd(mmc, "cd", 0, false, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) if (ret == -EPROBE_DEFER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) else if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) mmc->caps |= MMC_CAP_NEEDS_POLL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) ret = mmc_gpiod_request_ro(mmc, "wp", 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) if (ret == -EPROBE_DEFER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) static int davinci_mmcsd_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) const struct of_device_id *match;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) struct mmc_davinci_host *host = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) struct mmc_host *mmc = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) struct resource *r, *mem = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) int ret, irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) size_t mem_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) const struct platform_device_id *id_entry;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) if (!r)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) irq = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) if (irq < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) return irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) mem_size = resource_size(r);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) mem = devm_request_mem_region(&pdev->dev, r->start, mem_size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) pdev->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) if (!mem)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) mmc = mmc_alloc_host(sizeof(struct mmc_davinci_host), &pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) if (!mmc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) host = mmc_priv(mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) host->mmc = mmc; /* Important */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) host->mem_res = mem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) host->base = devm_ioremap(&pdev->dev, mem->start, mem_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) if (!host->base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) goto ioremap_fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) host->clk = devm_clk_get(&pdev->dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) if (IS_ERR(host->clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) ret = PTR_ERR(host->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) goto clk_get_fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) ret = clk_prepare_enable(host->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) goto clk_prepare_enable_fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) host->mmc_input_clk = clk_get_rate(host->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) match = of_match_device(davinci_mmc_dt_ids, &pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) if (match) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) pdev->id_entry = match->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) ret = mmc_of_parse(mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) dev_err_probe(&pdev->dev, ret,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) "could not parse of data\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) goto parse_fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) ret = mmc_davinci_parse_pdata(mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) dev_err(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) "could not parse platform data: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) goto parse_fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) } }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) if (host->nr_sg > MAX_NR_SG || !host->nr_sg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) host->nr_sg = MAX_NR_SG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) init_mmcsd_host(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) host->use_dma = use_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) host->mmc_irq = irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) host->sdio_irq = platform_get_irq(pdev, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) if (host->use_dma) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) ret = davinci_acquire_dma_channels(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) if (ret == -EPROBE_DEFER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) goto dma_probe_defer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) else if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) host->use_dma = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) mmc->caps |= MMC_CAP_WAIT_WHILE_BUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) id_entry = platform_get_device_id(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) if (id_entry)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) host->version = id_entry->driver_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) mmc->ops = &mmc_davinci_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) /* With no iommu coalescing pages, each phys_seg is a hw_seg.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) * Each hw_seg uses one EDMA parameter RAM slot, always one
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) * channel and then usually some linked slots.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) mmc->max_segs = MAX_NR_SG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) /* EDMA limit per hw segment (one or two MBytes) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) mmc->max_seg_size = MAX_CCNT * rw_threshold;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) /* MMC/SD controller limits for multiblock requests */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) mmc->max_blk_size = 4095; /* BLEN is 12 bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) mmc->max_blk_count = 65535; /* NBLK is 16 bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) dev_dbg(mmc_dev(host->mmc), "max_segs=%d\n", mmc->max_segs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) dev_dbg(mmc_dev(host->mmc), "max_blk_size=%d\n", mmc->max_blk_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) dev_dbg(mmc_dev(host->mmc), "max_req_size=%d\n", mmc->max_req_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) dev_dbg(mmc_dev(host->mmc), "max_seg_size=%d\n", mmc->max_seg_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) platform_set_drvdata(pdev, host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) ret = mmc_davinci_cpufreq_register(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) dev_err(&pdev->dev, "failed to register cpufreq\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) goto cpu_freq_fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) ret = mmc_add_host(mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) goto mmc_add_host_fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) ret = devm_request_irq(&pdev->dev, irq, mmc_davinci_irq, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) mmc_hostname(mmc), host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) goto request_irq_fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) if (host->sdio_irq >= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) ret = devm_request_irq(&pdev->dev, host->sdio_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) mmc_davinci_sdio_irq, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) mmc_hostname(mmc), host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) mmc->caps |= MMC_CAP_SDIO_IRQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) rename_region(mem, mmc_hostname(mmc));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) dev_info(mmc_dev(host->mmc), "Using %s, %d-bit mode\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) host->use_dma ? "DMA" : "PIO",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) (mmc->caps & MMC_CAP_4_BIT_DATA) ? 4 : 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) request_irq_fail:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) mmc_remove_host(mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) mmc_add_host_fail:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) mmc_davinci_cpufreq_deregister(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) cpu_freq_fail:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) davinci_release_dma_channels(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) parse_fail:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) dma_probe_defer:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) clk_disable_unprepare(host->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) clk_prepare_enable_fail:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) clk_get_fail:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) ioremap_fail:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) mmc_free_host(mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) static int __exit davinci_mmcsd_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) struct mmc_davinci_host *host = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) mmc_remove_host(host->mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) mmc_davinci_cpufreq_deregister(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) davinci_release_dma_channels(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) clk_disable_unprepare(host->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) mmc_free_host(host->mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) #ifdef CONFIG_PM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) static int davinci_mmcsd_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) struct mmc_davinci_host *host = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) writel(0, host->base + DAVINCI_MMCIM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) mmc_davinci_reset_ctrl(host, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) clk_disable(host->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) static int davinci_mmcsd_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) struct mmc_davinci_host *host = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) ret = clk_enable(host->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) mmc_davinci_reset_ctrl(host, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) static const struct dev_pm_ops davinci_mmcsd_pm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) .suspend = davinci_mmcsd_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) .resume = davinci_mmcsd_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) #define davinci_mmcsd_pm_ops (&davinci_mmcsd_pm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) #define davinci_mmcsd_pm_ops NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) static struct platform_driver davinci_mmcsd_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) .name = "davinci_mmc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) .probe_type = PROBE_PREFER_ASYNCHRONOUS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) .pm = davinci_mmcsd_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) .of_match_table = davinci_mmc_dt_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) .probe = davinci_mmcsd_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) .remove = __exit_p(davinci_mmcsd_remove),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) .id_table = davinci_mmc_devtype,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) module_platform_driver(davinci_mmcsd_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) MODULE_AUTHOR("Texas Instruments India");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) MODULE_DESCRIPTION("MMC/SD driver for Davinci MMC controller");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) MODULE_ALIAS("platform:davinci_mmc");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417)
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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