Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /* Copyright (c) 2015, The Linux Foundation. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4) #ifndef LINUX_MMC_CQHCI_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5) #define LINUX_MMC_CQHCI_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) #include <linux/compiler.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #include <linux/bitops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/spinlock_types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/completion.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/wait.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/irqreturn.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <asm/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) /* registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) /* version */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #define CQHCI_VER			0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #define CQHCI_VER_MAJOR(x)		(((x) & GENMASK(11, 8)) >> 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #define CQHCI_VER_MINOR1(x)		(((x) & GENMASK(7, 4)) >> 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #define CQHCI_VER_MINOR2(x)		((x) & GENMASK(3, 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) /* capabilities */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #define CQHCI_CAP			0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #define CQHCI_CAP_CS			0x10000000 /* Crypto Support */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) /* configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define CQHCI_CFG			0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define CQHCI_DCMD			0x00001000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define CQHCI_TASK_DESC_SZ		0x00000100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define CQHCI_CRYPTO_GENERAL_ENABLE	0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define CQHCI_ENABLE			0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) /* control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define CQHCI_CTL			0x0C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define CQHCI_CLEAR_ALL_TASKS		0x00000100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define CQHCI_HALT			0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) /* interrupt status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #define CQHCI_IS			0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #define CQHCI_IS_HAC			BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #define CQHCI_IS_TCC			BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #define CQHCI_IS_RED			BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #define CQHCI_IS_TCL			BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) #define CQHCI_IS_GCE			BIT(4) /* General Crypto Error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) #define CQHCI_IS_ICCE			BIT(5) /* Invalid Crypto Config Error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) #define CQHCI_IS_MASK (CQHCI_IS_TCC | CQHCI_IS_RED | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 		       CQHCI_IS_GCE | CQHCI_IS_ICCE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) /* interrupt status enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) #define CQHCI_ISTE			0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) /* interrupt signal enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) #define CQHCI_ISGE			0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) /* interrupt coalescing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) #define CQHCI_IC			0x1C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) #define CQHCI_IC_ENABLE			BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) #define CQHCI_IC_RESET			BIT(16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) #define CQHCI_IC_ICCTHWEN		BIT(15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) #define CQHCI_IC_ICCTH(x)		(((x) & 0x1F) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) #define CQHCI_IC_ICTOVALWEN		BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) #define CQHCI_IC_ICTOVAL(x)		((x) & 0x7F)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) /* task list base address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) #define CQHCI_TDLBA			0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) /* task list base address upper */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) #define CQHCI_TDLBAU			0x24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) /* door-bell */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) #define CQHCI_TDBR			0x28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) /* task completion notification */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) #define CQHCI_TCN			0x2C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) /* device queue status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) #define CQHCI_DQS			0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) /* device pending tasks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) #define CQHCI_DPT			0x34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) /* task clear */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) #define CQHCI_TCLR			0x38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) /* task descriptor processing error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) #define CQHCI_TDPE			0x3c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) /* send status config 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) #define CQHCI_SSC1			0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) #define CQHCI_SSC1_CBC_MASK		GENMASK(19, 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) /* send status config 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) #define CQHCI_SSC2			0x44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) /* response for dcmd */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) #define CQHCI_CRDCT			0x48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) /* response mode error mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define CQHCI_RMEM			0x50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) /* task error info */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define CQHCI_TERRI			0x54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define CQHCI_TERRI_C_INDEX(x)		((x) & GENMASK(5, 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define CQHCI_TERRI_C_TASK(x)		(((x) & GENMASK(12, 8)) >> 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define CQHCI_TERRI_C_VALID(x)		((x) & BIT(15))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define CQHCI_TERRI_D_INDEX(x)		(((x) & GENMASK(21, 16)) >> 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define CQHCI_TERRI_D_TASK(x)		(((x) & GENMASK(28, 24)) >> 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define CQHCI_TERRI_D_VALID(x)		((x) & BIT(31))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) /* command response index */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define CQHCI_CRI			0x58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) /* command response argument */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define CQHCI_CRA			0x5C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) /* crypto capabilities */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define CQHCI_CCAP			0x100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define CQHCI_CRYPTOCAP			0x104
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define CQHCI_INT_ALL			0xF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define CQHCI_IC_DEFAULT_ICCTH		31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define CQHCI_IC_DEFAULT_ICTOVAL	1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) /* attribute fields */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define CQHCI_VALID(x)			(((x) & 1) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define CQHCI_END(x)			(((x) & 1) << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define CQHCI_INT(x)			(((x) & 1) << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define CQHCI_ACT(x)			(((x) & 0x7) << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) /* data command task descriptor fields */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define CQHCI_FORCED_PROG(x)		(((x) & 1) << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define CQHCI_CONTEXT(x)		(((x) & 0xF) << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define CQHCI_DATA_TAG(x)		(((x) & 1) << 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define CQHCI_DATA_DIR(x)		(((x) & 1) << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define CQHCI_PRIORITY(x)		(((x) & 1) << 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define CQHCI_QBAR(x)			(((x) & 1) << 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define CQHCI_REL_WRITE(x)		(((x) & 1) << 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define CQHCI_BLK_COUNT(x)		(((x) & 0xFFFF) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define CQHCI_BLK_ADDR(x)		(((x) & 0xFFFFFFFF) << 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) /* direct command task descriptor fields */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define CQHCI_CMD_INDEX(x)		(((x) & 0x3F) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define CQHCI_CMD_TIMING(x)		(((x) & 1) << 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define CQHCI_RESP_TYPE(x)		(((x) & 0x3) << 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) /* crypto task descriptor fields (for bits 64-127 of task descriptor) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define CQHCI_CRYPTO_ENABLE_BIT		(1ULL << 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define CQHCI_CRYPTO_KEYSLOT(x)		((u64)(x) << 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) /* transfer descriptor fields */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define CQHCI_DAT_LENGTH(x)		(((x) & 0xFFFF) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define CQHCI_DAT_ADDR_LO(x)		(((x) & 0xFFFFFFFF) << 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define CQHCI_DAT_ADDR_HI(x)		(((x) & 0xFFFFFFFF) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) /* CCAP - Crypto Capability 100h */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) union cqhci_crypto_capabilities {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	__le32 reg_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 		u8 num_crypto_cap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 		u8 config_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 		u8 reserved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 		u8 config_array_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) enum cqhci_crypto_key_size {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	CQHCI_CRYPTO_KEY_SIZE_INVALID	= 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	CQHCI_CRYPTO_KEY_SIZE_128	= 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	CQHCI_CRYPTO_KEY_SIZE_192	= 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	CQHCI_CRYPTO_KEY_SIZE_256	= 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	CQHCI_CRYPTO_KEY_SIZE_512	= 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) enum cqhci_crypto_alg {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	CQHCI_CRYPTO_ALG_AES_XTS		= 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	CQHCI_CRYPTO_ALG_BITLOCKER_AES_CBC	= 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	CQHCI_CRYPTO_ALG_AES_ECB		= 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	CQHCI_CRYPTO_ALG_ESSIV_AES_CBC		= 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) /* x-CRYPTOCAP - Crypto Capability X */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) union cqhci_crypto_cap_entry {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	__le32 reg_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 		u8 algorithm_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 		u8 sdus_mask; /* Supported data unit size mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 		u8 key_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 		u8 reserved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define CQHCI_CRYPTO_CONFIGURATION_ENABLE (1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define CQHCI_CRYPTO_KEY_MAX_SIZE 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) /* x-CRYPTOCFG - Crypto Configuration X */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) union cqhci_crypto_cfg_entry {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	__le32 reg_val[32];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 		u8 crypto_key[CQHCI_CRYPTO_KEY_MAX_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 		u8 data_unit_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 		u8 crypto_cap_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 		u8 reserved_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 		u8 config_enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 		u8 reserved_multi_host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 		u8 reserved_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 		u8 vsb[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 		u8 reserved_3[56];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) struct cqhci_host_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) struct mmc_host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) struct mmc_request;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) struct cqhci_slot;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) struct cqhci_host {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	const struct cqhci_host_ops *ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	void __iomem *mmio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	struct mmc_host *mmc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 	spinlock_t lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 	/* relative card address of device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 	unsigned int rca;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 	/* 64 bit DMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	bool dma64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 	int num_slots;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 	int qcnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 	u32 dcmd_slot;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 	u32 caps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) #define CQHCI_TASK_DESC_SZ_128		0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 	u32 quirks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) #define CQHCI_QUIRK_SHORT_TXFR_DESC_SZ	0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 	bool enabled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 	bool halted;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 	bool init_done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 	bool activated;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 	bool waiting_for_idle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 	bool recovery_halt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 	size_t desc_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 	size_t data_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 	u8 *desc_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 	/* total descriptor size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 	u8 slot_sz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 	/* 64/128 bit depends on CQHCI_CFG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 	u8 task_desc_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 	/* 64 bit on 32-bit arch, 128 bit on 64-bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 	u8 link_desc_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 	u8 *trans_desc_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 	/* same length as transfer descriptor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 	u8 trans_desc_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 	dma_addr_t desc_dma_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 	dma_addr_t trans_desc_dma_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 	struct completion halt_comp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 	wait_queue_head_t wait_queue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 	struct cqhci_slot *slot;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) #ifdef CONFIG_MMC_CRYPTO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 	union cqhci_crypto_capabilities crypto_capabilities;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 	union cqhci_crypto_cap_entry *crypto_cap_array;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 	u32 crypto_cfg_register;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) struct cqhci_host_ops {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 	void (*dumpregs)(struct mmc_host *mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 	void (*write_l)(struct cqhci_host *host, u32 val, int reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 	u32 (*read_l)(struct cqhci_host *host, int reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 	void (*enable)(struct mmc_host *mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 	void (*disable)(struct mmc_host *mmc, bool recovery);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 	void (*update_dcmd_desc)(struct mmc_host *mmc, struct mmc_request *mrq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 				 u64 *data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 	void (*pre_enable)(struct mmc_host *mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 	void (*post_disable)(struct mmc_host *mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) #ifdef CONFIG_MMC_CRYPTO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 	int (*program_key)(struct cqhci_host *cq_host,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 			   const union cqhci_crypto_cfg_entry *cfg, int slot);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) static inline void cqhci_writel(struct cqhci_host *host, u32 val, int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 	if (unlikely(host->ops->write_l))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 		host->ops->write_l(host, val, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 		writel_relaxed(val, host->mmio + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) static inline u32 cqhci_readl(struct cqhci_host *host, int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 	if (unlikely(host->ops->read_l))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 		return host->ops->read_l(host, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 		return readl_relaxed(host->mmio + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) struct platform_device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) irqreturn_t cqhci_irq(struct mmc_host *mmc, u32 intmask, int cmd_error,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 		      int data_error);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) int cqhci_init(struct cqhci_host *cq_host, struct mmc_host *mmc, bool dma64);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) struct cqhci_host *cqhci_pltfm_init(struct platform_device *pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) int cqhci_deactivate(struct mmc_host *mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) static inline int cqhci_suspend(struct mmc_host *mmc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 	return cqhci_deactivate(mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) int cqhci_resume(struct mmc_host *mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) #endif