^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * CQHCI crypto engine (inline encryption) support
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright 2020 Google LLC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/blk-crypto.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/keyslot-manager.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/mmc/host.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include "cqhci-crypto.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) /* Map from blk-crypto modes to CQHCI crypto algorithm IDs and key sizes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) static const struct cqhci_crypto_alg_entry {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) enum cqhci_crypto_alg alg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) enum cqhci_crypto_key_size key_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) } cqhci_crypto_algs[BLK_ENCRYPTION_MODE_MAX] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) [BLK_ENCRYPTION_MODE_AES_256_XTS] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) .alg = CQHCI_CRYPTO_ALG_AES_XTS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) .key_size = CQHCI_CRYPTO_KEY_SIZE_256,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) static inline struct cqhci_host *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) cqhci_host_from_ksm(struct blk_keyslot_manager *ksm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) struct mmc_host *mmc = container_of(ksm, struct mmc_host, ksm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) return mmc->cqe_private;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) static int cqhci_crypto_program_key(struct cqhci_host *cq_host,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) const union cqhci_crypto_cfg_entry *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) int slot)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) u32 slot_offset = cq_host->crypto_cfg_register + slot * sizeof(*cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) if (cq_host->ops->program_key)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) return cq_host->ops->program_key(cq_host, cfg, slot);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) /* Clear CFGE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) cqhci_writel(cq_host, 0, slot_offset + 16 * sizeof(cfg->reg_val[0]));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) /* Write the key */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) for (i = 0; i < 16; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) cqhci_writel(cq_host, le32_to_cpu(cfg->reg_val[i]),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) slot_offset + i * sizeof(cfg->reg_val[0]));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) /* Write dword 17 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) cqhci_writel(cq_host, le32_to_cpu(cfg->reg_val[17]),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) slot_offset + 17 * sizeof(cfg->reg_val[0]));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) /* Write dword 16, which includes the new value of CFGE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) cqhci_writel(cq_host, le32_to_cpu(cfg->reg_val[16]),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) slot_offset + 16 * sizeof(cfg->reg_val[0]));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) static int cqhci_crypto_keyslot_program(struct blk_keyslot_manager *ksm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) const struct blk_crypto_key *key,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) unsigned int slot)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) struct cqhci_host *cq_host = cqhci_host_from_ksm(ksm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) const union cqhci_crypto_cap_entry *ccap_array =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) cq_host->crypto_cap_array;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) const struct cqhci_crypto_alg_entry *alg =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) &cqhci_crypto_algs[key->crypto_cfg.crypto_mode];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) u8 data_unit_mask = key->crypto_cfg.data_unit_size / 512;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) int cap_idx = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) union cqhci_crypto_cfg_entry cfg = {};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) BUILD_BUG_ON(CQHCI_CRYPTO_KEY_SIZE_INVALID != 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) for (i = 0; i < cq_host->crypto_capabilities.num_crypto_cap; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) if (ccap_array[i].algorithm_id == alg->alg &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) ccap_array[i].key_size == alg->key_size &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) (ccap_array[i].sdus_mask & data_unit_mask)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) cap_idx = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) if (WARN_ON(cap_idx < 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) return -EOPNOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) cfg.data_unit_size = data_unit_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) cfg.crypto_cap_idx = cap_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) cfg.config_enable = CQHCI_CRYPTO_CONFIGURATION_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) if (ccap_array[cap_idx].algorithm_id == CQHCI_CRYPTO_ALG_AES_XTS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) /* In XTS mode, the blk_crypto_key's size is already doubled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) memcpy(cfg.crypto_key, key->raw, key->size/2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) memcpy(cfg.crypto_key + CQHCI_CRYPTO_KEY_MAX_SIZE/2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) key->raw + key->size/2, key->size/2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) memcpy(cfg.crypto_key, key->raw, key->size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) err = cqhci_crypto_program_key(cq_host, &cfg, slot);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) memzero_explicit(&cfg, sizeof(cfg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) static int cqhci_crypto_clear_keyslot(struct cqhci_host *cq_host, int slot)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) * Clear the crypto cfg on the device. Clearing CFGE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) * might not be sufficient, so just clear the entire cfg.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) union cqhci_crypto_cfg_entry cfg = {};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) return cqhci_crypto_program_key(cq_host, &cfg, slot);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) static int cqhci_crypto_keyslot_evict(struct blk_keyslot_manager *ksm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) const struct blk_crypto_key *key,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) unsigned int slot)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) struct cqhci_host *cq_host = cqhci_host_from_ksm(ksm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) return cqhci_crypto_clear_keyslot(cq_host, slot);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) * The keyslot management operations for CQHCI crypto.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) * Note that the block layer ensures that these are never called while the host
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) * controller is runtime-suspended. However, the CQE won't necessarily be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) * "enabled" when these are called, i.e. CQHCI_ENABLE might not be set in the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) * CQHCI_CFG register. But the hardware allows that.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) static const struct blk_ksm_ll_ops cqhci_ksm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) .keyslot_program = cqhci_crypto_keyslot_program,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) .keyslot_evict = cqhci_crypto_keyslot_evict,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) static enum blk_crypto_mode_num
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) cqhci_find_blk_crypto_mode(union cqhci_crypto_cap_entry cap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) for (i = 0; i < ARRAY_SIZE(cqhci_crypto_algs); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) BUILD_BUG_ON(CQHCI_CRYPTO_KEY_SIZE_INVALID != 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) if (cqhci_crypto_algs[i].alg == cap.algorithm_id &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) cqhci_crypto_algs[i].key_size == cap.key_size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) return i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) return BLK_ENCRYPTION_MODE_INVALID;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) * cqhci_crypto_init - initialize CQHCI crypto support
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) * @cq_host: a cqhci host
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) * If the driver previously set MMC_CAP2_CRYPTO and the CQE declares
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) * CQHCI_CAP_CS, initialize the crypto support. This involves reading the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) * crypto capability registers, initializing the keyslot manager, clearing all
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) * keyslots, and enabling 128-bit task descriptors.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) * Return: 0 if crypto was initialized or isn't supported; whether
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) * MMC_CAP2_CRYPTO remains set indicates which one of those cases it is.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) * Also can return a negative errno value on unexpected error.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) int cqhci_crypto_init(struct cqhci_host *cq_host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) struct mmc_host *mmc = cq_host->mmc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) struct device *dev = mmc_dev(mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) struct blk_keyslot_manager *ksm = &mmc->ksm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) unsigned int num_keyslots;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) unsigned int cap_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) enum blk_crypto_mode_num blk_mode_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) unsigned int slot;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) int err = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) if (!(mmc->caps2 & MMC_CAP2_CRYPTO) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) !(cqhci_readl(cq_host, CQHCI_CAP) & CQHCI_CAP_CS))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) cq_host->crypto_capabilities.reg_val =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) cpu_to_le32(cqhci_readl(cq_host, CQHCI_CCAP));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) cq_host->crypto_cfg_register =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) (u32)cq_host->crypto_capabilities.config_array_ptr * 0x100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) cq_host->crypto_cap_array =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) devm_kcalloc(dev, cq_host->crypto_capabilities.num_crypto_cap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) sizeof(cq_host->crypto_cap_array[0]), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) if (!cq_host->crypto_cap_array) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) err = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) * CCAP.CFGC is off by one, so the actual number of crypto
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) * configurations (a.k.a. keyslots) is CCAP.CFGC + 1.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) num_keyslots = cq_host->crypto_capabilities.config_count + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) err = devm_blk_ksm_init(dev, ksm, num_keyslots);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) ksm->ksm_ll_ops = cqhci_ksm_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) ksm->dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) /* Unfortunately, CQHCI crypto only supports 32 DUN bits. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) ksm->max_dun_bytes_supported = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) ksm->features = BLK_CRYPTO_FEATURE_STANDARD_KEYS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) * Cache all the crypto capabilities and advertise the supported crypto
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) * modes and data unit sizes to the block layer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) for (cap_idx = 0; cap_idx < cq_host->crypto_capabilities.num_crypto_cap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) cap_idx++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) cq_host->crypto_cap_array[cap_idx].reg_val =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) cpu_to_le32(cqhci_readl(cq_host,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) CQHCI_CRYPTOCAP +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) cap_idx * sizeof(__le32)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) blk_mode_num = cqhci_find_blk_crypto_mode(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) cq_host->crypto_cap_array[cap_idx]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) if (blk_mode_num == BLK_ENCRYPTION_MODE_INVALID)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) ksm->crypto_modes_supported[blk_mode_num] |=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) cq_host->crypto_cap_array[cap_idx].sdus_mask * 512;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) /* Clear all the keyslots so that we start in a known state. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) for (slot = 0; slot < num_keyslots; slot++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) cqhci_crypto_clear_keyslot(cq_host, slot);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) /* CQHCI crypto requires the use of 128-bit task descriptors. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) cq_host->caps |= CQHCI_TASK_DESC_SZ_128;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) mmc->caps2 &= ~MMC_CAP2_CRYPTO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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