^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * cb710/cb710-mmc.h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright by Michał Mirosław, 2008-2009
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #ifndef LINUX_CB710_MMC_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #define LINUX_CB710_MMC_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/cb710.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) /* per-MMC-reader structure */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) struct cb710_mmc_reader {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) struct tasklet_struct finish_req_tasklet;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) struct mmc_request *mrq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) spinlock_t irq_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) unsigned char last_power_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) /* some device struct walking */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) static inline struct mmc_host *cb710_slot_to_mmc(struct cb710_slot *slot)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) return platform_get_drvdata(&slot->pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) static inline struct cb710_slot *cb710_mmc_to_slot(struct mmc_host *mmc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) struct platform_device *pdev = to_platform_device(mmc_dev(mmc));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) return cb710_pdev_to_slot(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) /* registers (this might be all wrong ;) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define CB710_MMC_DATA_PORT 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define CB710_MMC_CONFIG_PORT 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define CB710_MMC_CONFIG0_PORT 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define CB710_MMC_CONFIG1_PORT 0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define CB710_MMC_C1_4BIT_DATA_BUS 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define CB710_MMC_CONFIG2_PORT 0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define CB710_MMC_C2_READ_PIO_SIZE_MASK 0x0F /* N-1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define CB710_MMC_CONFIG3_PORT 0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define CB710_MMC_CONFIGB_PORT 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define CB710_MMC_IRQ_ENABLE_PORT 0x0C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define CB710_MMC_IE_TEST_MASK 0x00BF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define CB710_MMC_IE_CARD_INSERTION_STATUS 0x1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define CB710_MMC_IE_IRQ_ENABLE 0x8000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define CB710_MMC_IE_CISTATUS_MASK \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) (CB710_MMC_IE_CARD_INSERTION_STATUS|CB710_MMC_IE_IRQ_ENABLE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define CB710_MMC_STATUS_PORT 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define CB710_MMC_STATUS_ERROR_EVENTS 0x60FF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define CB710_MMC_STATUS0_PORT 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define CB710_MMC_S0_FIFO_UNDERFLOW 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define CB710_MMC_STATUS1_PORT 0x11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define CB710_MMC_S1_COMMAND_SENT 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define CB710_MMC_S1_DATA_TRANSFER_DONE 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define CB710_MMC_S1_PIO_TRANSFER_DONE 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define CB710_MMC_S1_CARD_CHANGED 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define CB710_MMC_S1_RESET 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define CB710_MMC_STATUS2_PORT 0x12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define CB710_MMC_S2_FIFO_READY 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define CB710_MMC_S2_FIFO_EMPTY 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define CB710_MMC_S2_BUSY_10 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define CB710_MMC_S2_BUSY_20 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define CB710_MMC_STATUS3_PORT 0x13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define CB710_MMC_S3_CARD_DETECTED 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define CB710_MMC_S3_WRITE_PROTECTED 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define CB710_MMC_CMD_TYPE_PORT 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define CB710_MMC_RSP_TYPE_MASK 0x0007
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define CB710_MMC_RSP_R1 (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define CB710_MMC_RSP_136 (5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define CB710_MMC_RSP_NO_CRC (2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define CB710_MMC_RSP_PRESENT_MASK 0x0018
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define CB710_MMC_RSP_NONE (0 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define CB710_MMC_RSP_PRESENT (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define CB710_MMC_RSP_PRESENT_X (2 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define CB710_MMC_CMD_TYPE_MASK 0x0060
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define CB710_MMC_CMD_BC (0 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define CB710_MMC_CMD_BCR (1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define CB710_MMC_CMD_AC (2 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define CB710_MMC_CMD_ADTC (3 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define CB710_MMC_DATA_READ 0x0080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define CB710_MMC_CMD_CODE_MASK 0x3F00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define CB710_MMC_CMD_CODE_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define CB710_MMC_IS_APP_CMD 0x4000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define CB710_MMC_RSP_BUSY 0x8000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define CB710_MMC_CMD_PARAM_PORT 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define CB710_MMC_TRANSFER_SIZE_PORT 0x1C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define CB710_MMC_RESPONSE0_PORT 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define CB710_MMC_RESPONSE1_PORT 0x24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define CB710_MMC_RESPONSE2_PORT 0x28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define CB710_MMC_RESPONSE3_PORT 0x2C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #endif /* LINUX_CB710_MMC_H */
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Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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