^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * cb710/mmc.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright by Michał Mirosław, 2008-2009
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include "cb710-mmc.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define CB710_MMC_REQ_TIMEOUT_MS 2000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) static const u8 cb710_clock_divider_log2[8] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) /* 1, 2, 4, 8, 16, 32, 128, 512 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) 0, 1, 2, 3, 4, 5, 7, 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define CB710_MAX_DIVIDER_IDX \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) (ARRAY_SIZE(cb710_clock_divider_log2) - 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) static const u8 cb710_src_freq_mhz[16] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) 33, 10, 20, 25, 30, 35, 40, 45,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) 50, 55, 60, 65, 70, 75, 80, 85
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) static void cb710_mmc_select_clock_divider(struct mmc_host *mmc, int hz)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) struct cb710_slot *slot = cb710_mmc_to_slot(mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) struct pci_dev *pdev = cb710_slot_to_chip(slot)->pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) u32 src_freq_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) u32 divider_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) int src_hz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) /* on CB710 in HP nx9500:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) * src_freq_idx == 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) * indexes 1-7 work as written in the table
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) * indexes 0,8-15 give no clock output
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) pci_read_config_dword(pdev, 0x48, &src_freq_idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) src_freq_idx = (src_freq_idx >> 16) & 0xF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) src_hz = cb710_src_freq_mhz[src_freq_idx] * 1000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) for (divider_idx = 0; divider_idx < CB710_MAX_DIVIDER_IDX; ++divider_idx) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) if (hz >= src_hz >> cb710_clock_divider_log2[divider_idx])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) if (src_freq_idx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) divider_idx |= 0x8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) else if (divider_idx == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) divider_idx = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) cb710_pci_update_config_reg(pdev, 0x40, ~0xF0000000, divider_idx << 28);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) dev_dbg(cb710_slot_dev(slot),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) "clock set to %d Hz, wanted %d Hz; src_freq_idx = %d, divider_idx = %d|%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) src_hz >> cb710_clock_divider_log2[divider_idx & 7],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) hz, src_freq_idx, divider_idx & 7, divider_idx & 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) static void __cb710_mmc_enable_irq(struct cb710_slot *slot,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) unsigned short enable, unsigned short mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) /* clear global IE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) * - it gets set later if any interrupt sources are enabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) mask |= CB710_MMC_IE_IRQ_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) /* look like interrupt is fired whenever
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) * WORD[0x0C] & WORD[0x10] != 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) * -> bit 15 port 0x0C seems to be global interrupt enable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) enable = (cb710_read_port_16(slot, CB710_MMC_IRQ_ENABLE_PORT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) & ~mask) | enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) if (enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) enable |= CB710_MMC_IE_IRQ_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) cb710_write_port_16(slot, CB710_MMC_IRQ_ENABLE_PORT, enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) static void cb710_mmc_enable_irq(struct cb710_slot *slot,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) unsigned short enable, unsigned short mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) struct cb710_mmc_reader *reader = mmc_priv(cb710_slot_to_mmc(slot));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) spin_lock_irqsave(&reader->irq_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) /* this is the only thing irq_lock protects */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) __cb710_mmc_enable_irq(slot, enable, mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) spin_unlock_irqrestore(&reader->irq_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) static void cb710_mmc_reset_events(struct cb710_slot *slot)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) cb710_write_port_8(slot, CB710_MMC_STATUS0_PORT, 0xFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) cb710_write_port_8(slot, CB710_MMC_STATUS1_PORT, 0xFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) cb710_write_port_8(slot, CB710_MMC_STATUS2_PORT, 0xFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) static void cb710_mmc_enable_4bit_data(struct cb710_slot *slot, int enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) if (enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) cb710_modify_port_8(slot, CB710_MMC_CONFIG1_PORT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) CB710_MMC_C1_4BIT_DATA_BUS, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) cb710_modify_port_8(slot, CB710_MMC_CONFIG1_PORT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 0, CB710_MMC_C1_4BIT_DATA_BUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) static int cb710_check_event(struct cb710_slot *slot, u8 what)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) u16 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) status = cb710_read_port_16(slot, CB710_MMC_STATUS_PORT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) if (status & CB710_MMC_S0_FIFO_UNDERFLOW) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) /* it is just a guess, so log it */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) dev_dbg(cb710_slot_dev(slot),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) "CHECK : ignoring bit 6 in status %04X\n", status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) cb710_write_port_8(slot, CB710_MMC_STATUS0_PORT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) CB710_MMC_S0_FIFO_UNDERFLOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) status &= ~CB710_MMC_S0_FIFO_UNDERFLOW;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) if (status & CB710_MMC_STATUS_ERROR_EVENTS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) dev_dbg(cb710_slot_dev(slot),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) "CHECK : returning EIO on status %04X\n", status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) cb710_write_port_8(slot, CB710_MMC_STATUS0_PORT, status & 0xFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) cb710_write_port_8(slot, CB710_MMC_STATUS1_PORT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) CB710_MMC_S1_RESET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) /* 'what' is a bit in MMC_STATUS1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) if ((status >> 8) & what) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) cb710_write_port_8(slot, CB710_MMC_STATUS1_PORT, what);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) static int cb710_wait_for_event(struct cb710_slot *slot, u8 what)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) int err = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) unsigned limit = 2000000; /* FIXME: real timeout */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #ifdef CONFIG_CB710_DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) u32 e, x;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) e = cb710_read_port_32(slot, CB710_MMC_STATUS_PORT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) while (!(err = cb710_check_event(slot, what))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) if (!--limit) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) cb710_dump_regs(cb710_slot_to_chip(slot),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) CB710_DUMP_REGS_MMC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) err = -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #ifdef CONFIG_CB710_DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) x = cb710_read_port_32(slot, CB710_MMC_STATUS_PORT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) limit = 2000000 - limit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) if (limit > 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) dev_dbg(cb710_slot_dev(slot),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) "WAIT10: waited %d loops, what %d, entry val %08X, exit val %08X\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) limit, what, e, x);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) return err < 0 ? err : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) static int cb710_wait_while_busy(struct cb710_slot *slot, uint8_t mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) unsigned limit = 500000; /* FIXME: real timeout */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) int err = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #ifdef CONFIG_CB710_DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) u32 e, x;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) e = cb710_read_port_32(slot, CB710_MMC_STATUS_PORT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) while (cb710_read_port_8(slot, CB710_MMC_STATUS2_PORT) & mask) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) if (!--limit) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) cb710_dump_regs(cb710_slot_to_chip(slot),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) CB710_DUMP_REGS_MMC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) err = -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #ifdef CONFIG_CB710_DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) x = cb710_read_port_32(slot, CB710_MMC_STATUS_PORT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) limit = 500000 - limit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) if (limit > 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) dev_dbg(cb710_slot_dev(slot),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) "WAIT12: waited %d loops, mask %02X, entry val %08X, exit val %08X\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) limit, mask, e, x);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) static void cb710_mmc_set_transfer_size(struct cb710_slot *slot,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) size_t count, size_t blocksize)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) cb710_wait_while_busy(slot, CB710_MMC_S2_BUSY_20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) cb710_write_port_32(slot, CB710_MMC_TRANSFER_SIZE_PORT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) ((count - 1) << 16)|(blocksize - 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) dev_vdbg(cb710_slot_dev(slot), "set up for %zu block%s of %zu bytes\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) count, count == 1 ? "" : "s", blocksize);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) static void cb710_mmc_fifo_hack(struct cb710_slot *slot)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) /* without this, received data is prepended with 8-bytes of zeroes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) u32 r1, r2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) int ok = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) r1 = cb710_read_port_32(slot, CB710_MMC_DATA_PORT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) r2 = cb710_read_port_32(slot, CB710_MMC_DATA_PORT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) if (cb710_read_port_8(slot, CB710_MMC_STATUS0_PORT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) & CB710_MMC_S0_FIFO_UNDERFLOW) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) cb710_write_port_8(slot, CB710_MMC_STATUS0_PORT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) CB710_MMC_S0_FIFO_UNDERFLOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) ok = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) dev_dbg(cb710_slot_dev(slot),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) "FIFO-read-hack: expected STATUS0 bit was %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) ok ? "set." : "NOT SET!");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) dev_dbg(cb710_slot_dev(slot),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) "FIFO-read-hack: dwords ignored: %08X %08X - %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) r1, r2, (r1|r2) ? "BAD (NOT ZERO)!" : "ok");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) static int cb710_mmc_receive_pio(struct cb710_slot *slot,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) struct sg_mapping_iter *miter, size_t dw_count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) if (!(cb710_read_port_8(slot, CB710_MMC_STATUS2_PORT) & CB710_MMC_S2_FIFO_READY)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) int err = cb710_wait_for_event(slot,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) CB710_MMC_S1_PIO_TRANSFER_DONE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) cb710_sg_dwiter_write_from_io(miter,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) slot->iobase + CB710_MMC_DATA_PORT, dw_count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) static bool cb710_is_transfer_size_supported(struct mmc_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) return !(data->blksz & 15 && (data->blocks != 1 || data->blksz != 8));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) static int cb710_mmc_receive(struct cb710_slot *slot, struct mmc_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) struct sg_mapping_iter miter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) size_t len, blocks = data->blocks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) int err = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) /* TODO: I don't know how/if the hardware handles non-16B-boundary blocks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) * except single 8B block */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) if (unlikely(data->blksz & 15 && (data->blocks != 1 || data->blksz != 8)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) sg_miter_start(&miter, data->sg, data->sg_len, SG_MITER_TO_SG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) cb710_modify_port_8(slot, CB710_MMC_CONFIG2_PORT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 15, CB710_MMC_C2_READ_PIO_SIZE_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) cb710_mmc_fifo_hack(slot);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) while (blocks-- > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) len = data->blksz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) while (len >= 16) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) err = cb710_mmc_receive_pio(slot, &miter, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) len -= 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) if (!len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) cb710_modify_port_8(slot, CB710_MMC_CONFIG2_PORT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) len - 1, CB710_MMC_C2_READ_PIO_SIZE_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) len = (len >= 8) ? 4 : 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) err = cb710_mmc_receive_pio(slot, &miter, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) sg_miter_stop(&miter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) static int cb710_mmc_send(struct cb710_slot *slot, struct mmc_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) struct sg_mapping_iter miter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) size_t len, blocks = data->blocks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) int err = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) /* TODO: I don't know how/if the hardware handles multiple
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) * non-16B-boundary blocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) if (unlikely(data->blocks > 1 && data->blksz & 15))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) sg_miter_start(&miter, data->sg, data->sg_len, SG_MITER_FROM_SG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) cb710_modify_port_8(slot, CB710_MMC_CONFIG2_PORT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 0, CB710_MMC_C2_READ_PIO_SIZE_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) while (blocks-- > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) len = (data->blksz + 15) >> 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) if (!(cb710_read_port_8(slot, CB710_MMC_STATUS2_PORT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) & CB710_MMC_S2_FIFO_EMPTY)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) err = cb710_wait_for_event(slot,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) CB710_MMC_S1_PIO_TRANSFER_DONE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) cb710_sg_dwiter_read_to_io(&miter,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) slot->iobase + CB710_MMC_DATA_PORT, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) } while (--len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) sg_miter_stop(&miter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) static u16 cb710_encode_cmd_flags(struct cb710_mmc_reader *reader,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) struct mmc_command *cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) unsigned int flags = cmd->flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) u16 cb_flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) /* Windows driver returned 0 for commands for which no response
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) * is expected. It happened that there were only two such commands
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) * used: MMC_GO_IDLE_STATE and MMC_GO_INACTIVE_STATE so it might
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) * as well be a bug in that driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) * Original driver set bit 14 for MMC/SD application
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) * commands. There's no difference 'on the wire' and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) * it apparently works without it anyway.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) switch (flags & MMC_CMD_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) case MMC_CMD_AC: cb_flags = CB710_MMC_CMD_AC; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) case MMC_CMD_ADTC: cb_flags = CB710_MMC_CMD_ADTC; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) case MMC_CMD_BC: cb_flags = CB710_MMC_CMD_BC; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) case MMC_CMD_BCR: cb_flags = CB710_MMC_CMD_BCR; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) if (flags & MMC_RSP_BUSY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) cb_flags |= CB710_MMC_RSP_BUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) cb_flags |= cmd->opcode << CB710_MMC_CMD_CODE_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) if (cmd->data && (cmd->data->flags & MMC_DATA_READ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) cb_flags |= CB710_MMC_DATA_READ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) if (flags & MMC_RSP_PRESENT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) /* Windows driver set 01 at bits 4,3 except for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) * MMC_SET_BLOCKLEN where it set 10. Maybe the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) * hardware can do something special about this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) * command? The original driver looks buggy/incomplete
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) * anyway so we ignore this for now.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) * I assume that 00 here means no response is expected.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) cb_flags |= CB710_MMC_RSP_PRESENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) if (flags & MMC_RSP_136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) cb_flags |= CB710_MMC_RSP_136;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) if (!(flags & MMC_RSP_CRC))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) cb_flags |= CB710_MMC_RSP_NO_CRC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) return cb_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) static void cb710_receive_response(struct cb710_slot *slot,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) struct mmc_command *cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) unsigned rsp_opcode, wanted_opcode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) /* Looks like final byte with CRC is always stripped (same as SDHCI) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) if (cmd->flags & MMC_RSP_136) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) u32 resp[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) resp[0] = cb710_read_port_32(slot, CB710_MMC_RESPONSE3_PORT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) resp[1] = cb710_read_port_32(slot, CB710_MMC_RESPONSE2_PORT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) resp[2] = cb710_read_port_32(slot, CB710_MMC_RESPONSE1_PORT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) resp[3] = cb710_read_port_32(slot, CB710_MMC_RESPONSE0_PORT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) rsp_opcode = resp[0] >> 24;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) cmd->resp[0] = (resp[0] << 8)|(resp[1] >> 24);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) cmd->resp[1] = (resp[1] << 8)|(resp[2] >> 24);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) cmd->resp[2] = (resp[2] << 8)|(resp[3] >> 24);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) cmd->resp[3] = (resp[3] << 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) rsp_opcode = cb710_read_port_32(slot, CB710_MMC_RESPONSE1_PORT) & 0x3F;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) cmd->resp[0] = cb710_read_port_32(slot, CB710_MMC_RESPONSE0_PORT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) wanted_opcode = (cmd->flags & MMC_RSP_OPCODE) ? cmd->opcode : 0x3F;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) if (rsp_opcode != wanted_opcode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) cmd->error = -EILSEQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) static int cb710_mmc_transfer_data(struct cb710_slot *slot,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) struct mmc_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) int error, to;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) if (data->flags & MMC_DATA_READ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) error = cb710_mmc_receive(slot, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) error = cb710_mmc_send(slot, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) to = cb710_wait_for_event(slot, CB710_MMC_S1_DATA_TRANSFER_DONE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) if (!error)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) error = to;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) if (!error)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) data->bytes_xfered = data->blksz * data->blocks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) return error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) static int cb710_mmc_command(struct mmc_host *mmc, struct mmc_command *cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) struct cb710_slot *slot = cb710_mmc_to_slot(mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) struct cb710_mmc_reader *reader = mmc_priv(mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) struct mmc_data *data = cmd->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) u16 cb_cmd = cb710_encode_cmd_flags(reader, cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) dev_dbg(cb710_slot_dev(slot), "cmd request: 0x%04X\n", cb_cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) if (data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) if (!cb710_is_transfer_size_supported(data)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) data->error = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) cb710_mmc_set_transfer_size(slot, data->blocks, data->blksz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) cb710_wait_while_busy(slot, CB710_MMC_S2_BUSY_20|CB710_MMC_S2_BUSY_10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) cb710_write_port_16(slot, CB710_MMC_CMD_TYPE_PORT, cb_cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) cb710_wait_while_busy(slot, CB710_MMC_S2_BUSY_20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) cb710_write_port_32(slot, CB710_MMC_CMD_PARAM_PORT, cmd->arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) cb710_mmc_reset_events(slot);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) cb710_wait_while_busy(slot, CB710_MMC_S2_BUSY_20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) cb710_modify_port_8(slot, CB710_MMC_CONFIG0_PORT, 0x01, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) cmd->error = cb710_wait_for_event(slot, CB710_MMC_S1_COMMAND_SENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) if (cmd->error)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) if (cmd->flags & MMC_RSP_PRESENT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) cb710_receive_response(slot, cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) if (cmd->error)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) if (data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) data->error = cb710_mmc_transfer_data(slot, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) static void cb710_mmc_request(struct mmc_host *mmc, struct mmc_request *mrq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) struct cb710_slot *slot = cb710_mmc_to_slot(mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) struct cb710_mmc_reader *reader = mmc_priv(mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) WARN_ON(reader->mrq != NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) reader->mrq = mrq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) cb710_mmc_enable_irq(slot, CB710_MMC_IE_TEST_MASK, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) if (!cb710_mmc_command(mmc, mrq->cmd) && mrq->stop)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) cb710_mmc_command(mmc, mrq->stop);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) tasklet_schedule(&reader->finish_req_tasklet);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) static int cb710_mmc_powerup(struct cb710_slot *slot)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) #ifdef CONFIG_CB710_DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) struct cb710_chip *chip = cb710_slot_to_chip(slot);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) /* a lot of magic for now */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) dev_dbg(cb710_slot_dev(slot), "bus powerup\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) cb710_dump_regs(chip, CB710_DUMP_REGS_MMC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) err = cb710_wait_while_busy(slot, CB710_MMC_S2_BUSY_20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) if (unlikely(err))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) cb710_modify_port_8(slot, CB710_MMC_CONFIG1_PORT, 0x80, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) cb710_modify_port_8(slot, CB710_MMC_CONFIG3_PORT, 0x80, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) cb710_dump_regs(chip, CB710_DUMP_REGS_MMC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) mdelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) dev_dbg(cb710_slot_dev(slot), "after delay 1\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) cb710_dump_regs(chip, CB710_DUMP_REGS_MMC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) err = cb710_wait_while_busy(slot, CB710_MMC_S2_BUSY_20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) if (unlikely(err))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) cb710_modify_port_8(slot, CB710_MMC_CONFIG1_PORT, 0x09, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) cb710_dump_regs(chip, CB710_DUMP_REGS_MMC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) mdelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) dev_dbg(cb710_slot_dev(slot), "after delay 2\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) cb710_dump_regs(chip, CB710_DUMP_REGS_MMC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) err = cb710_wait_while_busy(slot, CB710_MMC_S2_BUSY_20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) if (unlikely(err))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) cb710_modify_port_8(slot, CB710_MMC_CONFIG1_PORT, 0, 0x08);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) cb710_dump_regs(chip, CB710_DUMP_REGS_MMC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) mdelay(2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) dev_dbg(cb710_slot_dev(slot), "after delay 3\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) cb710_dump_regs(chip, CB710_DUMP_REGS_MMC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) cb710_modify_port_8(slot, CB710_MMC_CONFIG0_PORT, 0x06, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) cb710_modify_port_8(slot, CB710_MMC_CONFIG1_PORT, 0x70, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) cb710_modify_port_8(slot, CB710_MMC_CONFIG2_PORT, 0x80, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) cb710_modify_port_8(slot, CB710_MMC_CONFIG3_PORT, 0x03, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) cb710_dump_regs(chip, CB710_DUMP_REGS_MMC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) err = cb710_wait_while_busy(slot, CB710_MMC_S2_BUSY_20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) if (unlikely(err))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) /* This port behaves weird: quick byte reads of 0x08,0x09 return
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) * 0xFF,0x00 after writing 0xFFFF to 0x08; it works correctly when
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) * read/written from userspace... What am I missing here?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) * (it doesn't depend on write-to-read delay) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) cb710_write_port_16(slot, CB710_MMC_CONFIGB_PORT, 0xFFFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) cb710_modify_port_8(slot, CB710_MMC_CONFIG0_PORT, 0x06, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) cb710_dump_regs(chip, CB710_DUMP_REGS_MMC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) dev_dbg(cb710_slot_dev(slot), "bus powerup finished\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) return cb710_check_event(slot, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) static void cb710_mmc_powerdown(struct cb710_slot *slot)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) cb710_modify_port_8(slot, CB710_MMC_CONFIG1_PORT, 0, 0x81);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) cb710_modify_port_8(slot, CB710_MMC_CONFIG3_PORT, 0, 0x80);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) static void cb710_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) struct cb710_slot *slot = cb710_mmc_to_slot(mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) struct cb710_mmc_reader *reader = mmc_priv(mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) cb710_mmc_select_clock_divider(mmc, ios->clock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) if (ios->power_mode != reader->last_power_mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) switch (ios->power_mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) case MMC_POWER_ON:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) err = cb710_mmc_powerup(slot);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) dev_warn(cb710_slot_dev(slot),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) "powerup failed (%d)- retrying\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) cb710_mmc_powerdown(slot);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) err = cb710_mmc_powerup(slot);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) dev_warn(cb710_slot_dev(slot),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) "powerup retry failed (%d) - expect errors\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) reader->last_power_mode = MMC_POWER_ON;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) case MMC_POWER_OFF:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) cb710_mmc_powerdown(slot);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) reader->last_power_mode = MMC_POWER_OFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) case MMC_POWER_UP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) /* ignore */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) cb710_mmc_enable_4bit_data(slot, ios->bus_width != MMC_BUS_WIDTH_1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) cb710_mmc_enable_irq(slot, CB710_MMC_IE_TEST_MASK, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) static int cb710_mmc_get_ro(struct mmc_host *mmc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) struct cb710_slot *slot = cb710_mmc_to_slot(mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) return cb710_read_port_8(slot, CB710_MMC_STATUS3_PORT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) & CB710_MMC_S3_WRITE_PROTECTED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) static int cb710_mmc_get_cd(struct mmc_host *mmc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) struct cb710_slot *slot = cb710_mmc_to_slot(mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) return cb710_read_port_8(slot, CB710_MMC_STATUS3_PORT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) & CB710_MMC_S3_CARD_DETECTED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) static int cb710_mmc_irq_handler(struct cb710_slot *slot)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) struct mmc_host *mmc = cb710_slot_to_mmc(slot);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) struct cb710_mmc_reader *reader = mmc_priv(mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) u32 status, config1, config2, irqen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) status = cb710_read_port_32(slot, CB710_MMC_STATUS_PORT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) irqen = cb710_read_port_32(slot, CB710_MMC_IRQ_ENABLE_PORT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) config2 = cb710_read_port_32(slot, CB710_MMC_CONFIGB_PORT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) config1 = cb710_read_port_32(slot, CB710_MMC_CONFIG_PORT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) dev_dbg(cb710_slot_dev(slot), "interrupt; status: %08X, "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) "ie: %08X, c2: %08X, c1: %08X\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) status, irqen, config2, config1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) if (status & (CB710_MMC_S1_CARD_CHANGED << 8)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) /* ack the event */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) cb710_write_port_8(slot, CB710_MMC_STATUS1_PORT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) CB710_MMC_S1_CARD_CHANGED);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) if ((irqen & CB710_MMC_IE_CISTATUS_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) == CB710_MMC_IE_CISTATUS_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) mmc_detect_change(mmc, HZ/5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) dev_dbg(cb710_slot_dev(slot), "unknown interrupt (test)\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) spin_lock(&reader->irq_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) __cb710_mmc_enable_irq(slot, 0, CB710_MMC_IE_TEST_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) spin_unlock(&reader->irq_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) static void cb710_mmc_finish_request_tasklet(unsigned long data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) struct mmc_host *mmc = (void *)data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) struct cb710_mmc_reader *reader = mmc_priv(mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) struct mmc_request *mrq = reader->mrq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) reader->mrq = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) mmc_request_done(mmc, mrq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) static const struct mmc_host_ops cb710_mmc_host = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) .request = cb710_mmc_request,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) .set_ios = cb710_mmc_set_ios,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) .get_ro = cb710_mmc_get_ro,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) .get_cd = cb710_mmc_get_cd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) #ifdef CONFIG_PM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) static int cb710_mmc_suspend(struct platform_device *pdev, pm_message_t state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) struct cb710_slot *slot = cb710_pdev_to_slot(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) cb710_mmc_enable_irq(slot, 0, ~0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) static int cb710_mmc_resume(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) struct cb710_slot *slot = cb710_pdev_to_slot(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) cb710_mmc_enable_irq(slot, 0, ~0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) #endif /* CONFIG_PM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) static int cb710_mmc_init(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) struct cb710_slot *slot = cb710_pdev_to_slot(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) struct cb710_chip *chip = cb710_slot_to_chip(slot);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) struct mmc_host *mmc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) struct cb710_mmc_reader *reader;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) mmc = mmc_alloc_host(sizeof(*reader), cb710_slot_dev(slot));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) if (!mmc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) platform_set_drvdata(pdev, mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) /* harmless (maybe) magic */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) pci_read_config_dword(chip->pdev, 0x48, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) val = cb710_src_freq_mhz[(val >> 16) & 0xF];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) dev_dbg(cb710_slot_dev(slot), "source frequency: %dMHz\n", val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) val *= 1000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) mmc->ops = &cb710_mmc_host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) mmc->f_max = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) mmc->f_min = val >> cb710_clock_divider_log2[CB710_MAX_DIVIDER_IDX];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) mmc->ocr_avail = MMC_VDD_32_33|MMC_VDD_33_34;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) mmc->caps = MMC_CAP_4_BIT_DATA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) * In cb710_wait_for_event() we use a fixed timeout of ~2s, hence let's
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) * inform the core about it. A future improvement should instead make
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) * use of the cmd->busy_timeout.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) mmc->max_busy_timeout = CB710_MMC_REQ_TIMEOUT_MS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) reader = mmc_priv(mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) tasklet_init(&reader->finish_req_tasklet,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) cb710_mmc_finish_request_tasklet, (unsigned long)mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) spin_lock_init(&reader->irq_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) cb710_dump_regs(chip, CB710_DUMP_REGS_MMC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) cb710_mmc_enable_irq(slot, 0, ~0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) cb710_set_irq_handler(slot, cb710_mmc_irq_handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) err = mmc_add_host(mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) if (unlikely(err))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) goto err_free_mmc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) dev_dbg(cb710_slot_dev(slot), "mmc_hostname is %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) mmc_hostname(mmc));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) cb710_mmc_enable_irq(slot, CB710_MMC_IE_CARD_INSERTION_STATUS, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) err_free_mmc:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) dev_dbg(cb710_slot_dev(slot), "mmc_add_host() failed: %d\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) cb710_set_irq_handler(slot, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) mmc_free_host(mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) static int cb710_mmc_exit(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) struct cb710_slot *slot = cb710_pdev_to_slot(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) struct mmc_host *mmc = cb710_slot_to_mmc(slot);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) struct cb710_mmc_reader *reader = mmc_priv(mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) cb710_mmc_enable_irq(slot, 0, CB710_MMC_IE_CARD_INSERTION_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) mmc_remove_host(mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) /* IRQs should be disabled now, but let's stay on the safe side */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) cb710_mmc_enable_irq(slot, 0, ~0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) cb710_set_irq_handler(slot, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) /* clear config ports - just in case */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) cb710_write_port_32(slot, CB710_MMC_CONFIG_PORT, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) cb710_write_port_16(slot, CB710_MMC_CONFIGB_PORT, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) tasklet_kill(&reader->finish_req_tasklet);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) mmc_free_host(mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) static struct platform_driver cb710_mmc_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) .driver.name = "cb710-mmc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) .probe = cb710_mmc_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) .remove = cb710_mmc_exit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) #ifdef CONFIG_PM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) .suspend = cb710_mmc_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) .resume = cb710_mmc_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) module_platform_driver(cb710_mmc_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) MODULE_AUTHOR("Michał Mirosław <mirq-linux@rere.qmqm.pl>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) MODULE_DESCRIPTION("ENE CB710 memory card reader driver - MMC/SD part");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) MODULE_ALIAS("platform:cb710-mmc");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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