Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2)  * Driver for MMC and SSD cards for Cavium OCTEON and ThunderX SOCs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  * This file is subject to the terms and conditions of the GNU General Public
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * License.  See the file "COPYING" in the main directory of this archive
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  * for more details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  * Copyright (C) 2012-2017 Cavium Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #ifndef _CAVIUM_MMC_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #define _CAVIUM_MMC_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/bitops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/gpio/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include <linux/mmc/host.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #include <linux/scatterlist.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #include <linux/semaphore.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #define CAVIUM_MAX_MMC		4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) /* DMA register addresses */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define MIO_EMM_DMA_FIFO_CFG(x)	(0x00 + x->reg_off_dma)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #define MIO_EMM_DMA_FIFO_ADR(x)	(0x10 + x->reg_off_dma)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define MIO_EMM_DMA_FIFO_CMD(x)	(0x18 + x->reg_off_dma)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define MIO_EMM_DMA_CFG(x)	(0x20 + x->reg_off_dma)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define MIO_EMM_DMA_ADR(x)	(0x28 + x->reg_off_dma)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define MIO_EMM_DMA_INT(x)	(0x30 + x->reg_off_dma)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define MIO_EMM_DMA_INT_W1S(x)	(0x38 + x->reg_off_dma)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define MIO_EMM_DMA_INT_ENA_W1S(x) (0x40 + x->reg_off_dma)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define MIO_EMM_DMA_INT_ENA_W1C(x) (0x48 + x->reg_off_dma)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) /* register addresses */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define MIO_EMM_CFG(x)		(0x00 + x->reg_off)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define MIO_EMM_SWITCH(x)	(0x48 + x->reg_off)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #define MIO_EMM_DMA(x)		(0x50 + x->reg_off)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #define MIO_EMM_CMD(x)		(0x58 + x->reg_off)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #define MIO_EMM_RSP_STS(x)	(0x60 + x->reg_off)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #define MIO_EMM_RSP_LO(x)	(0x68 + x->reg_off)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #define MIO_EMM_RSP_HI(x)	(0x70 + x->reg_off)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #define MIO_EMM_INT(x)		(0x78 + x->reg_off)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) #define MIO_EMM_INT_EN(x)	(0x80 + x->reg_off)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) #define MIO_EMM_WDOG(x)		(0x88 + x->reg_off)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) #define MIO_EMM_SAMPLE(x)	(0x90 + x->reg_off)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) #define MIO_EMM_STS_MASK(x)	(0x98 + x->reg_off)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) #define MIO_EMM_RCA(x)		(0xa0 + x->reg_off)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) #define MIO_EMM_INT_EN_SET(x)	(0xb0 + x->reg_off)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) #define MIO_EMM_INT_EN_CLR(x)	(0xb8 + x->reg_off)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) #define MIO_EMM_BUF_IDX(x)	(0xe0 + x->reg_off)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) #define MIO_EMM_BUF_DAT(x)	(0xe8 + x->reg_off)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) struct cvm_mmc_host {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 	struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 	void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 	void __iomem *dma_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	int reg_off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 	int reg_off_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 	u64 emm_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	u64 n_minus_one;	/* OCTEON II workaround location */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 	int last_slot;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	int sys_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 	struct mmc_request *current_req;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	struct sg_mapping_iter smi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	bool dma_active;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	bool use_sg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	bool has_ciu3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	bool big_dma_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	bool need_irq_handler_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	spinlock_t irq_handler_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	struct semaphore mmc_serializer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	struct gpio_desc *global_pwr_gpiod;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	atomic_t shared_power_users;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	struct cvm_mmc_slot *slot[CAVIUM_MAX_MMC];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	struct platform_device *slot_pdev[CAVIUM_MAX_MMC];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	void (*set_shared_power)(struct cvm_mmc_host *, int);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	void (*acquire_bus)(struct cvm_mmc_host *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	void (*release_bus)(struct cvm_mmc_host *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	void (*int_enable)(struct cvm_mmc_host *, u64);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	/* required on some MIPS models */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	void (*dmar_fixup)(struct cvm_mmc_host *, struct mmc_command *,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 			   struct mmc_data *, u64);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	void (*dmar_fixup_done)(struct cvm_mmc_host *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) struct cvm_mmc_slot {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	struct mmc_host *mmc;		/* slot-level mmc_core object */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	struct cvm_mmc_host *host;	/* common hw for all slots */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	u64 clock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	u64 cached_switch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	u64 cached_rca;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	unsigned int cmd_cnt;		/* sample delay */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	unsigned int dat_cnt;		/* sample delay */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	int bus_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) struct cvm_mmc_cr_type {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	u8 ctype;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	u8 rtype;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) struct cvm_mmc_cr_mods {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	u8 ctype_xor;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	u8 rtype_xor;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) /* Bitfield definitions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define MIO_EMM_DMA_FIFO_CFG_CLR	BIT_ULL(16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define MIO_EMM_DMA_FIFO_CFG_INT_LVL	GENMASK_ULL(12, 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define MIO_EMM_DMA_FIFO_CFG_COUNT	GENMASK_ULL(4, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define MIO_EMM_DMA_FIFO_CMD_RW		BIT_ULL(62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define MIO_EMM_DMA_FIFO_CMD_INTDIS	BIT_ULL(60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define MIO_EMM_DMA_FIFO_CMD_SWAP32	BIT_ULL(59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define MIO_EMM_DMA_FIFO_CMD_SWAP16	BIT_ULL(58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define MIO_EMM_DMA_FIFO_CMD_SWAP8	BIT_ULL(57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define MIO_EMM_DMA_FIFO_CMD_ENDIAN	BIT_ULL(56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define MIO_EMM_DMA_FIFO_CMD_SIZE	GENMASK_ULL(55, 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define MIO_EMM_CMD_SKIP_BUSY		BIT_ULL(62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define MIO_EMM_CMD_BUS_ID		GENMASK_ULL(61, 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define MIO_EMM_CMD_VAL			BIT_ULL(59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define MIO_EMM_CMD_DBUF		BIT_ULL(55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define MIO_EMM_CMD_OFFSET		GENMASK_ULL(54, 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define MIO_EMM_CMD_CTYPE_XOR		GENMASK_ULL(42, 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define MIO_EMM_CMD_RTYPE_XOR		GENMASK_ULL(40, 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define MIO_EMM_CMD_IDX			GENMASK_ULL(37, 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define MIO_EMM_CMD_ARG			GENMASK_ULL(31, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define MIO_EMM_DMA_SKIP_BUSY		BIT_ULL(62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define MIO_EMM_DMA_BUS_ID		GENMASK_ULL(61, 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define MIO_EMM_DMA_VAL			BIT_ULL(59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define MIO_EMM_DMA_SECTOR		BIT_ULL(58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define MIO_EMM_DMA_DAT_NULL		BIT_ULL(57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define MIO_EMM_DMA_THRES		GENMASK_ULL(56, 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define MIO_EMM_DMA_REL_WR		BIT_ULL(50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define MIO_EMM_DMA_RW			BIT_ULL(49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define MIO_EMM_DMA_MULTI		BIT_ULL(48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define MIO_EMM_DMA_BLOCK_CNT		GENMASK_ULL(47, 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define MIO_EMM_DMA_CARD_ADDR		GENMASK_ULL(31, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define MIO_EMM_DMA_CFG_EN		BIT_ULL(63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define MIO_EMM_DMA_CFG_RW		BIT_ULL(62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define MIO_EMM_DMA_CFG_CLR		BIT_ULL(61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define MIO_EMM_DMA_CFG_SWAP32		BIT_ULL(59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define MIO_EMM_DMA_CFG_SWAP16		BIT_ULL(58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define MIO_EMM_DMA_CFG_SWAP8		BIT_ULL(57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define MIO_EMM_DMA_CFG_ENDIAN		BIT_ULL(56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define MIO_EMM_DMA_CFG_SIZE		GENMASK_ULL(55, 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define MIO_EMM_DMA_CFG_ADR		GENMASK_ULL(35, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define MIO_EMM_INT_SWITCH_ERR		BIT_ULL(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define MIO_EMM_INT_SWITCH_DONE		BIT_ULL(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define MIO_EMM_INT_DMA_ERR		BIT_ULL(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define MIO_EMM_INT_CMD_ERR		BIT_ULL(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define MIO_EMM_INT_DMA_DONE		BIT_ULL(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define MIO_EMM_INT_CMD_DONE		BIT_ULL(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define MIO_EMM_INT_BUF_DONE		BIT_ULL(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define MIO_EMM_RSP_STS_BUS_ID		GENMASK_ULL(61, 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define MIO_EMM_RSP_STS_CMD_VAL		BIT_ULL(59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define MIO_EMM_RSP_STS_SWITCH_VAL	BIT_ULL(58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define MIO_EMM_RSP_STS_DMA_VAL		BIT_ULL(57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define MIO_EMM_RSP_STS_DMA_PEND	BIT_ULL(56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define MIO_EMM_RSP_STS_DBUF_ERR	BIT_ULL(28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define MIO_EMM_RSP_STS_DBUF		BIT_ULL(23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define MIO_EMM_RSP_STS_BLK_TIMEOUT	BIT_ULL(22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define MIO_EMM_RSP_STS_BLK_CRC_ERR	BIT_ULL(21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define MIO_EMM_RSP_STS_RSP_BUSYBIT	BIT_ULL(20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define MIO_EMM_RSP_STS_STP_TIMEOUT	BIT_ULL(19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define MIO_EMM_RSP_STS_STP_CRC_ERR	BIT_ULL(18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define MIO_EMM_RSP_STS_STP_BAD_STS	BIT_ULL(17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define MIO_EMM_RSP_STS_STP_VAL		BIT_ULL(16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define MIO_EMM_RSP_STS_RSP_TIMEOUT	BIT_ULL(15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define MIO_EMM_RSP_STS_RSP_CRC_ERR	BIT_ULL(14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define MIO_EMM_RSP_STS_RSP_BAD_STS	BIT_ULL(13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define MIO_EMM_RSP_STS_RSP_VAL		BIT_ULL(12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define MIO_EMM_RSP_STS_RSP_TYPE	GENMASK_ULL(11, 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define MIO_EMM_RSP_STS_CMD_TYPE	GENMASK_ULL(8, 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define MIO_EMM_RSP_STS_CMD_IDX		GENMASK_ULL(6, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define MIO_EMM_RSP_STS_CMD_DONE	BIT_ULL(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define MIO_EMM_SAMPLE_CMD_CNT		GENMASK_ULL(25, 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define MIO_EMM_SAMPLE_DAT_CNT		GENMASK_ULL(9, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define MIO_EMM_SWITCH_BUS_ID		GENMASK_ULL(61, 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define MIO_EMM_SWITCH_EXE		BIT_ULL(59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define MIO_EMM_SWITCH_ERR0		BIT_ULL(58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define MIO_EMM_SWITCH_ERR1		BIT_ULL(57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define MIO_EMM_SWITCH_ERR2		BIT_ULL(56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define MIO_EMM_SWITCH_HS_TIMING	BIT_ULL(48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define MIO_EMM_SWITCH_BUS_WIDTH	GENMASK_ULL(42, 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define MIO_EMM_SWITCH_POWER_CLASS	GENMASK_ULL(35, 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define MIO_EMM_SWITCH_CLK_HI		GENMASK_ULL(31, 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #define MIO_EMM_SWITCH_CLK_LO		GENMASK_ULL(15, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) /* Protoypes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) irqreturn_t cvm_mmc_interrupt(int irq, void *dev_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) int cvm_mmc_of_slot_probe(struct device *dev, struct cvm_mmc_host *host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) int cvm_mmc_of_slot_remove(struct cvm_mmc_slot *slot);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) extern const char *cvm_mmc_irq_names[];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #endif