Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2)  * Driver for MMC and SSD cards for Cavium OCTEON SOCs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  * This file is subject to the terms and conditions of the GNU General Public
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * License.  See the file "COPYING" in the main directory of this archive
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  * for more details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  * Copyright (C) 2012-2017 Cavium Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/dma-mapping.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/gpio/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/mmc/mmc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/mmc/slot-gpio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/of_platform.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <asm/octeon/octeon.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include "cavium.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #define CVMX_MIO_BOOT_CTL CVMX_ADD_IO_SEG(0x00011800000000D0ull)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23)  * The l2c* functions below are used for the EMMC-17978 workaround.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25)  * Due to a bug in the design of the MMC bus hardware, the 2nd to last
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26)  * cache block of a DMA read must be locked into the L2 Cache.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27)  * Otherwise, data corruption may occur.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) static inline void *phys_to_ptr(u64 address)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 	return (void *)(address | (1ull << 63)); /* XKPHYS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35)  * Lock a single line into L2. The line is zeroed before locking
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36)  * to make sure no dram accesses are made.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) static void l2c_lock_line(u64 addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 	char *addr_ptr = phys_to_ptr(addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 	asm volatile (
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 		"cache 31, %[line]"	/* Unlock the line */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 		::[line] "m" (*addr_ptr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) /* Unlock a single line in the L2 cache. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) static void l2c_unlock_line(u64 addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 	char *addr_ptr = phys_to_ptr(addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 	asm volatile (
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 		"cache 23, %[line]"	/* Unlock the line */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 		::[line] "m" (*addr_ptr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) /* Locks a memory region in the L2 cache. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) static void l2c_lock_mem_region(u64 start, u64 len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 	u64 end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	/* Round start/end to cache line boundaries */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 	end = ALIGN(start + len - 1, CVMX_CACHE_LINE_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	start = ALIGN(start, CVMX_CACHE_LINE_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 	while (start <= end) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 		l2c_lock_line(start);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 		start += CVMX_CACHE_LINE_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	asm volatile("sync");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) /* Unlock a memory region in the L2 cache. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) static void l2c_unlock_mem_region(u64 start, u64 len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	u64 end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	/* Round start/end to cache line boundaries */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	end = ALIGN(start + len - 1, CVMX_CACHE_LINE_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	start = ALIGN(start, CVMX_CACHE_LINE_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	while (start <= end) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 		l2c_unlock_line(start);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 		start += CVMX_CACHE_LINE_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) static void octeon_mmc_acquire_bus(struct cvm_mmc_host *host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	if (!host->has_ciu3) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 		down(&octeon_bootbus_sem);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 		/* For CN70XX, switch the MMC controller onto the bus. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 		if (OCTEON_IS_MODEL(OCTEON_CN70XX))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 			writeq(0, (void __iomem *)CVMX_MIO_BOOT_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 		down(&host->mmc_serializer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) static void octeon_mmc_release_bus(struct cvm_mmc_host *host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	if (!host->has_ciu3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 		up(&octeon_bootbus_sem);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 		up(&host->mmc_serializer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) static void octeon_mmc_int_enable(struct cvm_mmc_host *host, u64 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	writeq(val, host->base + MIO_EMM_INT(host));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	if (!host->has_ciu3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 		writeq(val, host->base + MIO_EMM_INT_EN(host));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) static void octeon_mmc_set_shared_power(struct cvm_mmc_host *host, int dir)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	if (dir == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 		if (!atomic_dec_return(&host->shared_power_users))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 			gpiod_set_value_cansleep(host->global_pwr_gpiod, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	if (dir == 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 		if (atomic_inc_return(&host->shared_power_users) == 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 			gpiod_set_value_cansleep(host->global_pwr_gpiod, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) static void octeon_mmc_dmar_fixup(struct cvm_mmc_host *host,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 				  struct mmc_command *cmd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 				  struct mmc_data *data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 				  u64 addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	if (cmd->opcode != MMC_WRITE_MULTIPLE_BLOCK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	if (data->blksz * data->blocks <= 1024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	host->n_minus_one = addr + (data->blksz * data->blocks) - 1024;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	l2c_lock_mem_region(host->n_minus_one, 512);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) static void octeon_mmc_dmar_fixup_done(struct cvm_mmc_host *host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	if (!host->n_minus_one)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	l2c_unlock_mem_region(host->n_minus_one, 512);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	host->n_minus_one = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) static int octeon_mmc_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	struct device_node *cn, *node = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	struct cvm_mmc_host *host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	int mmc_irq[9];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	int i, ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	u64 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	host = devm_kzalloc(&pdev->dev, sizeof(*host), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	if (!host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	spin_lock_init(&host->irq_handler_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	sema_init(&host->mmc_serializer, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	host->dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	host->acquire_bus = octeon_mmc_acquire_bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	host->release_bus = octeon_mmc_release_bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	host->int_enable = octeon_mmc_int_enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	host->set_shared_power = octeon_mmc_set_shared_power;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	if (OCTEON_IS_MODEL(OCTEON_CN6XXX) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	    OCTEON_IS_MODEL(OCTEON_CNF7XXX)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 		host->dmar_fixup = octeon_mmc_dmar_fixup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 		host->dmar_fixup_done = octeon_mmc_dmar_fixup_done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	host->sys_freq = octeon_get_io_clock_rate();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	if (of_device_is_compatible(node, "cavium,octeon-7890-mmc")) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 		host->big_dma_addr = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 		host->need_irq_handler_lock = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 		host->has_ciu3 = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 		host->use_sg = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 		/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 		 * First seven are the EMM_INT bits 0..6, then two for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 		 * the EMM_DMA_INT bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 		 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 		for (i = 0; i < 9; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 			mmc_irq[i] = platform_get_irq(pdev, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 			if (mmc_irq[i] < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 				return mmc_irq[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 			/* work around legacy u-boot device trees */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 			irq_set_irq_type(mmc_irq[i], IRQ_TYPE_EDGE_RISING);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 		host->big_dma_addr = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 		host->need_irq_handler_lock = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 		host->has_ciu3 = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 		/* First one is EMM second DMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 		for (i = 0; i < 2; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 			mmc_irq[i] = platform_get_irq(pdev, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 			if (mmc_irq[i] < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 				return mmc_irq[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	host->last_slot = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	base = devm_platform_ioremap_resource(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 	if (IS_ERR(base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 		return PTR_ERR(base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	host->base = base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	host->reg_off = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	base = devm_platform_ioremap_resource(pdev, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 	if (IS_ERR(base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 		return PTR_ERR(base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	host->dma_base = base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 	 * To keep the register addresses shared we intentionaly use
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	 * a negative offset here, first register used on Octeon therefore
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	 * starts at 0x20 (MIO_EMM_DMA_CFG).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 	host->reg_off_dma = -0x20;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 	ret = dma_set_mask(&pdev->dev, DMA_BIT_MASK(64));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	 * Clear out any pending interrupts that may be left over from
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 	 * bootloader.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 	val = readq(host->base + MIO_EMM_INT(host));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 	writeq(val, host->base + MIO_EMM_INT(host));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 	if (host->has_ciu3) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 		/* Only CMD_DONE, DMA_DONE, CMD_ERR, DMA_ERR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 		for (i = 1; i <= 4; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 			ret = devm_request_irq(&pdev->dev, mmc_irq[i],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 					       cvm_mmc_interrupt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 					       0, cvm_mmc_irq_names[i], host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 			if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 				dev_err(&pdev->dev, "Error: devm_request_irq %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 					mmc_irq[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 				return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 			}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 		ret = devm_request_irq(&pdev->dev, mmc_irq[0],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 				       cvm_mmc_interrupt, 0, KBUILD_MODNAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 				       host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 		if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 			dev_err(&pdev->dev, "Error: devm_request_irq %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 				mmc_irq[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 			return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 	host->global_pwr_gpiod = devm_gpiod_get_optional(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 							 "power",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 							 GPIOD_OUT_HIGH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 	if (IS_ERR(host->global_pwr_gpiod)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 		dev_err(&pdev->dev, "Invalid power GPIO\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 		return PTR_ERR(host->global_pwr_gpiod);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 	platform_set_drvdata(pdev, host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 	i = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 	for_each_child_of_node(node, cn) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 		host->slot_pdev[i] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 			of_platform_device_create(cn, NULL, &pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 		if (!host->slot_pdev[i]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 			i++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 			continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 		ret = cvm_mmc_of_slot_probe(&host->slot_pdev[i]->dev, host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 		if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 			dev_err(&pdev->dev, "Error populating slots\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 			octeon_mmc_set_shared_power(host, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 			goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 		i++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) error:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 	for (i = 0; i < CAVIUM_MAX_MMC; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 		if (host->slot[i])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 			cvm_mmc_of_slot_remove(host->slot[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 		if (host->slot_pdev[i])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 			of_platform_device_destroy(&host->slot_pdev[i]->dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) static int octeon_mmc_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 	struct cvm_mmc_host *host = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 	u64 dma_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 	int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 	for (i = 0; i < CAVIUM_MAX_MMC; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 		if (host->slot[i])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 			cvm_mmc_of_slot_remove(host->slot[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 	dma_cfg = readq(host->dma_base + MIO_EMM_DMA_CFG(host));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 	dma_cfg &= ~MIO_EMM_DMA_CFG_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 	writeq(dma_cfg, host->dma_base + MIO_EMM_DMA_CFG(host));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 	octeon_mmc_set_shared_power(host, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) static const struct of_device_id octeon_mmc_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 		.compatible = "cavium,octeon-6130-mmc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 		.compatible = "cavium,octeon-7890-mmc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 	{},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) MODULE_DEVICE_TABLE(of, octeon_mmc_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) static struct platform_driver octeon_mmc_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 	.probe		= octeon_mmc_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 	.remove		= octeon_mmc_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 	.driver		= {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 		.name	= KBUILD_MODNAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 		.probe_type = PROBE_PREFER_ASYNCHRONOUS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 		.of_match_table = octeon_mmc_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) module_platform_driver(octeon_mmc_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) MODULE_AUTHOR("Cavium Inc. <support@cavium.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) MODULE_DESCRIPTION("Low-level driver for Cavium OCTEON MMC/SSD card");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) MODULE_LICENSE("GPL");