^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * bcm2835 sdhost driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * The 2835 has two SD controllers: The Arasan sdhci controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * (supported by the iproc driver) and a custom sdhost controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * (supported by this driver).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * The sdhci controller supports both sdcard and sdio. The sdhost
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * controller supports the sdcard only, but has better performance.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * Also note that the rpi3 has sdio wifi, so driving the sdcard with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * the sdhost controller allows to use the sdhci controller for wifi
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * support.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * The configuration is done by devicetree via pin muxing. Both
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * SD controller are available on the same pins (2 pin groups = pin 22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * to 27 + pin 48 to 53). So it's possible to use both SD controllers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * at the same time with different pin groups.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * Author: Phil Elwell <phil@raspberrypi.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) * Copyright (C) 2015-2016 Raspberry Pi (Trading) Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) * Based on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) * mmc-bcm2835.c by Gellert Weisz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * which is, in turn, based on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) * sdhci-bcm2708.c by Broadcom
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) * sdhci-bcm2835.c by Stephen Warren and Oleksandr Tymoshenko
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) * sdhci.c and sdhci-pci.c by Pierre Ossman
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #include <linux/dmaengine.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #include <linux/dma-mapping.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #include <linux/highmem.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #include <linux/iopoll.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #include <linux/of_irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #include <linux/scatterlist.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #include <linux/time.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #include <linux/workqueue.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #include <linux/mmc/host.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #include <linux/mmc/mmc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #include <linux/mmc/sd.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define SDCMD 0x00 /* Command to SD card - 16 R/W */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define SDARG 0x04 /* Argument to SD card - 32 R/W */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define SDTOUT 0x08 /* Start value for timeout counter - 32 R/W */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define SDCDIV 0x0c /* Start value for clock divider - 11 R/W */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define SDRSP0 0x10 /* SD card response (31:0) - 32 R */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define SDRSP1 0x14 /* SD card response (63:32) - 32 R */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define SDRSP2 0x18 /* SD card response (95:64) - 32 R */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define SDRSP3 0x1c /* SD card response (127:96) - 32 R */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define SDHSTS 0x20 /* SD host status - 11 R/W */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define SDVDD 0x30 /* SD card power control - 1 R/W */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define SDEDM 0x34 /* Emergency Debug Mode - 13 R/W */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define SDHCFG 0x38 /* Host configuration - 2 R/W */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define SDHBCT 0x3c /* Host byte count (debug) - 32 R/W */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define SDDATA 0x40 /* Data to/from SD card - 32 R/W */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define SDHBLC 0x50 /* Host block count (SDIO/SDHC) - 9 R/W */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define SDCMD_NEW_FLAG 0x8000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define SDCMD_FAIL_FLAG 0x4000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define SDCMD_BUSYWAIT 0x800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define SDCMD_NO_RESPONSE 0x400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define SDCMD_LONG_RESPONSE 0x200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define SDCMD_WRITE_CMD 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define SDCMD_READ_CMD 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define SDCMD_CMD_MASK 0x3f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define SDCDIV_MAX_CDIV 0x7ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define SDHSTS_BUSY_IRPT 0x400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define SDHSTS_BLOCK_IRPT 0x200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define SDHSTS_SDIO_IRPT 0x100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define SDHSTS_REW_TIME_OUT 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define SDHSTS_CMD_TIME_OUT 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define SDHSTS_CRC16_ERROR 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define SDHSTS_CRC7_ERROR 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define SDHSTS_FIFO_ERROR 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) /* Reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) /* Reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define SDHSTS_DATA_FLAG 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define SDHSTS_TRANSFER_ERROR_MASK (SDHSTS_CRC7_ERROR | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) SDHSTS_CRC16_ERROR | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) SDHSTS_REW_TIME_OUT | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) SDHSTS_FIFO_ERROR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define SDHSTS_ERROR_MASK (SDHSTS_CMD_TIME_OUT | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) SDHSTS_TRANSFER_ERROR_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define SDHCFG_BUSY_IRPT_EN BIT(10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define SDHCFG_BLOCK_IRPT_EN BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define SDHCFG_SDIO_IRPT_EN BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define SDHCFG_DATA_IRPT_EN BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define SDHCFG_SLOW_CARD BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define SDHCFG_WIDE_EXT_BUS BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define SDHCFG_WIDE_INT_BUS BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define SDHCFG_REL_CMD_LINE BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define SDVDD_POWER_OFF 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define SDVDD_POWER_ON 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define SDEDM_FORCE_DATA_MODE BIT(19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define SDEDM_CLOCK_PULSE BIT(20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define SDEDM_BYPASS BIT(21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define SDEDM_WRITE_THRESHOLD_SHIFT 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define SDEDM_READ_THRESHOLD_SHIFT 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define SDEDM_THRESHOLD_MASK 0x1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define SDEDM_FSM_MASK 0xf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define SDEDM_FSM_IDENTMODE 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define SDEDM_FSM_DATAMODE 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define SDEDM_FSM_READDATA 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define SDEDM_FSM_WRITEDATA 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define SDEDM_FSM_READWAIT 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define SDEDM_FSM_READCRC 0x5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define SDEDM_FSM_WRITECRC 0x6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define SDEDM_FSM_WRITEWAIT1 0x7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define SDEDM_FSM_POWERDOWN 0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define SDEDM_FSM_POWERUP 0x9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define SDEDM_FSM_WRITESTART1 0xa
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define SDEDM_FSM_WRITESTART2 0xb
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define SDEDM_FSM_GENPULSES 0xc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define SDEDM_FSM_WRITEWAIT2 0xd
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define SDEDM_FSM_STARTPOWDOWN 0xf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define SDDATA_FIFO_WORDS 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define FIFO_READ_THRESHOLD 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define FIFO_WRITE_THRESHOLD 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define SDDATA_FIFO_PIO_BURST 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define PIO_THRESHOLD 1 /* Maximum block count for PIO (0 = always DMA) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) struct bcm2835_host {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) spinlock_t lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) struct mutex mutex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) void __iomem *ioaddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) u32 phys_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) struct platform_device *pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) int clock; /* Current clock speed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) unsigned int max_clk; /* Max possible freq */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) struct work_struct dma_work;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) struct delayed_work timeout_work; /* Timer for timeouts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) struct sg_mapping_iter sg_miter; /* SG state for PIO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) unsigned int blocks; /* remaining PIO blocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) int irq; /* Device IRQ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) u32 ns_per_fifo_word;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) /* cached registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) u32 hcfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) u32 cdiv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) struct mmc_request *mrq; /* Current request */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) struct mmc_command *cmd; /* Current command */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) struct mmc_data *data; /* Current data request */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) bool data_complete:1;/* Data finished before cmd */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) bool use_busy:1; /* Wait for busy interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) bool use_sbc:1; /* Send CMD23 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) /* for threaded irq handler */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) bool irq_block;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) bool irq_busy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) bool irq_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) /* DMA part */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) struct dma_chan *dma_chan_rxtx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) struct dma_chan *dma_chan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) struct dma_slave_config dma_cfg_rx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) struct dma_slave_config dma_cfg_tx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) struct dma_async_tx_descriptor *dma_desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) u32 dma_dir;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) u32 drain_words;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) struct page *drain_page;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) u32 drain_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) bool use_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) static void bcm2835_dumpcmd(struct bcm2835_host *host, struct mmc_command *cmd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) const char *label)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) struct device *dev = &host->pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) if (!cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) dev_dbg(dev, "%c%s op %d arg 0x%x flags 0x%x - resp %08x %08x %08x %08x, err %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) (cmd == host->cmd) ? '>' : ' ',
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) label, cmd->opcode, cmd->arg, cmd->flags,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) cmd->resp[0], cmd->resp[1], cmd->resp[2], cmd->resp[3],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) cmd->error);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) static void bcm2835_dumpregs(struct bcm2835_host *host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) struct mmc_request *mrq = host->mrq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) struct device *dev = &host->pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) if (mrq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) bcm2835_dumpcmd(host, mrq->sbc, "sbc");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) bcm2835_dumpcmd(host, mrq->cmd, "cmd");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) if (mrq->data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) dev_dbg(dev, "data blocks %x blksz %x - err %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) mrq->data->blocks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) mrq->data->blksz,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) mrq->data->error);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) bcm2835_dumpcmd(host, mrq->stop, "stop");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) dev_dbg(dev, "=========== REGISTER DUMP ===========\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) dev_dbg(dev, "SDCMD 0x%08x\n", readl(host->ioaddr + SDCMD));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) dev_dbg(dev, "SDARG 0x%08x\n", readl(host->ioaddr + SDARG));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) dev_dbg(dev, "SDTOUT 0x%08x\n", readl(host->ioaddr + SDTOUT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) dev_dbg(dev, "SDCDIV 0x%08x\n", readl(host->ioaddr + SDCDIV));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) dev_dbg(dev, "SDRSP0 0x%08x\n", readl(host->ioaddr + SDRSP0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) dev_dbg(dev, "SDRSP1 0x%08x\n", readl(host->ioaddr + SDRSP1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) dev_dbg(dev, "SDRSP2 0x%08x\n", readl(host->ioaddr + SDRSP2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) dev_dbg(dev, "SDRSP3 0x%08x\n", readl(host->ioaddr + SDRSP3));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) dev_dbg(dev, "SDHSTS 0x%08x\n", readl(host->ioaddr + SDHSTS));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) dev_dbg(dev, "SDVDD 0x%08x\n", readl(host->ioaddr + SDVDD));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) dev_dbg(dev, "SDEDM 0x%08x\n", readl(host->ioaddr + SDEDM));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) dev_dbg(dev, "SDHCFG 0x%08x\n", readl(host->ioaddr + SDHCFG));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) dev_dbg(dev, "SDHBCT 0x%08x\n", readl(host->ioaddr + SDHBCT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) dev_dbg(dev, "SDHBLC 0x%08x\n", readl(host->ioaddr + SDHBLC));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) dev_dbg(dev, "===========================================\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) static void bcm2835_reset_internal(struct bcm2835_host *host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) u32 temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) writel(SDVDD_POWER_OFF, host->ioaddr + SDVDD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) writel(0, host->ioaddr + SDCMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) writel(0, host->ioaddr + SDARG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) writel(0xf00000, host->ioaddr + SDTOUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) writel(0, host->ioaddr + SDCDIV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) writel(0x7f8, host->ioaddr + SDHSTS); /* Write 1s to clear */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) writel(0, host->ioaddr + SDHCFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) writel(0, host->ioaddr + SDHBCT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) writel(0, host->ioaddr + SDHBLC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) /* Limit fifo usage due to silicon bug */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) temp = readl(host->ioaddr + SDEDM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) temp &= ~((SDEDM_THRESHOLD_MASK << SDEDM_READ_THRESHOLD_SHIFT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) (SDEDM_THRESHOLD_MASK << SDEDM_WRITE_THRESHOLD_SHIFT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) temp |= (FIFO_READ_THRESHOLD << SDEDM_READ_THRESHOLD_SHIFT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) (FIFO_WRITE_THRESHOLD << SDEDM_WRITE_THRESHOLD_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) writel(temp, host->ioaddr + SDEDM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) msleep(20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) writel(SDVDD_POWER_ON, host->ioaddr + SDVDD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) msleep(20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) host->clock = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) writel(host->hcfg, host->ioaddr + SDHCFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) writel(host->cdiv, host->ioaddr + SDCDIV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) static void bcm2835_reset(struct mmc_host *mmc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) struct bcm2835_host *host = mmc_priv(mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) if (host->dma_chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) dmaengine_terminate_sync(host->dma_chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) host->dma_chan = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) bcm2835_reset_internal(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) static void bcm2835_finish_command(struct bcm2835_host *host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) static void bcm2835_wait_transfer_complete(struct bcm2835_host *host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) int timediff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) u32 alternate_idle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) alternate_idle = (host->mrq->data->flags & MMC_DATA_READ) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) SDEDM_FSM_READWAIT : SDEDM_FSM_WRITESTART1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) timediff = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) while (1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) u32 edm, fsm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) edm = readl(host->ioaddr + SDEDM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) fsm = edm & SDEDM_FSM_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) if ((fsm == SDEDM_FSM_IDENTMODE) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) (fsm == SDEDM_FSM_DATAMODE))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) if (fsm == alternate_idle) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) writel(edm | SDEDM_FORCE_DATA_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) host->ioaddr + SDEDM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) timediff++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) if (timediff == 100000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) dev_err(&host->pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) "wait_transfer_complete - still waiting after %d retries\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) timediff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) bcm2835_dumpregs(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) host->mrq->data->error = -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) cpu_relax();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) static void bcm2835_dma_complete(void *param)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) struct bcm2835_host *host = param;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) schedule_work(&host->dma_work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) static void bcm2835_transfer_block_pio(struct bcm2835_host *host, bool is_read)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) size_t blksize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) unsigned long wait_max;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) blksize = host->data->blksz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) wait_max = jiffies + msecs_to_jiffies(500);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) local_irq_save(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) while (blksize) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) int copy_words;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) u32 hsts = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) size_t len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) u32 *buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) if (!sg_miter_next(&host->sg_miter)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) host->data->error = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) len = min(host->sg_miter.length, blksize);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) if (len % 4) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) host->data->error = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) blksize -= len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) host->sg_miter.consumed = len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) buf = (u32 *)host->sg_miter.addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) copy_words = len / 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) while (copy_words) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) int burst_words, words;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) u32 edm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) burst_words = min(SDDATA_FIFO_PIO_BURST, copy_words);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) edm = readl(host->ioaddr + SDEDM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) if (is_read)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) words = ((edm >> 4) & 0x1f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) words = SDDATA_FIFO_WORDS - ((edm >> 4) & 0x1f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) if (words < burst_words) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) int fsm_state = (edm & SDEDM_FSM_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) struct device *dev = &host->pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) if ((is_read &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) (fsm_state != SDEDM_FSM_READDATA &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) fsm_state != SDEDM_FSM_READWAIT &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) fsm_state != SDEDM_FSM_READCRC)) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) (!is_read &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) (fsm_state != SDEDM_FSM_WRITEDATA &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) fsm_state != SDEDM_FSM_WRITESTART1 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) fsm_state != SDEDM_FSM_WRITESTART2))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) hsts = readl(host->ioaddr + SDHSTS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) dev_err(dev, "fsm %x, hsts %08x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) fsm_state, hsts);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) if (hsts & SDHSTS_ERROR_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) if (time_after(jiffies, wait_max)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) dev_err(dev, "PIO %s timeout - EDM %08x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) is_read ? "read" : "write",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) edm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) hsts = SDHSTS_REW_TIME_OUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) ndelay((burst_words - words) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) host->ns_per_fifo_word);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) } else if (words > copy_words) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) words = copy_words;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) copy_words -= words;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) while (words) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) if (is_read)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) *(buf++) = readl(host->ioaddr + SDDATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) writel(*(buf++), host->ioaddr + SDDATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) words--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) if (hsts & SDHSTS_ERROR_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) sg_miter_stop(&host->sg_miter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) local_irq_restore(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) static void bcm2835_transfer_pio(struct bcm2835_host *host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) struct device *dev = &host->pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) u32 sdhsts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) bool is_read;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) is_read = (host->data->flags & MMC_DATA_READ) != 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) bcm2835_transfer_block_pio(host, is_read);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) sdhsts = readl(host->ioaddr + SDHSTS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) if (sdhsts & (SDHSTS_CRC16_ERROR |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) SDHSTS_CRC7_ERROR |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) SDHSTS_FIFO_ERROR)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) dev_err(dev, "%s transfer error - HSTS %08x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) is_read ? "read" : "write", sdhsts);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) host->data->error = -EILSEQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) } else if ((sdhsts & (SDHSTS_CMD_TIME_OUT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) SDHSTS_REW_TIME_OUT))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) dev_err(dev, "%s timeout error - HSTS %08x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) is_read ? "read" : "write", sdhsts);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) host->data->error = -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) static
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) void bcm2835_prepare_dma(struct bcm2835_host *host, struct mmc_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) int sg_len, dir_data, dir_slave;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) struct dma_async_tx_descriptor *desc = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) struct dma_chan *dma_chan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) dma_chan = host->dma_chan_rxtx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) if (data->flags & MMC_DATA_READ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) dir_data = DMA_FROM_DEVICE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) dir_slave = DMA_DEV_TO_MEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) dir_data = DMA_TO_DEVICE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) dir_slave = DMA_MEM_TO_DEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) /* The block doesn't manage the FIFO DREQs properly for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) * multi-block transfers, so don't attempt to DMA the final
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) * few words. Unfortunately this requires the final sg entry
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) * to be trimmed. N.B. This code demands that the overspill
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) * is contained in a single sg entry.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) host->drain_words = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) if ((data->blocks > 1) && (dir_data == DMA_FROM_DEVICE)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) struct scatterlist *sg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) u32 len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) len = min((u32)(FIFO_READ_THRESHOLD - 1) * 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) (u32)data->blocks * data->blksz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) for_each_sg(data->sg, sg, data->sg_len, i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) if (sg_is_last(sg)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) WARN_ON(sg->length < len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) sg->length -= len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) host->drain_page = sg_page(sg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) host->drain_offset = sg->offset + sg->length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) host->drain_words = len / 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) /* The parameters have already been validated, so this will not fail */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) (void)dmaengine_slave_config(dma_chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) (dir_data == DMA_FROM_DEVICE) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) &host->dma_cfg_rx :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) &host->dma_cfg_tx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) sg_len = dma_map_sg(dma_chan->device->dev, data->sg, data->sg_len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) dir_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) if (!sg_len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) desc = dmaengine_prep_slave_sg(dma_chan, data->sg, sg_len, dir_slave,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) if (!desc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) dma_unmap_sg(dma_chan->device->dev, data->sg, sg_len, dir_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) desc->callback = bcm2835_dma_complete;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) desc->callback_param = host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) host->dma_desc = desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) host->dma_chan = dma_chan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) host->dma_dir = dir_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) static void bcm2835_start_dma(struct bcm2835_host *host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) dmaengine_submit(host->dma_desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) dma_async_issue_pending(host->dma_chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) static void bcm2835_set_transfer_irqs(struct bcm2835_host *host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) u32 all_irqs = SDHCFG_DATA_IRPT_EN | SDHCFG_BLOCK_IRPT_EN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) SDHCFG_BUSY_IRPT_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) if (host->dma_desc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) host->hcfg = (host->hcfg & ~all_irqs) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) SDHCFG_BUSY_IRPT_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) host->hcfg = (host->hcfg & ~all_irqs) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) SDHCFG_DATA_IRPT_EN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) SDHCFG_BUSY_IRPT_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) writel(host->hcfg, host->ioaddr + SDHCFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) static
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) void bcm2835_prepare_data(struct bcm2835_host *host, struct mmc_command *cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) struct mmc_data *data = cmd->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) WARN_ON(host->data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) host->data = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) if (!data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) host->data_complete = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) host->data->bytes_xfered = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) if (!host->dma_desc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) /* Use PIO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) int flags = SG_MITER_ATOMIC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) if (data->flags & MMC_DATA_READ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) flags |= SG_MITER_TO_SG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) flags |= SG_MITER_FROM_SG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) host->blocks = data->blocks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) bcm2835_set_transfer_irqs(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) writel(data->blksz, host->ioaddr + SDHBCT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) writel(data->blocks, host->ioaddr + SDHBLC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) static u32 bcm2835_read_wait_sdcmd(struct bcm2835_host *host, u32 max_ms)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) struct device *dev = &host->pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) u32 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) ret = readl_poll_timeout(host->ioaddr + SDCMD, value,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) !(value & SDCMD_NEW_FLAG), 1, 10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) if (ret == -ETIMEDOUT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) /* if it takes a while make poll interval bigger */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) ret = readl_poll_timeout(host->ioaddr + SDCMD, value,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) !(value & SDCMD_NEW_FLAG),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) 10, max_ms * 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) if (ret == -ETIMEDOUT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) dev_err(dev, "%s: timeout (%d ms)\n", __func__, max_ms);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) return value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) static void bcm2835_finish_request(struct bcm2835_host *host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) struct dma_chan *terminate_chan = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) struct mmc_request *mrq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) cancel_delayed_work(&host->timeout_work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) mrq = host->mrq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) host->mrq = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) host->cmd = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) host->data = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) host->dma_desc = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) terminate_chan = host->dma_chan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) host->dma_chan = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) if (terminate_chan) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) int err = dmaengine_terminate_all(terminate_chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) dev_err(&host->pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) "failed to terminate DMA (%d)\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) mmc_request_done(mmc_from_priv(host), mrq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) static
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) bool bcm2835_send_command(struct bcm2835_host *host, struct mmc_command *cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) struct device *dev = &host->pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) u32 sdcmd, sdhsts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) unsigned long timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) WARN_ON(host->cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) sdcmd = bcm2835_read_wait_sdcmd(host, 100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) if (sdcmd & SDCMD_NEW_FLAG) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) dev_err(dev, "previous command never completed.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) bcm2835_dumpregs(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) cmd->error = -EILSEQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) bcm2835_finish_request(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) if (!cmd->data && cmd->busy_timeout > 9000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) timeout = DIV_ROUND_UP(cmd->busy_timeout, 1000) * HZ + HZ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) timeout = 10 * HZ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) schedule_delayed_work(&host->timeout_work, timeout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) host->cmd = cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) /* Clear any error flags */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) sdhsts = readl(host->ioaddr + SDHSTS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) if (sdhsts & SDHSTS_ERROR_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) writel(sdhsts, host->ioaddr + SDHSTS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) dev_err(dev, "unsupported response type!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) cmd->error = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) bcm2835_finish_request(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) bcm2835_prepare_data(host, cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) writel(cmd->arg, host->ioaddr + SDARG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) sdcmd = cmd->opcode & SDCMD_CMD_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) host->use_busy = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) if (!(cmd->flags & MMC_RSP_PRESENT)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) sdcmd |= SDCMD_NO_RESPONSE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) if (cmd->flags & MMC_RSP_136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) sdcmd |= SDCMD_LONG_RESPONSE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) if (cmd->flags & MMC_RSP_BUSY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) sdcmd |= SDCMD_BUSYWAIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) host->use_busy = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) if (cmd->data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) if (cmd->data->flags & MMC_DATA_WRITE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) sdcmd |= SDCMD_WRITE_CMD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) if (cmd->data->flags & MMC_DATA_READ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) sdcmd |= SDCMD_READ_CMD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) writel(sdcmd | SDCMD_NEW_FLAG, host->ioaddr + SDCMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) static void bcm2835_transfer_complete(struct bcm2835_host *host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) struct mmc_data *data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) WARN_ON(!host->data_complete);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) data = host->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) host->data = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) /* Need to send CMD12 if -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) * a) open-ended multiblock transfer (no CMD23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) * b) error in multiblock transfer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) if (host->mrq->stop && (data->error || !host->use_sbc)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) if (bcm2835_send_command(host, host->mrq->stop)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) /* No busy, so poll for completion */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) if (!host->use_busy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) bcm2835_finish_command(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) bcm2835_wait_transfer_complete(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) bcm2835_finish_request(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) static void bcm2835_finish_data(struct bcm2835_host *host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) struct device *dev = &host->pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) struct mmc_data *data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) data = host->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) host->hcfg &= ~(SDHCFG_DATA_IRPT_EN | SDHCFG_BLOCK_IRPT_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) writel(host->hcfg, host->ioaddr + SDHCFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) data->bytes_xfered = data->error ? 0 : (data->blksz * data->blocks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) host->data_complete = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) if (host->cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) /* Data managed to finish before the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) * command completed. Make sure we do
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) * things in the proper order.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) dev_dbg(dev, "Finished early - HSTS %08x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) readl(host->ioaddr + SDHSTS));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) bcm2835_transfer_complete(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) static void bcm2835_finish_command(struct bcm2835_host *host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) struct device *dev = &host->pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) struct mmc_command *cmd = host->cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) u32 sdcmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) sdcmd = bcm2835_read_wait_sdcmd(host, 100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) /* Check for errors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) if (sdcmd & SDCMD_NEW_FLAG) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) dev_err(dev, "command never completed.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) bcm2835_dumpregs(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) host->cmd->error = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) bcm2835_finish_request(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) } else if (sdcmd & SDCMD_FAIL_FLAG) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) u32 sdhsts = readl(host->ioaddr + SDHSTS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) /* Clear the errors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) writel(SDHSTS_ERROR_MASK, host->ioaddr + SDHSTS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) if (!(sdhsts & SDHSTS_CRC7_ERROR) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) (host->cmd->opcode != MMC_SEND_OP_COND)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) u32 edm, fsm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) if (sdhsts & SDHSTS_CMD_TIME_OUT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) host->cmd->error = -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) dev_err(dev, "unexpected command %d error\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) host->cmd->opcode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) bcm2835_dumpregs(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) host->cmd->error = -EILSEQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) edm = readl(host->ioaddr + SDEDM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) fsm = edm & SDEDM_FSM_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) if (fsm == SDEDM_FSM_READWAIT ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) fsm == SDEDM_FSM_WRITESTART1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) /* Kick the FSM out of its wait */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) writel(edm | SDEDM_FORCE_DATA_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) host->ioaddr + SDEDM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) bcm2835_finish_request(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) if (cmd->flags & MMC_RSP_PRESENT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) if (cmd->flags & MMC_RSP_136) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) for (i = 0; i < 4; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) cmd->resp[3 - i] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) readl(host->ioaddr + SDRSP0 + i * 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) cmd->resp[0] = readl(host->ioaddr + SDRSP0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) if (cmd == host->mrq->sbc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) /* Finished CMD23, now send actual command. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) host->cmd = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) if (bcm2835_send_command(host, host->mrq->cmd)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) if (host->data && host->dma_desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) /* DMA transfer starts now, PIO starts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) * after irq
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) bcm2835_start_dma(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) if (!host->use_busy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) bcm2835_finish_command(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) } else if (cmd == host->mrq->stop) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) /* Finished CMD12 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) bcm2835_finish_request(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) /* Processed actual command. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) host->cmd = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) if (!host->data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) bcm2835_finish_request(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) else if (host->data_complete)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) bcm2835_transfer_complete(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) static void bcm2835_timeout(struct work_struct *work)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) struct delayed_work *d = to_delayed_work(work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) struct bcm2835_host *host =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) container_of(d, struct bcm2835_host, timeout_work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) struct device *dev = &host->pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) mutex_lock(&host->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) if (host->mrq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) dev_err(dev, "timeout waiting for hardware interrupt.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) bcm2835_dumpregs(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) bcm2835_reset(mmc_from_priv(host));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) if (host->data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) host->data->error = -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) bcm2835_finish_data(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) if (host->cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) host->cmd->error = -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) host->mrq->cmd->error = -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) bcm2835_finish_request(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) mutex_unlock(&host->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) static bool bcm2835_check_cmd_error(struct bcm2835_host *host, u32 intmask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) struct device *dev = &host->pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) if (!(intmask & SDHSTS_ERROR_MASK))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) if (!host->cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) dev_err(dev, "sdhost_busy_irq: intmask %08x\n", intmask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) if (intmask & SDHSTS_CRC7_ERROR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) host->cmd->error = -EILSEQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) } else if (intmask & (SDHSTS_CRC16_ERROR |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) SDHSTS_FIFO_ERROR)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) if (host->mrq->data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) host->mrq->data->error = -EILSEQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) host->cmd->error = -EILSEQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) } else if (intmask & SDHSTS_REW_TIME_OUT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) if (host->mrq->data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) host->mrq->data->error = -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) host->cmd->error = -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) } else if (intmask & SDHSTS_CMD_TIME_OUT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) host->cmd->error = -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) bcm2835_dumpregs(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) static void bcm2835_check_data_error(struct bcm2835_host *host, u32 intmask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) if (!host->data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) if (intmask & (SDHSTS_CRC16_ERROR | SDHSTS_FIFO_ERROR))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) host->data->error = -EILSEQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) if (intmask & SDHSTS_REW_TIME_OUT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) host->data->error = -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) static void bcm2835_busy_irq(struct bcm2835_host *host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) if (WARN_ON(!host->cmd)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) bcm2835_dumpregs(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) if (WARN_ON(!host->use_busy)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) bcm2835_dumpregs(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) host->use_busy = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) bcm2835_finish_command(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) static void bcm2835_data_irq(struct bcm2835_host *host, u32 intmask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) /* There are no dedicated data/space available interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) * status bits, so it is necessary to use the single shared
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) * data/space available FIFO status bits. It is therefore not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) * an error to get here when there is no data transfer in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) * progress.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) if (!host->data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) bcm2835_check_data_error(host, intmask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) if (host->data->error)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) goto finished;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) if (host->data->flags & MMC_DATA_WRITE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) /* Use the block interrupt for writes after the first block */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) host->hcfg &= ~(SDHCFG_DATA_IRPT_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) host->hcfg |= SDHCFG_BLOCK_IRPT_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) writel(host->hcfg, host->ioaddr + SDHCFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) bcm2835_transfer_pio(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) bcm2835_transfer_pio(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) host->blocks--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) if ((host->blocks == 0) || host->data->error)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) goto finished;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) finished:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) host->hcfg &= ~(SDHCFG_DATA_IRPT_EN | SDHCFG_BLOCK_IRPT_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) writel(host->hcfg, host->ioaddr + SDHCFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) static void bcm2835_data_threaded_irq(struct bcm2835_host *host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) if (!host->data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) if ((host->blocks == 0) || host->data->error)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) bcm2835_finish_data(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) static void bcm2835_block_irq(struct bcm2835_host *host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) if (WARN_ON(!host->data)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) bcm2835_dumpregs(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) if (!host->dma_desc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) WARN_ON(!host->blocks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) if (host->data->error || (--host->blocks == 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) bcm2835_finish_data(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) bcm2835_transfer_pio(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) } else if (host->data->flags & MMC_DATA_WRITE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) bcm2835_finish_data(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) static irqreturn_t bcm2835_irq(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) irqreturn_t result = IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) struct bcm2835_host *host = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) u32 intmask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) spin_lock(&host->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) intmask = readl(host->ioaddr + SDHSTS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) writel(SDHSTS_BUSY_IRPT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) SDHSTS_BLOCK_IRPT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) SDHSTS_SDIO_IRPT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) SDHSTS_DATA_FLAG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) host->ioaddr + SDHSTS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) if (intmask & SDHSTS_BLOCK_IRPT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) bcm2835_check_data_error(host, intmask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) host->irq_block = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) result = IRQ_WAKE_THREAD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) if (intmask & SDHSTS_BUSY_IRPT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) if (!bcm2835_check_cmd_error(host, intmask)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) host->irq_busy = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) result = IRQ_WAKE_THREAD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) result = IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) /* There is no true data interrupt status bit, so it is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) * necessary to qualify the data flag with the interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) * enable bit.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) if ((intmask & SDHSTS_DATA_FLAG) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) (host->hcfg & SDHCFG_DATA_IRPT_EN)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) bcm2835_data_irq(host, intmask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) host->irq_data = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) result = IRQ_WAKE_THREAD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) spin_unlock(&host->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) return result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) static irqreturn_t bcm2835_threaded_irq(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) struct bcm2835_host *host = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) bool block, busy, data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) spin_lock_irqsave(&host->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) block = host->irq_block;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) busy = host->irq_busy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) data = host->irq_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) host->irq_block = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) host->irq_busy = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) host->irq_data = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) spin_unlock_irqrestore(&host->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) mutex_lock(&host->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) if (block)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) bcm2835_block_irq(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) if (busy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) bcm2835_busy_irq(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) if (data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) bcm2835_data_threaded_irq(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) mutex_unlock(&host->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) static void bcm2835_dma_complete_work(struct work_struct *work)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) struct bcm2835_host *host =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) container_of(work, struct bcm2835_host, dma_work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) struct mmc_data *data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) mutex_lock(&host->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) data = host->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) if (host->dma_chan) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) dma_unmap_sg(host->dma_chan->device->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) data->sg, data->sg_len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) host->dma_dir);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) host->dma_chan = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) if (host->drain_words) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) void *page;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) u32 *buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) if (host->drain_offset & PAGE_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) host->drain_page += host->drain_offset >> PAGE_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) host->drain_offset &= ~PAGE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) local_irq_save(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) page = kmap_atomic(host->drain_page);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) buf = page + host->drain_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) while (host->drain_words) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) u32 edm = readl(host->ioaddr + SDEDM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) if ((edm >> 4) & 0x1f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) *(buf++) = readl(host->ioaddr + SDDATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) host->drain_words--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) kunmap_atomic(page);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) local_irq_restore(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) bcm2835_finish_data(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) mutex_unlock(&host->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) static void bcm2835_set_clock(struct bcm2835_host *host, unsigned int clock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) struct mmc_host *mmc = mmc_from_priv(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) int div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) /* The SDCDIV register has 11 bits, and holds (div - 2). But
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) * in data mode the max is 50MHz wihout a minimum, and only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) * the bottom 3 bits are used. Since the switch over is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) * automatic (unless we have marked the card as slow...),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) * chosen values have to make sense in both modes. Ident mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) * must be 100-400KHz, so can range check the requested
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) * clock. CMD15 must be used to return to data mode, so this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) * can be monitored.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) * clock 250MHz -> 0->125MHz, 1->83.3MHz, 2->62.5MHz, 3->50.0MHz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) * 4->41.7MHz, 5->35.7MHz, 6->31.3MHz, 7->27.8MHz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) * 623->400KHz/27.8MHz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) * reset value (507)->491159/50MHz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) * BUT, the 3-bit clock divisor in data mode is too small if
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) * the core clock is higher than 250MHz, so instead use the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) * SLOW_CARD configuration bit to force the use of the ident
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) * clock divisor at all times.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) if (clock < 100000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) /* Can't stop the clock, but make it as slow as possible
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) * to show willing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) host->cdiv = SDCDIV_MAX_CDIV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) writel(host->cdiv, host->ioaddr + SDCDIV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) div = host->max_clk / clock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) if (div < 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) div = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) if ((host->max_clk / div) > clock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) div++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) div -= 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) if (div > SDCDIV_MAX_CDIV)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) div = SDCDIV_MAX_CDIV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) clock = host->max_clk / (div + 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) mmc->actual_clock = clock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) /* Calibrate some delays */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) host->ns_per_fifo_word = (1000000000 / clock) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) ((mmc->caps & MMC_CAP_4_BIT_DATA) ? 8 : 32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) host->cdiv = div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) writel(host->cdiv, host->ioaddr + SDCDIV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) /* Set the timeout to 500ms */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) writel(mmc->actual_clock / 2, host->ioaddr + SDTOUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) static void bcm2835_request(struct mmc_host *mmc, struct mmc_request *mrq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) struct bcm2835_host *host = mmc_priv(mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) struct device *dev = &host->pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) u32 edm, fsm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) /* Reset the error statuses in case this is a retry */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) if (mrq->sbc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) mrq->sbc->error = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) if (mrq->cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) mrq->cmd->error = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) if (mrq->data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) mrq->data->error = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) if (mrq->stop)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) mrq->stop->error = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) if (mrq->data && !is_power_of_2(mrq->data->blksz)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) dev_err(dev, "unsupported block size (%d bytes)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) mrq->data->blksz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) if (mrq->cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) mrq->cmd->error = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) mmc_request_done(mmc, mrq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) mutex_lock(&host->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) WARN_ON(host->mrq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) host->mrq = mrq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) edm = readl(host->ioaddr + SDEDM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) fsm = edm & SDEDM_FSM_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) if ((fsm != SDEDM_FSM_IDENTMODE) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) (fsm != SDEDM_FSM_DATAMODE)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) dev_err(dev, "previous command (%d) not complete (EDM %08x)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) readl(host->ioaddr + SDCMD) & SDCMD_CMD_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) edm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) bcm2835_dumpregs(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) if (mrq->cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) mrq->cmd->error = -EILSEQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) bcm2835_finish_request(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) mutex_unlock(&host->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) if (host->use_dma && mrq->data && (mrq->data->blocks > PIO_THRESHOLD))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) bcm2835_prepare_dma(host, mrq->data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) host->use_sbc = !!mrq->sbc && host->mrq->data &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) (host->mrq->data->flags & MMC_DATA_READ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) if (host->use_sbc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) if (bcm2835_send_command(host, mrq->sbc)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) if (!host->use_busy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) bcm2835_finish_command(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) } else if (mrq->cmd && bcm2835_send_command(host, mrq->cmd)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) if (host->data && host->dma_desc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) /* DMA transfer starts now, PIO starts after irq */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) bcm2835_start_dma(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) if (!host->use_busy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) bcm2835_finish_command(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) mutex_unlock(&host->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) static void bcm2835_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) struct bcm2835_host *host = mmc_priv(mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) mutex_lock(&host->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) if (!ios->clock || ios->clock != host->clock) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) bcm2835_set_clock(host, ios->clock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) host->clock = ios->clock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) /* set bus width */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) host->hcfg &= ~SDHCFG_WIDE_EXT_BUS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) if (ios->bus_width == MMC_BUS_WIDTH_4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) host->hcfg |= SDHCFG_WIDE_EXT_BUS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) host->hcfg |= SDHCFG_WIDE_INT_BUS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) /* Disable clever clock switching, to cope with fast core clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) host->hcfg |= SDHCFG_SLOW_CARD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) writel(host->hcfg, host->ioaddr + SDHCFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) mutex_unlock(&host->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) static const struct mmc_host_ops bcm2835_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) .request = bcm2835_request,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) .set_ios = bcm2835_set_ios,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) .hw_reset = bcm2835_reset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) static int bcm2835_add_host(struct bcm2835_host *host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) struct mmc_host *mmc = mmc_from_priv(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) struct device *dev = &host->pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) char pio_limit_string[20];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) if (!mmc->f_max || mmc->f_max > host->max_clk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) mmc->f_max = host->max_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) mmc->f_min = host->max_clk / SDCDIV_MAX_CDIV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) mmc->max_busy_timeout = ~0 / (mmc->f_max / 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) dev_dbg(dev, "f_max %d, f_min %d, max_busy_timeout %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) mmc->f_max, mmc->f_min, mmc->max_busy_timeout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) /* host controller capabilities */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) mmc->caps |= MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) MMC_CAP_NEEDS_POLL | MMC_CAP_HW_RESET | MMC_CAP_CMD23;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) spin_lock_init(&host->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) mutex_init(&host->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) if (!host->dma_chan_rxtx) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) dev_warn(dev, "unable to initialise DMA channel. Falling back to PIO\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) host->use_dma = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) host->use_dma = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) host->dma_cfg_tx.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) host->dma_cfg_tx.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) host->dma_cfg_tx.slave_id = 13; /* DREQ channel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) host->dma_cfg_tx.direction = DMA_MEM_TO_DEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) host->dma_cfg_tx.src_addr = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) host->dma_cfg_tx.dst_addr = host->phys_addr + SDDATA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) host->dma_cfg_rx.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) host->dma_cfg_rx.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) host->dma_cfg_rx.slave_id = 13; /* DREQ channel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) host->dma_cfg_rx.direction = DMA_DEV_TO_MEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) host->dma_cfg_rx.src_addr = host->phys_addr + SDDATA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) host->dma_cfg_rx.dst_addr = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) if (dmaengine_slave_config(host->dma_chan_rxtx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) &host->dma_cfg_tx) != 0 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) dmaengine_slave_config(host->dma_chan_rxtx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) &host->dma_cfg_rx) != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) host->use_dma = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) mmc->max_segs = 128;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) mmc->max_req_size = min_t(size_t, 524288, dma_max_mapping_size(dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) mmc->max_seg_size = mmc->max_req_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) mmc->max_blk_size = 1024;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) mmc->max_blk_count = 65535;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) /* report supported voltage ranges */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) INIT_WORK(&host->dma_work, bcm2835_dma_complete_work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) INIT_DELAYED_WORK(&host->timeout_work, bcm2835_timeout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) /* Set interrupt enables */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) host->hcfg = SDHCFG_BUSY_IRPT_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) bcm2835_reset_internal(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) ret = request_threaded_irq(host->irq, bcm2835_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) bcm2835_threaded_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) 0, mmc_hostname(mmc), host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) dev_err(dev, "failed to request IRQ %d: %d\n", host->irq, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) ret = mmc_add_host(mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) free_irq(host->irq, host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) pio_limit_string[0] = '\0';
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) if (host->use_dma && (PIO_THRESHOLD > 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) sprintf(pio_limit_string, " (>%d)", PIO_THRESHOLD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) dev_info(dev, "loaded - DMA %s%s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) host->use_dma ? "enabled" : "disabled", pio_limit_string);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) static int bcm2835_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) struct bcm2835_host *host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) struct mmc_host *mmc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) const __be32 *regaddr_p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) dev_dbg(dev, "%s\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) mmc = mmc_alloc_host(sizeof(*host), dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) if (!mmc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) mmc->ops = &bcm2835_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) host = mmc_priv(mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) host->pdev = pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) spin_lock_init(&host->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) host->ioaddr = devm_platform_ioremap_resource(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) if (IS_ERR(host->ioaddr)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) ret = PTR_ERR(host->ioaddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) /* Parse OF address directly to get the physical address for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) * DMA to our registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) regaddr_p = of_get_address(pdev->dev.of_node, 0, NULL, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) if (!regaddr_p) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) dev_err(dev, "Can't get phys address\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) host->phys_addr = be32_to_cpup(regaddr_p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) host->dma_chan = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) host->dma_desc = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) host->dma_chan_rxtx = dma_request_chan(dev, "rx-tx");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) if (IS_ERR(host->dma_chan_rxtx)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) ret = PTR_ERR(host->dma_chan_rxtx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) host->dma_chan_rxtx = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) if (ret == -EPROBE_DEFER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) /* Ignore errors to fall back to PIO mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) clk = devm_clk_get(dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) if (IS_ERR(clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) ret = dev_err_probe(dev, PTR_ERR(clk), "could not get clk\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) host->max_clk = clk_get_rate(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) host->irq = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) if (host->irq <= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) ret = mmc_of_parse(mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) ret = bcm2835_add_host(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) platform_set_drvdata(pdev, host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) dev_dbg(dev, "%s -> OK\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) dev_dbg(dev, "%s -> err %d\n", __func__, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) if (host->dma_chan_rxtx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) dma_release_channel(host->dma_chan_rxtx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) mmc_free_host(mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) static int bcm2835_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) struct bcm2835_host *host = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) struct mmc_host *mmc = mmc_from_priv(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) mmc_remove_host(mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) writel(SDVDD_POWER_OFF, host->ioaddr + SDVDD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) free_irq(host->irq, host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) cancel_work_sync(&host->dma_work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) cancel_delayed_work_sync(&host->timeout_work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) if (host->dma_chan_rxtx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) dma_release_channel(host->dma_chan_rxtx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) mmc_free_host(mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) static const struct of_device_id bcm2835_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) { .compatible = "brcm,bcm2835-sdhost" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) MODULE_DEVICE_TABLE(of, bcm2835_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) static struct platform_driver bcm2835_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) .probe = bcm2835_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) .remove = bcm2835_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) .name = "sdhost-bcm2835",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) .probe_type = PROBE_PREFER_ASYNCHRONOUS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) .of_match_table = bcm2835_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) module_platform_driver(bcm2835_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) MODULE_ALIAS("platform:sdhost-bcm2835");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) MODULE_DESCRIPTION("BCM2835 SDHost driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) MODULE_LICENSE("GPL v2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) MODULE_AUTHOR("Phil Elwell");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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