^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * linux/drivers/mmc/host/au1xmmc.c - AU1XX0 MMC driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (c) 2005, Advanced Micro Devices, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Developed with help from the 2.4.30 MMC AU1XXX controller including
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * the following copyright notices:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Copyright (c) 2003-2004 Embedded Edge, LLC.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * Portions Copyright (C) 2002 Embedix, Inc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * Copyright 2002 Hewlett-Packard Company
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * 2.6 version of this driver inspired by:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * (drivers/mmc/wbsd.c) Copyright (C) 2004-2005 Pierre Ossman,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * All Rights Reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * (drivers/mmc/pxa.c) Copyright (C) 2003 Russell King,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * All Rights Reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) /* Why don't we use the SD controllers' carddetect feature?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) * From the AU1100 MMC application guide:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * If the Au1100-based design is intended to support both MultiMediaCards
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) * and 1- or 4-data bit SecureDigital cards, then the solution is to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) * connect a weak (560KOhm) pull-up resistor to connector pin 1.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) * In doing so, a MMC card never enters SPI-mode communications,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) * but now the SecureDigital card-detect feature of CD/DAT3 is ineffective
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) * (the low to high transition will not occur).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #include <linux/mm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #include <linux/dma-mapping.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #include <linux/scatterlist.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #include <linux/highmem.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #include <linux/leds.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #include <linux/mmc/host.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #include <asm/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #include <asm/mach-au1x00/au1000.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #include <asm/mach-au1x00/au1xxx_dbdma.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #include <asm/mach-au1x00/au1100_mmc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define DRIVER_NAME "au1xxx-mmc"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) /* Set this to enable special debugging macros */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) /* #define DEBUG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #ifdef DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define DBG(fmt, idx, args...) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) pr_debug("au1xmmc(%d): DEBUG: " fmt, idx, ##args)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define DBG(fmt, idx, args...) do {} while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) /* Hardware definitions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define AU1XMMC_DESCRIPTOR_COUNT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) /* max DMA seg size: 64KB on Au1100, 4MB on Au1200 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define AU1100_MMC_DESCRIPTOR_SIZE 0x0000ffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define AU1200_MMC_DESCRIPTOR_SIZE 0x003fffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define AU1XMMC_OCR (MMC_VDD_27_28 | MMC_VDD_28_29 | MMC_VDD_29_30 | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) MMC_VDD_30_31 | MMC_VDD_31_32 | MMC_VDD_32_33 | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) MMC_VDD_33_34 | MMC_VDD_34_35 | MMC_VDD_35_36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) /* This gives us a hard value for the stop command that we can write directly
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) * to the command register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define STOP_CMD \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) (SD_CMD_RT_1B | SD_CMD_CT_7 | (0xC << SD_CMD_CI_SHIFT) | SD_CMD_GO)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) /* This is the set of interrupts that we configure by default. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define AU1XMMC_INTERRUPTS \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) (SD_CONFIG_SC | SD_CONFIG_DT | SD_CONFIG_RAT | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) SD_CONFIG_CR | SD_CONFIG_I)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) /* The poll event (looking for insert/remove events runs twice a second. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define AU1XMMC_DETECT_TIMEOUT (HZ/2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) struct au1xmmc_host {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) struct mmc_host *mmc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) struct mmc_request *mrq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) u32 flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) void __iomem *iobase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) u32 clock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) u32 bus_width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) u32 power_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) int status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) int len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) int dir;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) } dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) int index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) int offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) int len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) } pio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) u32 tx_chan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) u32 rx_chan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) struct tasklet_struct finish_task;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) struct tasklet_struct data_task;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) struct au1xmmc_platform_data *platdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) struct platform_device *pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) struct resource *ioarea;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) /* Status flags used by the host structure */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define HOST_F_XMIT 0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define HOST_F_RECV 0x0002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define HOST_F_DMA 0x0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define HOST_F_DBDMA 0x0020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define HOST_F_ACTIVE 0x0100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define HOST_F_STOP 0x1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define HOST_S_IDLE 0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define HOST_S_CMD 0x0002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define HOST_S_DATA 0x0003
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define HOST_S_STOP 0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) /* Easy access macros */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define HOST_STATUS(h) ((h)->iobase + SD_STATUS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define HOST_CONFIG(h) ((h)->iobase + SD_CONFIG)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define HOST_ENABLE(h) ((h)->iobase + SD_ENABLE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define HOST_TXPORT(h) ((h)->iobase + SD_TXPORT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define HOST_RXPORT(h) ((h)->iobase + SD_RXPORT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define HOST_CMDARG(h) ((h)->iobase + SD_CMDARG)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define HOST_BLKSIZE(h) ((h)->iobase + SD_BLKSIZE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define HOST_CMD(h) ((h)->iobase + SD_CMD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define HOST_CONFIG2(h) ((h)->iobase + SD_CONFIG2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define HOST_TIMEOUT(h) ((h)->iobase + SD_TIMEOUT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define HOST_DEBUG(h) ((h)->iobase + SD_DEBUG)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define DMA_CHANNEL(h) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) (((h)->flags & HOST_F_XMIT) ? (h)->tx_chan : (h)->rx_chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) static inline int has_dbdma(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) switch (alchemy_get_cputype()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) case ALCHEMY_CPU_AU1200:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) case ALCHEMY_CPU_AU1300:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) static inline void IRQ_ON(struct au1xmmc_host *host, u32 mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) u32 val = __raw_readl(HOST_CONFIG(host));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) val |= mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) __raw_writel(val, HOST_CONFIG(host));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) wmb(); /* drain writebuffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) static inline void FLUSH_FIFO(struct au1xmmc_host *host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) u32 val = __raw_readl(HOST_CONFIG2(host));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) __raw_writel(val | SD_CONFIG2_FF, HOST_CONFIG2(host));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) wmb(); /* drain writebuffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) mdelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) /* SEND_STOP will turn off clock control - this re-enables it */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) val &= ~SD_CONFIG2_DF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) __raw_writel(val, HOST_CONFIG2(host));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) wmb(); /* drain writebuffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) static inline void IRQ_OFF(struct au1xmmc_host *host, u32 mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) u32 val = __raw_readl(HOST_CONFIG(host));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) val &= ~mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) __raw_writel(val, HOST_CONFIG(host));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) wmb(); /* drain writebuffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) static inline void SEND_STOP(struct au1xmmc_host *host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) u32 config2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) WARN_ON(host->status != HOST_S_DATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) host->status = HOST_S_STOP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) config2 = __raw_readl(HOST_CONFIG2(host));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) __raw_writel(config2 | SD_CONFIG2_DF, HOST_CONFIG2(host));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) wmb(); /* drain writebuffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) /* Send the stop command */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) __raw_writel(STOP_CMD, HOST_CMD(host));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) wmb(); /* drain writebuffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) static void au1xmmc_set_power(struct au1xmmc_host *host, int state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) if (host->platdata && host->platdata->set_power)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) host->platdata->set_power(host->mmc, state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) static int au1xmmc_card_inserted(struct mmc_host *mmc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) struct au1xmmc_host *host = mmc_priv(mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) if (host->platdata && host->platdata->card_inserted)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) return !!host->platdata->card_inserted(host->mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) return -ENOSYS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) static int au1xmmc_card_readonly(struct mmc_host *mmc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) struct au1xmmc_host *host = mmc_priv(mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) if (host->platdata && host->platdata->card_readonly)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) return !!host->platdata->card_readonly(mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) return -ENOSYS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) static void au1xmmc_finish_request(struct au1xmmc_host *host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) struct mmc_request *mrq = host->mrq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) host->mrq = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) host->flags &= HOST_F_ACTIVE | HOST_F_DMA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) host->dma.len = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) host->dma.dir = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) host->pio.index = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) host->pio.offset = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) host->pio.len = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) host->status = HOST_S_IDLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) mmc_request_done(host->mmc, mrq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) static void au1xmmc_tasklet_finish(unsigned long param)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) struct au1xmmc_host *host = (struct au1xmmc_host *) param;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) au1xmmc_finish_request(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) static int au1xmmc_send_command(struct au1xmmc_host *host,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) struct mmc_command *cmd, struct mmc_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) u32 mmccmd = (cmd->opcode << SD_CMD_CI_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) switch (mmc_resp_type(cmd)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) case MMC_RSP_NONE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) case MMC_RSP_R1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) mmccmd |= SD_CMD_RT_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) case MMC_RSP_R1B:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) mmccmd |= SD_CMD_RT_1B;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) case MMC_RSP_R2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) mmccmd |= SD_CMD_RT_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) case MMC_RSP_R3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) mmccmd |= SD_CMD_RT_3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) pr_info("au1xmmc: unhandled response type %02x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) mmc_resp_type(cmd));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) if (data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) if (data->flags & MMC_DATA_READ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) if (data->blocks > 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) mmccmd |= SD_CMD_CT_4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) mmccmd |= SD_CMD_CT_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) } else if (data->flags & MMC_DATA_WRITE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) if (data->blocks > 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) mmccmd |= SD_CMD_CT_3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) mmccmd |= SD_CMD_CT_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) __raw_writel(cmd->arg, HOST_CMDARG(host));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) wmb(); /* drain writebuffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) __raw_writel((mmccmd | SD_CMD_GO), HOST_CMD(host));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) wmb(); /* drain writebuffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) /* Wait for the command to go on the line */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) while (__raw_readl(HOST_CMD(host)) & SD_CMD_GO)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) /* nop */;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) static void au1xmmc_data_complete(struct au1xmmc_host *host, u32 status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) struct mmc_request *mrq = host->mrq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) struct mmc_data *data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) u32 crc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) WARN_ON((host->status != HOST_S_DATA) && (host->status != HOST_S_STOP));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) if (host->mrq == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) data = mrq->cmd->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) if (status == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) status = __raw_readl(HOST_STATUS(host));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) /* The transaction is really over when the SD_STATUS_DB bit is clear */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) while ((host->flags & HOST_F_XMIT) && (status & SD_STATUS_DB))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) status = __raw_readl(HOST_STATUS(host));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) data->error = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len, host->dma.dir);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) /* Process any errors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) crc = (status & (SD_STATUS_WC | SD_STATUS_RC));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) if (host->flags & HOST_F_XMIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) crc |= ((status & 0x07) == 0x02) ? 0 : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) if (crc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) data->error = -EILSEQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) /* Clear the CRC bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) __raw_writel(SD_STATUS_WC | SD_STATUS_RC, HOST_STATUS(host));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) data->bytes_xfered = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) if (!data->error) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) if (host->flags & (HOST_F_DMA | HOST_F_DBDMA)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) u32 chan = DMA_CHANNEL(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) chan_tab_t *c = *((chan_tab_t **)chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) au1x_dma_chan_t *cp = c->chan_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) data->bytes_xfered = cp->ddma_bytecnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) data->bytes_xfered =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) (data->blocks * data->blksz) - host->pio.len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) au1xmmc_finish_request(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) static void au1xmmc_tasklet_data(unsigned long param)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) struct au1xmmc_host *host = (struct au1xmmc_host *)param;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) u32 status = __raw_readl(HOST_STATUS(host));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) au1xmmc_data_complete(host, status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) #define AU1XMMC_MAX_TRANSFER 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) static void au1xmmc_send_pio(struct au1xmmc_host *host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) struct mmc_data *data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) int sg_len, max, count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) unsigned char *sg_ptr, val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) u32 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) struct scatterlist *sg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) data = host->mrq->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) if (!(host->flags & HOST_F_XMIT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) /* This is the pointer to the data buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) sg = &data->sg[host->pio.index];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) sg_ptr = kmap_atomic(sg_page(sg)) + sg->offset + host->pio.offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) /* This is the space left inside the buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) sg_len = data->sg[host->pio.index].length - host->pio.offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) /* Check if we need less than the size of the sg_buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) max = (sg_len > host->pio.len) ? host->pio.len : sg_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) if (max > AU1XMMC_MAX_TRANSFER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) max = AU1XMMC_MAX_TRANSFER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) for (count = 0; count < max; count++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) status = __raw_readl(HOST_STATUS(host));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) if (!(status & SD_STATUS_TH))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) val = sg_ptr[count];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) __raw_writel((unsigned long)val, HOST_TXPORT(host));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) wmb(); /* drain writebuffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) kunmap_atomic(sg_ptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) host->pio.len -= count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) host->pio.offset += count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) if (count == sg_len) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) host->pio.index++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) host->pio.offset = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) if (host->pio.len == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) IRQ_OFF(host, SD_CONFIG_TH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) if (host->flags & HOST_F_STOP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) SEND_STOP(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) tasklet_schedule(&host->data_task);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) static void au1xmmc_receive_pio(struct au1xmmc_host *host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) struct mmc_data *data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) int max, count, sg_len = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) unsigned char *sg_ptr = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) u32 status, val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) struct scatterlist *sg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) data = host->mrq->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) if (!(host->flags & HOST_F_RECV))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) max = host->pio.len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) if (host->pio.index < host->dma.len) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) sg = &data->sg[host->pio.index];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) sg_ptr = kmap_atomic(sg_page(sg)) + sg->offset + host->pio.offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) /* This is the space left inside the buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) sg_len = sg_dma_len(&data->sg[host->pio.index]) - host->pio.offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) /* Check if we need less than the size of the sg_buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) if (sg_len < max)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) max = sg_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) if (max > AU1XMMC_MAX_TRANSFER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) max = AU1XMMC_MAX_TRANSFER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) for (count = 0; count < max; count++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) status = __raw_readl(HOST_STATUS(host));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) if (!(status & SD_STATUS_NE))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) if (status & SD_STATUS_RC) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) DBG("RX CRC Error [%d + %d].\n", host->pdev->id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) host->pio.len, count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) if (status & SD_STATUS_RO) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) DBG("RX Overrun [%d + %d]\n", host->pdev->id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) host->pio.len, count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) else if (status & SD_STATUS_RU) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) DBG("RX Underrun [%d + %d]\n", host->pdev->id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) host->pio.len, count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) val = __raw_readl(HOST_RXPORT(host));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) if (sg_ptr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) sg_ptr[count] = (unsigned char)(val & 0xFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) if (sg_ptr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) kunmap_atomic(sg_ptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) host->pio.len -= count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) host->pio.offset += count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) if (sg_len && count == sg_len) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) host->pio.index++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) host->pio.offset = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) if (host->pio.len == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) /* IRQ_OFF(host, SD_CONFIG_RA | SD_CONFIG_RF); */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) IRQ_OFF(host, SD_CONFIG_NE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) if (host->flags & HOST_F_STOP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) SEND_STOP(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) tasklet_schedule(&host->data_task);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) /* This is called when a command has been completed - grab the response
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) * and check for errors. Then start the data transfer if it is indicated.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) static void au1xmmc_cmd_complete(struct au1xmmc_host *host, u32 status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) struct mmc_request *mrq = host->mrq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) struct mmc_command *cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) u32 r[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) int i, trans;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) if (!host->mrq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) cmd = mrq->cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) cmd->error = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) if (cmd->flags & MMC_RSP_PRESENT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) if (cmd->flags & MMC_RSP_136) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) r[0] = __raw_readl(host->iobase + SD_RESP3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) r[1] = __raw_readl(host->iobase + SD_RESP2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) r[2] = __raw_readl(host->iobase + SD_RESP1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) r[3] = __raw_readl(host->iobase + SD_RESP0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) /* The CRC is omitted from the response, so really
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) * we only got 120 bytes, but the engine expects
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) * 128 bits, so we have to shift things up.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) for (i = 0; i < 4; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) cmd->resp[i] = (r[i] & 0x00FFFFFF) << 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) if (i != 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) cmd->resp[i] |= (r[i + 1] & 0xFF000000) >> 24;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) /* Techincally, we should be getting all 48 bits of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) * the response (SD_RESP1 + SD_RESP2), but because
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) * our response omits the CRC, our data ends up
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) * being shifted 8 bits to the right. In this case,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) * that means that the OSR data starts at bit 31,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) * so we can just read RESP0 and return that.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) cmd->resp[0] = __raw_readl(host->iobase + SD_RESP0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) /* Figure out errors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) if (status & (SD_STATUS_SC | SD_STATUS_WC | SD_STATUS_RC))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) cmd->error = -EILSEQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) trans = host->flags & (HOST_F_XMIT | HOST_F_RECV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) if (!trans || cmd->error) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) IRQ_OFF(host, SD_CONFIG_TH | SD_CONFIG_RA | SD_CONFIG_RF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) tasklet_schedule(&host->finish_task);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) host->status = HOST_S_DATA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) if ((host->flags & (HOST_F_DMA | HOST_F_DBDMA))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) u32 channel = DMA_CHANNEL(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) /* Start the DBDMA as soon as the buffer gets something in it */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) if (host->flags & HOST_F_RECV) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) u32 mask = SD_STATUS_DB | SD_STATUS_NE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) while((status & mask) != mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) status = __raw_readl(HOST_STATUS(host));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) au1xxx_dbdma_start(channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) static void au1xmmc_set_clock(struct au1xmmc_host *host, int rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) unsigned int pbus = clk_get_rate(host->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) unsigned int divisor = ((pbus / rate) / 2) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) u32 config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) config = __raw_readl(HOST_CONFIG(host));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) config &= ~(SD_CONFIG_DIV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) config |= (divisor & SD_CONFIG_DIV) | SD_CONFIG_DE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) __raw_writel(config, HOST_CONFIG(host));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) wmb(); /* drain writebuffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) static int au1xmmc_prepare_data(struct au1xmmc_host *host,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) struct mmc_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) int datalen = data->blocks * data->blksz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) if (data->flags & MMC_DATA_READ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) host->flags |= HOST_F_RECV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) host->flags |= HOST_F_XMIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) if (host->mrq->stop)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) host->flags |= HOST_F_STOP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) host->dma.dir = DMA_BIDIRECTIONAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) host->dma.len = dma_map_sg(mmc_dev(host->mmc), data->sg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) data->sg_len, host->dma.dir);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) if (host->dma.len == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) __raw_writel(data->blksz - 1, HOST_BLKSIZE(host));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) if (host->flags & (HOST_F_DMA | HOST_F_DBDMA)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) u32 channel = DMA_CHANNEL(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) au1xxx_dbdma_stop(channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) for (i = 0; i < host->dma.len; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) u32 ret = 0, flags = DDMA_FLAGS_NOIE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) struct scatterlist *sg = &data->sg[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) int sg_len = sg->length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) int len = (datalen > sg_len) ? sg_len : datalen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) if (i == host->dma.len - 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) flags = DDMA_FLAGS_IE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) if (host->flags & HOST_F_XMIT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) ret = au1xxx_dbdma_put_source(channel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) sg_phys(sg), len, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) ret = au1xxx_dbdma_put_dest(channel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) sg_phys(sg), len, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) goto dataerr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) datalen -= len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) host->pio.index = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) host->pio.offset = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) host->pio.len = datalen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) if (host->flags & HOST_F_XMIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) IRQ_ON(host, SD_CONFIG_TH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) IRQ_ON(host, SD_CONFIG_NE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) /* IRQ_ON(host, SD_CONFIG_RA | SD_CONFIG_RF); */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) dataerr:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) host->dma.dir);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) /* This actually starts a command or data transaction */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) static void au1xmmc_request(struct mmc_host* mmc, struct mmc_request* mrq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) struct au1xmmc_host *host = mmc_priv(mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) WARN_ON(irqs_disabled());
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) WARN_ON(host->status != HOST_S_IDLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) host->mrq = mrq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) host->status = HOST_S_CMD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) /* fail request immediately if no card is present */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) if (0 == au1xmmc_card_inserted(mmc)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) mrq->cmd->error = -ENOMEDIUM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) au1xmmc_finish_request(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) if (mrq->data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) FLUSH_FIFO(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) ret = au1xmmc_prepare_data(host, mrq->data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) ret = au1xmmc_send_command(host, mrq->cmd, mrq->data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) mrq->cmd->error = ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) au1xmmc_finish_request(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) static void au1xmmc_reset_controller(struct au1xmmc_host *host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) /* Apply the clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) __raw_writel(SD_ENABLE_CE, HOST_ENABLE(host));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) wmb(); /* drain writebuffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) mdelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) __raw_writel(SD_ENABLE_R | SD_ENABLE_CE, HOST_ENABLE(host));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) wmb(); /* drain writebuffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) mdelay(5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) __raw_writel(~0, HOST_STATUS(host));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) wmb(); /* drain writebuffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) __raw_writel(0, HOST_BLKSIZE(host));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) __raw_writel(0x001fffff, HOST_TIMEOUT(host));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) wmb(); /* drain writebuffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) __raw_writel(SD_CONFIG2_EN, HOST_CONFIG2(host));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) wmb(); /* drain writebuffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) __raw_writel(SD_CONFIG2_EN | SD_CONFIG2_FF, HOST_CONFIG2(host));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) wmb(); /* drain writebuffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) mdelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) __raw_writel(SD_CONFIG2_EN, HOST_CONFIG2(host));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) wmb(); /* drain writebuffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) /* Configure interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) __raw_writel(AU1XMMC_INTERRUPTS, HOST_CONFIG(host));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) wmb(); /* drain writebuffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) static void au1xmmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) struct au1xmmc_host *host = mmc_priv(mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) u32 config2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) if (ios->power_mode == MMC_POWER_OFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) au1xmmc_set_power(host, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) else if (ios->power_mode == MMC_POWER_ON) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) au1xmmc_set_power(host, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) if (ios->clock && ios->clock != host->clock) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) au1xmmc_set_clock(host, ios->clock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) host->clock = ios->clock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) config2 = __raw_readl(HOST_CONFIG2(host));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) switch (ios->bus_width) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) case MMC_BUS_WIDTH_8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) config2 |= SD_CONFIG2_BB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) case MMC_BUS_WIDTH_4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) config2 &= ~SD_CONFIG2_BB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) config2 |= SD_CONFIG2_WB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) case MMC_BUS_WIDTH_1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) config2 &= ~(SD_CONFIG2_WB | SD_CONFIG2_BB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) __raw_writel(config2, HOST_CONFIG2(host));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) wmb(); /* drain writebuffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) #define STATUS_TIMEOUT (SD_STATUS_RAT | SD_STATUS_DT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) #define STATUS_DATA_IN (SD_STATUS_NE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) #define STATUS_DATA_OUT (SD_STATUS_TH)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) static irqreturn_t au1xmmc_irq(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) struct au1xmmc_host *host = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) u32 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) status = __raw_readl(HOST_STATUS(host));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) if (!(status & SD_STATUS_I))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) return IRQ_NONE; /* not ours */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) if (status & SD_STATUS_SI) /* SDIO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) mmc_signal_sdio_irq(host->mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) if (host->mrq && (status & STATUS_TIMEOUT)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) if (status & SD_STATUS_RAT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) host->mrq->cmd->error = -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) else if (status & SD_STATUS_DT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) host->mrq->data->error = -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) /* In PIO mode, interrupts might still be enabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) IRQ_OFF(host, SD_CONFIG_NE | SD_CONFIG_TH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) /* IRQ_OFF(host, SD_CONFIG_TH | SD_CONFIG_RA | SD_CONFIG_RF); */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) tasklet_schedule(&host->finish_task);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) #if 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) else if (status & SD_STATUS_DD) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) /* Sometimes we get a DD before a NE in PIO mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) if (!(host->flags & HOST_F_DMA) && (status & SD_STATUS_NE))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) au1xmmc_receive_pio(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) au1xmmc_data_complete(host, status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) /* tasklet_schedule(&host->data_task); */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) else if (status & SD_STATUS_CR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) if (host->status == HOST_S_CMD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) au1xmmc_cmd_complete(host, status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) } else if (!(host->flags & HOST_F_DMA)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) if ((host->flags & HOST_F_XMIT) && (status & STATUS_DATA_OUT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) au1xmmc_send_pio(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) else if ((host->flags & HOST_F_RECV) && (status & STATUS_DATA_IN))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) au1xmmc_receive_pio(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) } else if (status & 0x203F3C70) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) DBG("Unhandled status %8.8x\n", host->pdev->id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) __raw_writel(status, HOST_STATUS(host));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) wmb(); /* drain writebuffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) /* 8bit memory DMA device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) static dbdev_tab_t au1xmmc_mem_dbdev = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) .dev_id = DSCR_CMD0_ALWAYS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) .dev_flags = DEV_FLAGS_ANYUSE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) .dev_tsize = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) .dev_devwidth = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) .dev_physaddr = 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) .dev_intlevel = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) .dev_intpolarity = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) static int memid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) static void au1xmmc_dbdma_callback(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) struct au1xmmc_host *host = (struct au1xmmc_host *)dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) /* Avoid spurious interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) if (!host->mrq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) if (host->flags & HOST_F_STOP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) SEND_STOP(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) tasklet_schedule(&host->data_task);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) static int au1xmmc_dbdma_init(struct au1xmmc_host *host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) int txid, rxid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) res = platform_get_resource(host->pdev, IORESOURCE_DMA, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) if (!res)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) txid = res->start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) res = platform_get_resource(host->pdev, IORESOURCE_DMA, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) if (!res)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) rxid = res->start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) if (!memid)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) host->tx_chan = au1xxx_dbdma_chan_alloc(memid, txid,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) au1xmmc_dbdma_callback, (void *)host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) if (!host->tx_chan) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) dev_err(&host->pdev->dev, "cannot allocate TX DMA\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) host->rx_chan = au1xxx_dbdma_chan_alloc(rxid, memid,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) au1xmmc_dbdma_callback, (void *)host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) if (!host->rx_chan) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) dev_err(&host->pdev->dev, "cannot allocate RX DMA\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) au1xxx_dbdma_chan_free(host->tx_chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) au1xxx_dbdma_set_devwidth(host->tx_chan, 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) au1xxx_dbdma_set_devwidth(host->rx_chan, 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) au1xxx_dbdma_ring_alloc(host->tx_chan, AU1XMMC_DESCRIPTOR_COUNT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) au1xxx_dbdma_ring_alloc(host->rx_chan, AU1XMMC_DESCRIPTOR_COUNT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) /* DBDMA is good to go */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) host->flags |= HOST_F_DMA | HOST_F_DBDMA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) static void au1xmmc_dbdma_shutdown(struct au1xmmc_host *host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) if (host->flags & HOST_F_DMA) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) host->flags &= ~HOST_F_DMA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) au1xxx_dbdma_chan_free(host->tx_chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) au1xxx_dbdma_chan_free(host->rx_chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) static void au1xmmc_enable_sdio_irq(struct mmc_host *mmc, int en)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) struct au1xmmc_host *host = mmc_priv(mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) if (en)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) IRQ_ON(host, SD_CONFIG_SI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) IRQ_OFF(host, SD_CONFIG_SI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) static const struct mmc_host_ops au1xmmc_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) .request = au1xmmc_request,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) .set_ios = au1xmmc_set_ios,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) .get_ro = au1xmmc_card_readonly,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) .get_cd = au1xmmc_card_inserted,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) .enable_sdio_irq = au1xmmc_enable_sdio_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) static int au1xmmc_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) struct mmc_host *mmc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) struct au1xmmc_host *host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) struct resource *r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) int ret, iflag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) mmc = mmc_alloc_host(sizeof(struct au1xmmc_host), &pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) if (!mmc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) dev_err(&pdev->dev, "no memory for mmc_host\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) goto out0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) host = mmc_priv(mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) host->mmc = mmc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) host->platdata = pdev->dev.platform_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) host->pdev = pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) ret = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) if (!r) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) dev_err(&pdev->dev, "no mmio defined\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) goto out1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) host->ioarea = request_mem_region(r->start, resource_size(r),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) pdev->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) if (!host->ioarea) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) dev_err(&pdev->dev, "mmio already in use\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) goto out1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) host->iobase = ioremap(r->start, 0x3c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) if (!host->iobase) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) dev_err(&pdev->dev, "cannot remap mmio\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) goto out2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) host->irq = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) if (host->irq < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) goto out3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) mmc->ops = &au1xmmc_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) mmc->f_min = 450000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) mmc->f_max = 24000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) mmc->max_blk_size = 2048;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) mmc->max_blk_count = 512;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) mmc->ocr_avail = AU1XMMC_OCR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) mmc->caps = MMC_CAP_4_BIT_DATA | MMC_CAP_SDIO_IRQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) mmc->max_segs = AU1XMMC_DESCRIPTOR_COUNT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) iflag = IRQF_SHARED; /* Au1100/Au1200: one int for both ctrls */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) switch (alchemy_get_cputype()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) case ALCHEMY_CPU_AU1100:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) mmc->max_seg_size = AU1100_MMC_DESCRIPTOR_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) case ALCHEMY_CPU_AU1200:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) mmc->max_seg_size = AU1200_MMC_DESCRIPTOR_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) case ALCHEMY_CPU_AU1300:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) iflag = 0; /* nothing is shared */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) mmc->max_seg_size = AU1200_MMC_DESCRIPTOR_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) mmc->f_max = 52000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) if (host->ioarea->start == AU1100_SD0_PHYS_ADDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) mmc->caps |= MMC_CAP_8_BIT_DATA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) ret = request_irq(host->irq, au1xmmc_irq, iflag, DRIVER_NAME, host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) dev_err(&pdev->dev, "cannot grab IRQ\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) goto out3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) host->clk = clk_get(&pdev->dev, ALCHEMY_PERIPH_CLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) if (IS_ERR(host->clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) dev_err(&pdev->dev, "cannot find clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) ret = PTR_ERR(host->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) goto out_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) ret = clk_prepare_enable(host->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) dev_err(&pdev->dev, "cannot enable clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) goto out_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) host->status = HOST_S_IDLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) /* board-specific carddetect setup, if any */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) if (host->platdata && host->platdata->cd_setup) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) ret = host->platdata->cd_setup(mmc, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) dev_warn(&pdev->dev, "board CD setup failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) mmc->caps |= MMC_CAP_NEEDS_POLL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) mmc->caps |= MMC_CAP_NEEDS_POLL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) /* platform may not be able to use all advertised caps */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) if (host->platdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) mmc->caps &= ~(host->platdata->mask_host_caps);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) tasklet_init(&host->data_task, au1xmmc_tasklet_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) (unsigned long)host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) tasklet_init(&host->finish_task, au1xmmc_tasklet_finish,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) (unsigned long)host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) if (has_dbdma()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) ret = au1xmmc_dbdma_init(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) pr_info(DRIVER_NAME ": DBDMA init failed; using PIO\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) #ifdef CONFIG_LEDS_CLASS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) if (host->platdata && host->platdata->led) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) struct led_classdev *led = host->platdata->led;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) led->name = mmc_hostname(mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) led->brightness = LED_OFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) led->default_trigger = mmc_hostname(mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) ret = led_classdev_register(mmc_dev(mmc), led);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) goto out5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) au1xmmc_reset_controller(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) ret = mmc_add_host(mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) dev_err(&pdev->dev, "cannot add mmc host\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) goto out6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) platform_set_drvdata(pdev, host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) pr_info(DRIVER_NAME ": MMC Controller %d set up at %p"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) " (mode=%s)\n", pdev->id, host->iobase,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) host->flags & HOST_F_DMA ? "dma" : "pio");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) return 0; /* all ok */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) out6:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) #ifdef CONFIG_LEDS_CLASS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) if (host->platdata && host->platdata->led)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) led_classdev_unregister(host->platdata->led);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) out5:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) __raw_writel(0, HOST_ENABLE(host));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) __raw_writel(0, HOST_CONFIG(host));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) __raw_writel(0, HOST_CONFIG2(host));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) wmb(); /* drain writebuffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) if (host->flags & HOST_F_DBDMA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) au1xmmc_dbdma_shutdown(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) tasklet_kill(&host->data_task);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) tasklet_kill(&host->finish_task);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) if (host->platdata && host->platdata->cd_setup &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) !(mmc->caps & MMC_CAP_NEEDS_POLL))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) host->platdata->cd_setup(mmc, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) out_clk:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) clk_disable_unprepare(host->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) clk_put(host->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) out_irq:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) free_irq(host->irq, host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) out3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) iounmap((void *)host->iobase);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) out2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) release_resource(host->ioarea);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) kfree(host->ioarea);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) out1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) mmc_free_host(mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) out0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) static int au1xmmc_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) struct au1xmmc_host *host = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) if (host) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) mmc_remove_host(host->mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) #ifdef CONFIG_LEDS_CLASS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) if (host->platdata && host->platdata->led)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) led_classdev_unregister(host->platdata->led);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) if (host->platdata && host->platdata->cd_setup &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) !(host->mmc->caps & MMC_CAP_NEEDS_POLL))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) host->platdata->cd_setup(host->mmc, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) __raw_writel(0, HOST_ENABLE(host));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) __raw_writel(0, HOST_CONFIG(host));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) __raw_writel(0, HOST_CONFIG2(host));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) wmb(); /* drain writebuffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) tasklet_kill(&host->data_task);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) tasklet_kill(&host->finish_task);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) if (host->flags & HOST_F_DBDMA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) au1xmmc_dbdma_shutdown(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) au1xmmc_set_power(host, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) clk_disable_unprepare(host->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) clk_put(host->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) free_irq(host->irq, host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) iounmap((void *)host->iobase);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) release_resource(host->ioarea);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) kfree(host->ioarea);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) mmc_free_host(host->mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) #ifdef CONFIG_PM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) static int au1xmmc_suspend(struct platform_device *pdev, pm_message_t state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) struct au1xmmc_host *host = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) __raw_writel(0, HOST_CONFIG2(host));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) __raw_writel(0, HOST_CONFIG(host));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) __raw_writel(0xffffffff, HOST_STATUS(host));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) __raw_writel(0, HOST_ENABLE(host));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) wmb(); /* drain writebuffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) static int au1xmmc_resume(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) struct au1xmmc_host *host = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) au1xmmc_reset_controller(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) #define au1xmmc_suspend NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) #define au1xmmc_resume NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) static struct platform_driver au1xmmc_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) .probe = au1xmmc_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) .remove = au1xmmc_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) .suspend = au1xmmc_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) .resume = au1xmmc_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) .name = DRIVER_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) .probe_type = PROBE_PREFER_ASYNCHRONOUS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) static int __init au1xmmc_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) if (has_dbdma()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) /* DSCR_CMD0_ALWAYS has a stride of 32 bits, we need a stride
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) * of 8 bits. And since devices are shared, we need to create
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) * our own to avoid freaking out other devices.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) memid = au1xxx_ddma_add_device(&au1xmmc_mem_dbdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) if (!memid)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) pr_err("au1xmmc: cannot add memory dbdma\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) return platform_driver_register(&au1xmmc_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) static void __exit au1xmmc_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) if (has_dbdma() && memid)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) au1xxx_ddma_del_device(memid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) platform_driver_unregister(&au1xmmc_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) module_init(au1xmmc_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) module_exit(au1xmmc_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) MODULE_AUTHOR("Advanced Micro Devices, Inc");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) MODULE_DESCRIPTION("MMC/SD driver for the Alchemy Au1XXX");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) MODULE_ALIAS("platform:au1xxx-mmc");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags