^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright 2007, Google Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright 2012, Intel Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * based on omap.c driver, which was
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Copyright (C) 2004 Nokia Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Written by Tuukka Tikkanen and Juha Yrjölä <juha.yrjola@nokia.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Misc hacks here and there by Tony Lindgren <tony@atomide.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * Other hacks (DMA, SD, etc) by David Brownell
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/major.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/fs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/errno.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/hdreg.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/kdev_t.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/blkdev.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <linux/mutex.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <linux/scatterlist.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <linux/mmc/mmc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <linux/mmc/host.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include <linux/mmc/card.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #include <linux/moduleparam.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #include <linux/ioport.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #include <linux/dma-mapping.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #include <linux/spinlock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #include <linux/timer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #include <asm/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #include <asm/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #include <asm/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #include <linux/uaccess.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define DRIVER_NAME "goldfish_mmc"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define BUFFER_SIZE 16384
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define GOLDFISH_MMC_READ(host, addr) (readl(host->reg_base + addr))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define GOLDFISH_MMC_WRITE(host, addr, x) (writel(x, host->reg_base + addr))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) /* status register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) MMC_INT_STATUS = 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) /* set this to enable IRQ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) MMC_INT_ENABLE = 0x04,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) /* set this to specify buffer address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) MMC_SET_BUFFER = 0x08,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) /* MMC command number */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) MMC_CMD = 0x0C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) /* MMC argument */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) MMC_ARG = 0x10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) /* MMC response (or R2 bits 0 - 31) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) MMC_RESP_0 = 0x14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) /* MMC R2 response bits 32 - 63 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) MMC_RESP_1 = 0x18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) /* MMC R2 response bits 64 - 95 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) MMC_RESP_2 = 0x1C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) /* MMC R2 response bits 96 - 127 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) MMC_RESP_3 = 0x20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) MMC_BLOCK_LENGTH = 0x24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) MMC_BLOCK_COUNT = 0x28,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) /* MMC state flags */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) MMC_STATE = 0x2C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) /* MMC_INT_STATUS bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) MMC_STAT_END_OF_CMD = 1U << 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) MMC_STAT_END_OF_DATA = 1U << 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) MMC_STAT_STATE_CHANGE = 1U << 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) MMC_STAT_CMD_TIMEOUT = 1U << 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) /* MMC_STATE bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) MMC_STATE_INSERTED = 1U << 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) MMC_STATE_READ_ONLY = 1U << 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) * Command types
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define OMAP_MMC_CMDTYPE_BC 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define OMAP_MMC_CMDTYPE_BCR 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define OMAP_MMC_CMDTYPE_AC 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define OMAP_MMC_CMDTYPE_ADTC 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) struct goldfish_mmc_host {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) struct mmc_request *mrq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) struct mmc_command *cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) struct mmc_data *data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) unsigned char id; /* 16xx chips have 2 MMC blocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) void *virt_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) unsigned int phys_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) unsigned char bus_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) unsigned char hw_bus_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) unsigned int sg_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) unsigned dma_done:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) unsigned dma_in_use:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) void __iomem *reg_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) static inline int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) goldfish_mmc_cover_is_open(struct goldfish_mmc_host *host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) static ssize_t
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) goldfish_mmc_show_cover_switch(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) struct device_attribute *attr, char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) struct goldfish_mmc_host *host = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) return sprintf(buf, "%s\n", goldfish_mmc_cover_is_open(host) ? "open" :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) "closed");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) static DEVICE_ATTR(cover_switch, S_IRUGO, goldfish_mmc_show_cover_switch, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) goldfish_mmc_start_command(struct goldfish_mmc_host *host, struct mmc_command *cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) u32 cmdreg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) u32 resptype;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) u32 cmdtype;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) host->cmd = cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) resptype = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) cmdtype = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) /* Our hardware needs to know exact type */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) switch (mmc_resp_type(cmd)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) case MMC_RSP_NONE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) case MMC_RSP_R1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) case MMC_RSP_R1B:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) /* resp 1, 1b, 6, 7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) resptype = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) case MMC_RSP_R2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) resptype = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) case MMC_RSP_R3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) resptype = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) dev_err(mmc_dev(mmc_from_priv(host)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) "Invalid response type: %04x\n", mmc_resp_type(cmd));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) if (mmc_cmd_type(cmd) == MMC_CMD_ADTC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) cmdtype = OMAP_MMC_CMDTYPE_ADTC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) else if (mmc_cmd_type(cmd) == MMC_CMD_BC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) cmdtype = OMAP_MMC_CMDTYPE_BC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) else if (mmc_cmd_type(cmd) == MMC_CMD_BCR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) cmdtype = OMAP_MMC_CMDTYPE_BCR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) cmdtype = OMAP_MMC_CMDTYPE_AC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) cmdreg = cmd->opcode | (resptype << 8) | (cmdtype << 12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) if (host->bus_mode == MMC_BUSMODE_OPENDRAIN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) cmdreg |= 1 << 6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) if (cmd->flags & MMC_RSP_BUSY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) cmdreg |= 1 << 11;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) if (host->data && !(host->data->flags & MMC_DATA_WRITE))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) cmdreg |= 1 << 15;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) GOLDFISH_MMC_WRITE(host, MMC_ARG, cmd->arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) GOLDFISH_MMC_WRITE(host, MMC_CMD, cmdreg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) static void goldfish_mmc_xfer_done(struct goldfish_mmc_host *host,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) struct mmc_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) if (host->dma_in_use) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) enum dma_data_direction dma_data_dir;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) dma_data_dir = mmc_get_dma_dir(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) if (dma_data_dir == DMA_FROM_DEVICE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) * We don't really have DMA, so we need
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) * to copy from our platform driver buffer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) sg_copy_from_buffer(data->sg, 1, host->virt_base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) data->sg->length);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) host->data->bytes_xfered += data->sg->length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) dma_unmap_sg(mmc_dev(mmc_from_priv(host)), data->sg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) host->sg_len, dma_data_dir);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) host->data = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) host->sg_len = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) * NOTE: MMC layer will sometimes poll-wait CMD13 next, issuing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) * dozens of requests until the card finishes writing data.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) * It'd be cheaper to just wait till an EOFB interrupt arrives...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) if (!data->stop) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) host->mrq = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) mmc_request_done(mmc_from_priv(host), data->mrq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) goldfish_mmc_start_command(host, data->stop);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) static void goldfish_mmc_end_of_data(struct goldfish_mmc_host *host,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) struct mmc_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) if (!host->dma_in_use) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) goldfish_mmc_xfer_done(host, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) if (host->dma_done)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) goldfish_mmc_xfer_done(host, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) static void goldfish_mmc_cmd_done(struct goldfish_mmc_host *host,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) struct mmc_command *cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) host->cmd = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) if (cmd->flags & MMC_RSP_PRESENT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) if (cmd->flags & MMC_RSP_136) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) /* response type 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) cmd->resp[3] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) GOLDFISH_MMC_READ(host, MMC_RESP_0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) cmd->resp[2] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) GOLDFISH_MMC_READ(host, MMC_RESP_1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) cmd->resp[1] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) GOLDFISH_MMC_READ(host, MMC_RESP_2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) cmd->resp[0] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) GOLDFISH_MMC_READ(host, MMC_RESP_3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) /* response types 1, 1b, 3, 4, 5, 6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) cmd->resp[0] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) GOLDFISH_MMC_READ(host, MMC_RESP_0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) if (host->data == NULL || cmd->error) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) host->mrq = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) mmc_request_done(mmc_from_priv(host), cmd->mrq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) static irqreturn_t goldfish_mmc_irq(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) struct goldfish_mmc_host *host = (struct goldfish_mmc_host *)dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) u16 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) int end_command = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) int end_transfer = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) int state_changed = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) int cmd_timeout = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) while ((status = GOLDFISH_MMC_READ(host, MMC_INT_STATUS)) != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) GOLDFISH_MMC_WRITE(host, MMC_INT_STATUS, status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) if (status & MMC_STAT_END_OF_CMD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) end_command = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) if (status & MMC_STAT_END_OF_DATA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) end_transfer = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) if (status & MMC_STAT_STATE_CHANGE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) state_changed = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) if (status & MMC_STAT_CMD_TIMEOUT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) end_command = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) cmd_timeout = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) if (cmd_timeout) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) struct mmc_request *mrq = host->mrq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) mrq->cmd->error = -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) host->mrq = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) mmc_request_done(mmc_from_priv(host), mrq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) if (end_command)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) goldfish_mmc_cmd_done(host, host->cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) if (end_transfer) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) host->dma_done = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) goldfish_mmc_end_of_data(host, host->data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) } else if (host->data != NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) * WORKAROUND -- after porting this driver from 2.6 to 3.4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) * during device initialization, cases where host->data is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) * non-null but end_transfer is false would occur. Doing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) * nothing in such cases results in no further interrupts,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) * and initialization failure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) * TODO -- find the real cause.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) host->dma_done = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) goldfish_mmc_end_of_data(host, host->data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) if (state_changed) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) u32 state = GOLDFISH_MMC_READ(host, MMC_STATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) pr_info("%s: Card detect now %d\n", __func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) (state & MMC_STATE_INSERTED));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) mmc_detect_change(mmc_from_priv(host), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) if (!end_command && !end_transfer && !state_changed && !cmd_timeout) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) status = GOLDFISH_MMC_READ(host, MMC_INT_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) dev_info(mmc_dev(mmc_from_priv(host)), "spurious irq 0x%04x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) if (status != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) GOLDFISH_MMC_WRITE(host, MMC_INT_STATUS, status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) GOLDFISH_MMC_WRITE(host, MMC_INT_ENABLE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) static void goldfish_mmc_prepare_data(struct goldfish_mmc_host *host,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) struct mmc_request *req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) struct mmc_data *data = req->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) int block_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) unsigned sg_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) enum dma_data_direction dma_data_dir;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) host->data = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) if (data == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) GOLDFISH_MMC_WRITE(host, MMC_BLOCK_LENGTH, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) GOLDFISH_MMC_WRITE(host, MMC_BLOCK_COUNT, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) host->dma_in_use = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) block_size = data->blksz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) GOLDFISH_MMC_WRITE(host, MMC_BLOCK_COUNT, data->blocks - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) GOLDFISH_MMC_WRITE(host, MMC_BLOCK_LENGTH, block_size - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) * Cope with calling layer confusion; it issues "single
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) * block" writes using multi-block scatterlists.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) sg_len = (data->blocks == 1) ? 1 : data->sg_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) dma_data_dir = mmc_get_dma_dir(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) host->sg_len = dma_map_sg(mmc_dev(mmc_from_priv(host)), data->sg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) sg_len, dma_data_dir);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) host->dma_done = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) host->dma_in_use = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) if (dma_data_dir == DMA_TO_DEVICE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) * We don't really have DMA, so we need to copy to our
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) * platform driver buffer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) sg_copy_to_buffer(data->sg, 1, host->virt_base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) data->sg->length);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) static void goldfish_mmc_request(struct mmc_host *mmc, struct mmc_request *req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) struct goldfish_mmc_host *host = mmc_priv(mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) WARN_ON(host->mrq != NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) host->mrq = req;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) goldfish_mmc_prepare_data(host, req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) goldfish_mmc_start_command(host, req->cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) static void goldfish_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) struct goldfish_mmc_host *host = mmc_priv(mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) host->bus_mode = ios->bus_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) host->hw_bus_mode = host->bus_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) static int goldfish_mmc_get_ro(struct mmc_host *mmc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) uint32_t state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) struct goldfish_mmc_host *host = mmc_priv(mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) state = GOLDFISH_MMC_READ(host, MMC_STATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) return ((state & MMC_STATE_READ_ONLY) != 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) static const struct mmc_host_ops goldfish_mmc_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) .request = goldfish_mmc_request,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) .set_ios = goldfish_mmc_set_ios,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) .get_ro = goldfish_mmc_get_ro,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) static int goldfish_mmc_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) struct mmc_host *mmc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) struct goldfish_mmc_host *host = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) dma_addr_t buf_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) irq = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) if (res == NULL || irq < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) return -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) mmc = mmc_alloc_host(sizeof(struct goldfish_mmc_host), &pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) if (mmc == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) goto err_alloc_host_failed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) host = mmc_priv(mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) pr_err("mmc: Mapping %lX to %lX\n", (long)res->start, (long)res->end);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) host->reg_base = ioremap(res->start, resource_size(res));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) if (host->reg_base == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) goto ioremap_failed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) host->virt_base = dma_alloc_coherent(&pdev->dev, BUFFER_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) &buf_addr, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) if (host->virt_base == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) goto dma_alloc_failed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) host->phys_base = buf_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) host->id = pdev->id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) host->irq = irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) mmc->ops = &goldfish_mmc_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) mmc->f_min = 400000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) mmc->f_max = 24000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) mmc->caps = MMC_CAP_4_BIT_DATA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) mmc->caps2 = MMC_CAP2_NO_SDIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) /* Use scatterlist DMA to reduce per-transfer costs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) * NOTE max_seg_size assumption that small blocks aren't
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) * normally used (except e.g. for reading SD registers).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) mmc->max_segs = 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) mmc->max_blk_size = 2048; /* MMC_BLOCK_LENGTH is 11 bits (+1) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) mmc->max_blk_count = 2048; /* MMC_BLOCK_COUNT is 11 bits (+1) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) mmc->max_req_size = BUFFER_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) mmc->max_seg_size = mmc->max_req_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) ret = request_irq(host->irq, goldfish_mmc_irq, 0, DRIVER_NAME, host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) dev_err(&pdev->dev, "Failed IRQ Adding goldfish MMC\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) goto err_request_irq_failed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) host->dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) platform_set_drvdata(pdev, host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) ret = device_create_file(&pdev->dev, &dev_attr_cover_switch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) dev_warn(mmc_dev(mmc), "Unable to create sysfs attributes\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) GOLDFISH_MMC_WRITE(host, MMC_SET_BUFFER, host->phys_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) GOLDFISH_MMC_WRITE(host, MMC_INT_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) MMC_STAT_END_OF_CMD | MMC_STAT_END_OF_DATA |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) MMC_STAT_STATE_CHANGE | MMC_STAT_CMD_TIMEOUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) mmc_add_host(mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) err_request_irq_failed:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) dma_free_coherent(&pdev->dev, BUFFER_SIZE, host->virt_base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) host->phys_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) dma_alloc_failed:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) iounmap(host->reg_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) ioremap_failed:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) mmc_free_host(mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) err_alloc_host_failed:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) static int goldfish_mmc_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) struct goldfish_mmc_host *host = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) struct mmc_host *mmc = mmc_from_priv(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) BUG_ON(host == NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) mmc_remove_host(mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) free_irq(host->irq, host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) dma_free_coherent(&pdev->dev, BUFFER_SIZE, host->virt_base, host->phys_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) iounmap(host->reg_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) mmc_free_host(mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) static struct platform_driver goldfish_mmc_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) .probe = goldfish_mmc_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) .remove = goldfish_mmc_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) .name = DRIVER_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) .probe_type = PROBE_PREFER_ASYNCHRONOUS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) module_platform_driver(goldfish_mmc_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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