^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Xilinx SDFEC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2019 Xilinx, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Description:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * This driver is developed for SDFEC16 (Soft Decision FEC 16nm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * IP. It exposes a char device which supports file operations
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * like open(), close() and ioctl().
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/miscdevice.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/of_platform.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/poll.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/compat.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/highmem.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <uapi/misc/xilinx_sdfec.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define DEV_NAME_LEN 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) static DEFINE_IDA(dev_nrs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) /* Xilinx SDFEC Register Map */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) /* CODE_WRI_PROTECT Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define XSDFEC_CODE_WR_PROTECT_ADDR (0x4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) /* ACTIVE Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define XSDFEC_ACTIVE_ADDR (0x8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define XSDFEC_IS_ACTIVITY_SET (0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) /* AXIS_WIDTH Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define XSDFEC_AXIS_WIDTH_ADDR (0xC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define XSDFEC_AXIS_DOUT_WORDS_LSB (5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define XSDFEC_AXIS_DOUT_WIDTH_LSB (3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define XSDFEC_AXIS_DIN_WORDS_LSB (2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define XSDFEC_AXIS_DIN_WIDTH_LSB (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) /* AXIS_ENABLE Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define XSDFEC_AXIS_ENABLE_ADDR (0x10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define XSDFEC_AXIS_OUT_ENABLE_MASK (0x38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define XSDFEC_AXIS_IN_ENABLE_MASK (0x7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define XSDFEC_AXIS_ENABLE_MASK \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) (XSDFEC_AXIS_OUT_ENABLE_MASK | XSDFEC_AXIS_IN_ENABLE_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) /* FEC_CODE Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define XSDFEC_FEC_CODE_ADDR (0x14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) /* ORDER Register Map */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define XSDFEC_ORDER_ADDR (0x18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) /* Interrupt Status Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define XSDFEC_ISR_ADDR (0x1C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) /* Interrupt Status Register Bit Mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define XSDFEC_ISR_MASK (0x3F)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) /* Write Only - Interrupt Enable Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define XSDFEC_IER_ADDR (0x20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) /* Write Only - Interrupt Disable Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define XSDFEC_IDR_ADDR (0x24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) /* Read Only - Interrupt Mask Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define XSDFEC_IMR_ADDR (0x28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) /* ECC Interrupt Status Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define XSDFEC_ECC_ISR_ADDR (0x2C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) /* Single Bit Errors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define XSDFEC_ECC_ISR_SBE_MASK (0x7FF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) /* PL Initialize Single Bit Errors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define XSDFEC_PL_INIT_ECC_ISR_SBE_MASK (0x3C00000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) /* Multi Bit Errors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define XSDFEC_ECC_ISR_MBE_MASK (0x3FF800)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) /* PL Initialize Multi Bit Errors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define XSDFEC_PL_INIT_ECC_ISR_MBE_MASK (0x3C000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) /* Multi Bit Error to Event Shift */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define XSDFEC_ECC_ISR_MBE_TO_EVENT_SHIFT (11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) /* PL Initialize Multi Bit Error to Event Shift */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define XSDFEC_PL_INIT_ECC_ISR_MBE_TO_EVENT_SHIFT (4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) /* ECC Interrupt Status Bit Mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define XSDFEC_ECC_ISR_MASK (XSDFEC_ECC_ISR_SBE_MASK | XSDFEC_ECC_ISR_MBE_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) /* ECC Interrupt Status PL Initialize Bit Mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define XSDFEC_PL_INIT_ECC_ISR_MASK \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) (XSDFEC_PL_INIT_ECC_ISR_SBE_MASK | XSDFEC_PL_INIT_ECC_ISR_MBE_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) /* ECC Interrupt Status All Bit Mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define XSDFEC_ALL_ECC_ISR_MASK \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) (XSDFEC_ECC_ISR_MASK | XSDFEC_PL_INIT_ECC_ISR_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) /* ECC Interrupt Status Single Bit Errors Mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define XSDFEC_ALL_ECC_ISR_SBE_MASK \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) (XSDFEC_ECC_ISR_SBE_MASK | XSDFEC_PL_INIT_ECC_ISR_SBE_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) /* ECC Interrupt Status Multi Bit Errors Mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define XSDFEC_ALL_ECC_ISR_MBE_MASK \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) (XSDFEC_ECC_ISR_MBE_MASK | XSDFEC_PL_INIT_ECC_ISR_MBE_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) /* Write Only - ECC Interrupt Enable Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define XSDFEC_ECC_IER_ADDR (0x30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) /* Write Only - ECC Interrupt Disable Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define XSDFEC_ECC_IDR_ADDR (0x34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) /* Read Only - ECC Interrupt Mask Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define XSDFEC_ECC_IMR_ADDR (0x38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) /* BYPASS Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define XSDFEC_BYPASS_ADDR (0x3C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) /* Turbo Code Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define XSDFEC_TURBO_ADDR (0x100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define XSDFEC_TURBO_SCALE_MASK (0xFFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define XSDFEC_TURBO_SCALE_BIT_POS (8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define XSDFEC_TURBO_SCALE_MAX (15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) /* REG0 Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define XSDFEC_LDPC_CODE_REG0_ADDR_BASE (0x2000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define XSDFEC_LDPC_CODE_REG0_ADDR_HIGH (0x27F0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define XSDFEC_REG0_N_MIN (4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define XSDFEC_REG0_N_MAX (32768)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define XSDFEC_REG0_N_MUL_P (256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define XSDFEC_REG0_N_LSB (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define XSDFEC_REG0_K_MIN (2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define XSDFEC_REG0_K_MAX (32766)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define XSDFEC_REG0_K_MUL_P (256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define XSDFEC_REG0_K_LSB (16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) /* REG1 Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define XSDFEC_LDPC_CODE_REG1_ADDR_BASE (0x2004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define XSDFEC_LDPC_CODE_REG1_ADDR_HIGH (0x27f4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define XSDFEC_REG1_PSIZE_MIN (2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define XSDFEC_REG1_PSIZE_MAX (512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define XSDFEC_REG1_NO_PACKING_MASK (0x400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define XSDFEC_REG1_NO_PACKING_LSB (10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define XSDFEC_REG1_NM_MASK (0xFF800)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define XSDFEC_REG1_NM_LSB (11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define XSDFEC_REG1_BYPASS_MASK (0x100000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) /* REG2 Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define XSDFEC_LDPC_CODE_REG2_ADDR_BASE (0x2008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define XSDFEC_LDPC_CODE_REG2_ADDR_HIGH (0x27f8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define XSDFEC_REG2_NLAYERS_MIN (1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define XSDFEC_REG2_NLAYERS_MAX (256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define XSDFEC_REG2_NNMQC_MASK (0xFFE00)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define XSDFEC_REG2_NMQC_LSB (9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define XSDFEC_REG2_NORM_TYPE_MASK (0x100000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define XSDFEC_REG2_NORM_TYPE_LSB (20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define XSDFEC_REG2_SPECIAL_QC_MASK (0x200000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define XSDFEC_REG2_SPEICAL_QC_LSB (21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define XSDFEC_REG2_NO_FINAL_PARITY_MASK (0x400000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define XSDFEC_REG2_NO_FINAL_PARITY_LSB (22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define XSDFEC_REG2_MAX_SCHEDULE_MASK (0x1800000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define XSDFEC_REG2_MAX_SCHEDULE_LSB (23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) /* REG3 Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define XSDFEC_LDPC_CODE_REG3_ADDR_BASE (0x200C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define XSDFEC_LDPC_CODE_REG3_ADDR_HIGH (0x27FC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define XSDFEC_REG3_LA_OFF_LSB (8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define XSDFEC_REG3_QC_OFF_LSB (16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define XSDFEC_LDPC_REG_JUMP (0x10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define XSDFEC_REG_WIDTH_JUMP (4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) /* The maximum number of pinned pages */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define MAX_NUM_PAGES ((XSDFEC_QC_TABLE_DEPTH / PAGE_SIZE) + 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) * struct xsdfec_clks - For managing SD-FEC clocks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) * @core_clk: Main processing clock for core
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) * @axi_clk: AXI4-Lite memory-mapped clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) * @din_words_clk: DIN Words AXI4-Stream Slave clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) * @din_clk: DIN AXI4-Stream Slave clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) * @dout_clk: DOUT Words AXI4-Stream Slave clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) * @dout_words_clk: DOUT AXI4-Stream Slave clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) * @ctrl_clk: Control AXI4-Stream Slave clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) * @status_clk: Status AXI4-Stream Slave clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) struct xsdfec_clks {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) struct clk *core_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) struct clk *axi_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) struct clk *din_words_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) struct clk *din_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) struct clk *dout_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) struct clk *dout_words_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) struct clk *ctrl_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) struct clk *status_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) * struct xsdfec_dev - Driver data for SDFEC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) * @miscdev: Misc device handle
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) * @clks: Clocks managed by the SDFEC driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) * @waitq: Driver wait queue
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) * @config: Configuration of the SDFEC device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) * @dev_name: Device name
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) * @flags: spinlock flags
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) * @regs: device physical base address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) * @dev: pointer to device struct
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) * @state: State of the SDFEC device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) * @error_data_lock: Error counter and states spinlock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) * @dev_id: Device ID
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) * @isr_err_count: Count of ISR errors
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) * @cecc_count: Count of Correctable ECC errors (SBE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) * @uecc_count: Count of Uncorrectable ECC errors (MBE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) * @irq: IRQ number
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) * @state_updated: indicates State updated by interrupt handler
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) * @stats_updated: indicates Stats updated by interrupt handler
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) * @intr_enabled: indicates IRQ enabled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) * This structure contains necessary state for SDFEC driver to operate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) struct xsdfec_dev {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) struct miscdevice miscdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) struct xsdfec_clks clks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) wait_queue_head_t waitq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) struct xsdfec_config config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) char dev_name[DEV_NAME_LEN];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) void __iomem *regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) enum xsdfec_state state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) /* Spinlock to protect state_updated and stats_updated */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) spinlock_t error_data_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) int dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) u32 isr_err_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) u32 cecc_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) u32 uecc_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) bool state_updated;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) bool stats_updated;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) bool intr_enabled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) static inline void xsdfec_regwrite(struct xsdfec_dev *xsdfec, u32 addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) u32 value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) dev_dbg(xsdfec->dev, "Writing 0x%x to offset 0x%x", value, addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) iowrite32(value, xsdfec->regs + addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) static inline u32 xsdfec_regread(struct xsdfec_dev *xsdfec, u32 addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) u32 rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) rval = ioread32(xsdfec->regs + addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) dev_dbg(xsdfec->dev, "Read value = 0x%x from offset 0x%x", rval, addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) return rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) static void update_bool_config_from_reg(struct xsdfec_dev *xsdfec,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) u32 reg_offset, u32 bit_num,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) char *config_value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) u32 reg_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) u32 bit_mask = 1 << bit_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) reg_val = xsdfec_regread(xsdfec, reg_offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) *config_value = (reg_val & bit_mask) > 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) static void update_config_from_hw(struct xsdfec_dev *xsdfec)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) u32 reg_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) bool sdfec_started;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) /* Update the Order */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) reg_value = xsdfec_regread(xsdfec, XSDFEC_ORDER_ADDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) xsdfec->config.order = reg_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) update_bool_config_from_reg(xsdfec, XSDFEC_BYPASS_ADDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 0, /* Bit Number, maybe change to mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) &xsdfec->config.bypass);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) update_bool_config_from_reg(xsdfec, XSDFEC_CODE_WR_PROTECT_ADDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 0, /* Bit Number */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) &xsdfec->config.code_wr_protect);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) reg_value = xsdfec_regread(xsdfec, XSDFEC_IMR_ADDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) xsdfec->config.irq.enable_isr = (reg_value & XSDFEC_ISR_MASK) > 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) reg_value = xsdfec_regread(xsdfec, XSDFEC_ECC_IMR_ADDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) xsdfec->config.irq.enable_ecc_isr =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) (reg_value & XSDFEC_ECC_ISR_MASK) > 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) reg_value = xsdfec_regread(xsdfec, XSDFEC_AXIS_ENABLE_ADDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) sdfec_started = (reg_value & XSDFEC_AXIS_IN_ENABLE_MASK) > 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) if (sdfec_started)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) xsdfec->state = XSDFEC_STARTED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) xsdfec->state = XSDFEC_STOPPED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) static int xsdfec_get_status(struct xsdfec_dev *xsdfec, void __user *arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) struct xsdfec_status status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) memset(&status, 0, sizeof(status));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) spin_lock_irqsave(&xsdfec->error_data_lock, xsdfec->flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) status.state = xsdfec->state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) xsdfec->state_updated = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) spin_unlock_irqrestore(&xsdfec->error_data_lock, xsdfec->flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) status.activity = (xsdfec_regread(xsdfec, XSDFEC_ACTIVE_ADDR) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) XSDFEC_IS_ACTIVITY_SET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) err = copy_to_user(arg, &status, sizeof(status));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) err = -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) static int xsdfec_get_config(struct xsdfec_dev *xsdfec, void __user *arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) err = copy_to_user(arg, &xsdfec->config, sizeof(xsdfec->config));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) err = -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) static int xsdfec_isr_enable(struct xsdfec_dev *xsdfec, bool enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) u32 mask_read;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) if (enable) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) /* Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) xsdfec_regwrite(xsdfec, XSDFEC_IER_ADDR, XSDFEC_ISR_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) mask_read = xsdfec_regread(xsdfec, XSDFEC_IMR_ADDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) if (mask_read & XSDFEC_ISR_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) dev_dbg(xsdfec->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) "SDFEC enabling irq with IER failed");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) /* Disable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) xsdfec_regwrite(xsdfec, XSDFEC_IDR_ADDR, XSDFEC_ISR_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) mask_read = xsdfec_regread(xsdfec, XSDFEC_IMR_ADDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) if ((mask_read & XSDFEC_ISR_MASK) != XSDFEC_ISR_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) dev_dbg(xsdfec->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) "SDFEC disabling irq with IDR failed");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) static int xsdfec_ecc_isr_enable(struct xsdfec_dev *xsdfec, bool enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) u32 mask_read;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) if (enable) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) /* Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) xsdfec_regwrite(xsdfec, XSDFEC_ECC_IER_ADDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) XSDFEC_ALL_ECC_ISR_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) mask_read = xsdfec_regread(xsdfec, XSDFEC_ECC_IMR_ADDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) if (mask_read & XSDFEC_ALL_ECC_ISR_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) dev_dbg(xsdfec->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) "SDFEC enabling ECC irq with ECC IER failed");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) /* Disable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) xsdfec_regwrite(xsdfec, XSDFEC_ECC_IDR_ADDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) XSDFEC_ALL_ECC_ISR_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) mask_read = xsdfec_regread(xsdfec, XSDFEC_ECC_IMR_ADDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) if (!(((mask_read & XSDFEC_ALL_ECC_ISR_MASK) ==
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) XSDFEC_ECC_ISR_MASK) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) ((mask_read & XSDFEC_ALL_ECC_ISR_MASK) ==
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) XSDFEC_PL_INIT_ECC_ISR_MASK))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) dev_dbg(xsdfec->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) "SDFEC disable ECC irq with ECC IDR failed");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) static int xsdfec_set_irq(struct xsdfec_dev *xsdfec, void __user *arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) struct xsdfec_irq irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) int isr_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) int ecc_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) err = copy_from_user(&irq, arg, sizeof(irq));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) return -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) /* Setup tlast related IRQ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) isr_err = xsdfec_isr_enable(xsdfec, irq.enable_isr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) if (!isr_err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) xsdfec->config.irq.enable_isr = irq.enable_isr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) /* Setup ECC related IRQ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) ecc_err = xsdfec_ecc_isr_enable(xsdfec, irq.enable_ecc_isr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) if (!ecc_err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) xsdfec->config.irq.enable_ecc_isr = irq.enable_ecc_isr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) if (isr_err < 0 || ecc_err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) err = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) static int xsdfec_set_turbo(struct xsdfec_dev *xsdfec, void __user *arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) struct xsdfec_turbo turbo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) u32 turbo_write;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) err = copy_from_user(&turbo, arg, sizeof(turbo));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) return -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) if (turbo.alg >= XSDFEC_TURBO_ALG_MAX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) if (turbo.scale > XSDFEC_TURBO_SCALE_MAX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) /* Check to see what device tree says about the FEC codes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) if (xsdfec->config.code == XSDFEC_LDPC_CODE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) turbo_write = ((turbo.scale & XSDFEC_TURBO_SCALE_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) << XSDFEC_TURBO_SCALE_BIT_POS) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) turbo.alg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) xsdfec_regwrite(xsdfec, XSDFEC_TURBO_ADDR, turbo_write);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) static int xsdfec_get_turbo(struct xsdfec_dev *xsdfec, void __user *arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) u32 reg_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) struct xsdfec_turbo turbo_params;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) if (xsdfec->config.code == XSDFEC_LDPC_CODE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) memset(&turbo_params, 0, sizeof(turbo_params));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) reg_value = xsdfec_regread(xsdfec, XSDFEC_TURBO_ADDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) turbo_params.scale = (reg_value & XSDFEC_TURBO_SCALE_MASK) >>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) XSDFEC_TURBO_SCALE_BIT_POS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) turbo_params.alg = reg_value & 0x1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) err = copy_to_user(arg, &turbo_params, sizeof(turbo_params));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) err = -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) static int xsdfec_reg0_write(struct xsdfec_dev *xsdfec, u32 n, u32 k, u32 psize,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) u32 offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) u32 wdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) if (n < XSDFEC_REG0_N_MIN || n > XSDFEC_REG0_N_MAX || psize == 0 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) (n > XSDFEC_REG0_N_MUL_P * psize) || n <= k || ((n % psize) != 0)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) dev_dbg(xsdfec->dev, "N value is not in range");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) n <<= XSDFEC_REG0_N_LSB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) if (k < XSDFEC_REG0_K_MIN || k > XSDFEC_REG0_K_MAX ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) (k > XSDFEC_REG0_K_MUL_P * psize) || ((k % psize) != 0)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) dev_dbg(xsdfec->dev, "K value is not in range");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) k = k << XSDFEC_REG0_K_LSB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) wdata = k | n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) if (XSDFEC_LDPC_CODE_REG0_ADDR_BASE + (offset * XSDFEC_LDPC_REG_JUMP) >
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) XSDFEC_LDPC_CODE_REG0_ADDR_HIGH) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) dev_dbg(xsdfec->dev, "Writing outside of LDPC reg0 space 0x%x",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) XSDFEC_LDPC_CODE_REG0_ADDR_BASE +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) (offset * XSDFEC_LDPC_REG_JUMP));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) xsdfec_regwrite(xsdfec,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) XSDFEC_LDPC_CODE_REG0_ADDR_BASE +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) (offset * XSDFEC_LDPC_REG_JUMP),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) wdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) static int xsdfec_reg1_write(struct xsdfec_dev *xsdfec, u32 psize,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) u32 no_packing, u32 nm, u32 offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) u32 wdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) if (psize < XSDFEC_REG1_PSIZE_MIN || psize > XSDFEC_REG1_PSIZE_MAX) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) dev_dbg(xsdfec->dev, "Psize is not in range");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) if (no_packing != 0 && no_packing != 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) dev_dbg(xsdfec->dev, "No-packing bit register invalid");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) no_packing = ((no_packing << XSDFEC_REG1_NO_PACKING_LSB) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) XSDFEC_REG1_NO_PACKING_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) if (nm & ~(XSDFEC_REG1_NM_MASK >> XSDFEC_REG1_NM_LSB))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) dev_dbg(xsdfec->dev, "NM is beyond 10 bits");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) nm = (nm << XSDFEC_REG1_NM_LSB) & XSDFEC_REG1_NM_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) wdata = nm | no_packing | psize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) if (XSDFEC_LDPC_CODE_REG1_ADDR_BASE + (offset * XSDFEC_LDPC_REG_JUMP) >
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) XSDFEC_LDPC_CODE_REG1_ADDR_HIGH) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) dev_dbg(xsdfec->dev, "Writing outside of LDPC reg1 space 0x%x",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) XSDFEC_LDPC_CODE_REG1_ADDR_BASE +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) (offset * XSDFEC_LDPC_REG_JUMP));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) xsdfec_regwrite(xsdfec,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) XSDFEC_LDPC_CODE_REG1_ADDR_BASE +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) (offset * XSDFEC_LDPC_REG_JUMP),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) wdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) static int xsdfec_reg2_write(struct xsdfec_dev *xsdfec, u32 nlayers, u32 nmqc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) u32 norm_type, u32 special_qc, u32 no_final_parity,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) u32 max_schedule, u32 offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) u32 wdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) if (nlayers < XSDFEC_REG2_NLAYERS_MIN ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) nlayers > XSDFEC_REG2_NLAYERS_MAX) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) dev_dbg(xsdfec->dev, "Nlayers is not in range");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) if (nmqc & ~(XSDFEC_REG2_NNMQC_MASK >> XSDFEC_REG2_NMQC_LSB))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) dev_dbg(xsdfec->dev, "NMQC exceeds 11 bits");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) nmqc = (nmqc << XSDFEC_REG2_NMQC_LSB) & XSDFEC_REG2_NNMQC_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) if (norm_type > 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) dev_dbg(xsdfec->dev, "Norm type is invalid");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) norm_type = ((norm_type << XSDFEC_REG2_NORM_TYPE_LSB) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) XSDFEC_REG2_NORM_TYPE_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) if (special_qc > 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) dev_dbg(xsdfec->dev, "Special QC in invalid");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) special_qc = ((special_qc << XSDFEC_REG2_SPEICAL_QC_LSB) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) XSDFEC_REG2_SPECIAL_QC_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) if (no_final_parity > 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) dev_dbg(xsdfec->dev, "No final parity check invalid");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) no_final_parity =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) ((no_final_parity << XSDFEC_REG2_NO_FINAL_PARITY_LSB) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) XSDFEC_REG2_NO_FINAL_PARITY_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) if (max_schedule &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) ~(XSDFEC_REG2_MAX_SCHEDULE_MASK >> XSDFEC_REG2_MAX_SCHEDULE_LSB))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) dev_dbg(xsdfec->dev, "Max Schedule exceeds 2 bits");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) max_schedule = ((max_schedule << XSDFEC_REG2_MAX_SCHEDULE_LSB) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) XSDFEC_REG2_MAX_SCHEDULE_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) wdata = (max_schedule | no_final_parity | special_qc | norm_type |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) nmqc | nlayers);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) if (XSDFEC_LDPC_CODE_REG2_ADDR_BASE + (offset * XSDFEC_LDPC_REG_JUMP) >
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) XSDFEC_LDPC_CODE_REG2_ADDR_HIGH) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) dev_dbg(xsdfec->dev, "Writing outside of LDPC reg2 space 0x%x",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) XSDFEC_LDPC_CODE_REG2_ADDR_BASE +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) (offset * XSDFEC_LDPC_REG_JUMP));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) xsdfec_regwrite(xsdfec,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) XSDFEC_LDPC_CODE_REG2_ADDR_BASE +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) (offset * XSDFEC_LDPC_REG_JUMP),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) wdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) static int xsdfec_reg3_write(struct xsdfec_dev *xsdfec, u8 sc_off, u8 la_off,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) u16 qc_off, u32 offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) u32 wdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) wdata = ((qc_off << XSDFEC_REG3_QC_OFF_LSB) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) (la_off << XSDFEC_REG3_LA_OFF_LSB) | sc_off);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) if (XSDFEC_LDPC_CODE_REG3_ADDR_BASE + (offset * XSDFEC_LDPC_REG_JUMP) >
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) XSDFEC_LDPC_CODE_REG3_ADDR_HIGH) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) dev_dbg(xsdfec->dev, "Writing outside of LDPC reg3 space 0x%x",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) XSDFEC_LDPC_CODE_REG3_ADDR_BASE +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) (offset * XSDFEC_LDPC_REG_JUMP));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) xsdfec_regwrite(xsdfec,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) XSDFEC_LDPC_CODE_REG3_ADDR_BASE +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) (offset * XSDFEC_LDPC_REG_JUMP),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) wdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) static int xsdfec_table_write(struct xsdfec_dev *xsdfec, u32 offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) u32 *src_ptr, u32 len, const u32 base_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) const u32 depth)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) u32 reg = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) int res, i, nr_pages;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) u32 n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) u32 *addr = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) struct page *pages[MAX_NUM_PAGES];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) * Writes that go beyond the length of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) * Shared Scale(SC) table should fail
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) if (offset > depth / XSDFEC_REG_WIDTH_JUMP ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) len > depth / XSDFEC_REG_WIDTH_JUMP ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) offset + len > depth / XSDFEC_REG_WIDTH_JUMP) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) dev_dbg(xsdfec->dev, "Write exceeds SC table length");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) n = (len * XSDFEC_REG_WIDTH_JUMP) / PAGE_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) if ((len * XSDFEC_REG_WIDTH_JUMP) % PAGE_SIZE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) n += 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) if (WARN_ON_ONCE(n > INT_MAX))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) nr_pages = n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) res = pin_user_pages_fast((unsigned long)src_ptr, nr_pages, 0, pages);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) if (res < nr_pages) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) if (res > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) unpin_user_pages(pages, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) for (i = 0; i < nr_pages; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) addr = kmap(pages[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) xsdfec_regwrite(xsdfec,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) base_addr + ((offset + reg) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) XSDFEC_REG_WIDTH_JUMP),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) addr[reg]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) reg++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) } while ((reg < len) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) ((reg * XSDFEC_REG_WIDTH_JUMP) % PAGE_SIZE));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) unpin_user_page(pages[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) static int xsdfec_add_ldpc(struct xsdfec_dev *xsdfec, void __user *arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) struct xsdfec_ldpc_params *ldpc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) int ret, n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) ldpc = memdup_user(arg, sizeof(*ldpc));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) if (IS_ERR(ldpc))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) return PTR_ERR(ldpc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) if (xsdfec->config.code == XSDFEC_TURBO_CODE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) ret = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) goto err_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) /* Verify Device has not started */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) if (xsdfec->state == XSDFEC_STARTED) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) ret = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) goto err_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) if (xsdfec->config.code_wr_protect) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) ret = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) goto err_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) /* Write Reg 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) ret = xsdfec_reg0_write(xsdfec, ldpc->n, ldpc->k, ldpc->psize,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) ldpc->code_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) goto err_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) /* Write Reg 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) ret = xsdfec_reg1_write(xsdfec, ldpc->psize, ldpc->no_packing, ldpc->nm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) ldpc->code_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) goto err_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) /* Write Reg 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) ret = xsdfec_reg2_write(xsdfec, ldpc->nlayers, ldpc->nmqc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) ldpc->norm_type, ldpc->special_qc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) ldpc->no_final_parity, ldpc->max_schedule,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) ldpc->code_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) goto err_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) /* Write Reg 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) ret = xsdfec_reg3_write(xsdfec, ldpc->sc_off, ldpc->la_off,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) ldpc->qc_off, ldpc->code_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) goto err_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) /* Write Shared Codes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) n = ldpc->nlayers / 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) if (ldpc->nlayers % 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) n++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) ret = xsdfec_table_write(xsdfec, ldpc->sc_off, ldpc->sc_table, n,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) XSDFEC_LDPC_SC_TABLE_ADDR_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) XSDFEC_SC_TABLE_DEPTH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) goto err_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) ret = xsdfec_table_write(xsdfec, 4 * ldpc->la_off, ldpc->la_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) ldpc->nlayers, XSDFEC_LDPC_LA_TABLE_ADDR_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) XSDFEC_LA_TABLE_DEPTH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) goto err_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) ret = xsdfec_table_write(xsdfec, 4 * ldpc->qc_off, ldpc->qc_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) ldpc->nqc, XSDFEC_LDPC_QC_TABLE_ADDR_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) XSDFEC_QC_TABLE_DEPTH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) err_out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) kfree(ldpc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) static int xsdfec_set_order(struct xsdfec_dev *xsdfec, void __user *arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) bool order_invalid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) enum xsdfec_order order;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) err = get_user(order, (enum xsdfec_order __user *)arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) return -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) order_invalid = (order != XSDFEC_MAINTAIN_ORDER) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) (order != XSDFEC_OUT_OF_ORDER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) if (order_invalid)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) /* Verify Device has not started */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) if (xsdfec->state == XSDFEC_STARTED)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) xsdfec_regwrite(xsdfec, XSDFEC_ORDER_ADDR, order);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) xsdfec->config.order = order;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) static int xsdfec_set_bypass(struct xsdfec_dev *xsdfec, bool __user *arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) bool bypass;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) err = get_user(bypass, arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) return -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) /* Verify Device has not started */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) if (xsdfec->state == XSDFEC_STARTED)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) if (bypass)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) xsdfec_regwrite(xsdfec, XSDFEC_BYPASS_ADDR, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) xsdfec_regwrite(xsdfec, XSDFEC_BYPASS_ADDR, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) xsdfec->config.bypass = bypass;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) static int xsdfec_is_active(struct xsdfec_dev *xsdfec, bool __user *arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) u32 reg_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) bool is_active;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) reg_value = xsdfec_regread(xsdfec, XSDFEC_ACTIVE_ADDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) /* using a double ! operator instead of casting */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) is_active = !!(reg_value & XSDFEC_IS_ACTIVITY_SET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) err = put_user(is_active, arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) return -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) static u32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) xsdfec_translate_axis_width_cfg_val(enum xsdfec_axis_width axis_width_cfg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) u32 axis_width_field = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) switch (axis_width_cfg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) case XSDFEC_1x128b:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) axis_width_field = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) case XSDFEC_2x128b:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) axis_width_field = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) case XSDFEC_4x128b:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) axis_width_field = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) return axis_width_field;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) static u32 xsdfec_translate_axis_words_cfg_val(enum xsdfec_axis_word_include
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) axis_word_inc_cfg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) u32 axis_words_field = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) if (axis_word_inc_cfg == XSDFEC_FIXED_VALUE ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) axis_word_inc_cfg == XSDFEC_IN_BLOCK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) axis_words_field = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) else if (axis_word_inc_cfg == XSDFEC_PER_AXI_TRANSACTION)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) axis_words_field = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) return axis_words_field;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) static int xsdfec_cfg_axi_streams(struct xsdfec_dev *xsdfec)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) u32 reg_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) u32 dout_words_field;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) u32 dout_width_field;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) u32 din_words_field;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) u32 din_width_field;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) struct xsdfec_config *config = &xsdfec->config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) /* translate config info to register values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) dout_words_field =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) xsdfec_translate_axis_words_cfg_val(config->dout_word_include);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) dout_width_field =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) xsdfec_translate_axis_width_cfg_val(config->dout_width);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) din_words_field =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) xsdfec_translate_axis_words_cfg_val(config->din_word_include);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) din_width_field =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) xsdfec_translate_axis_width_cfg_val(config->din_width);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) reg_value = dout_words_field << XSDFEC_AXIS_DOUT_WORDS_LSB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) reg_value |= dout_width_field << XSDFEC_AXIS_DOUT_WIDTH_LSB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) reg_value |= din_words_field << XSDFEC_AXIS_DIN_WORDS_LSB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) reg_value |= din_width_field << XSDFEC_AXIS_DIN_WIDTH_LSB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) xsdfec_regwrite(xsdfec, XSDFEC_AXIS_WIDTH_ADDR, reg_value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) static int xsdfec_dev_open(struct inode *iptr, struct file *fptr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) static int xsdfec_dev_release(struct inode *iptr, struct file *fptr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) static int xsdfec_start(struct xsdfec_dev *xsdfec)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) u32 regread;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) regread = xsdfec_regread(xsdfec, XSDFEC_FEC_CODE_ADDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) regread &= 0x1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) if (regread != xsdfec->config.code) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) dev_dbg(xsdfec->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) "%s SDFEC HW code does not match driver code, reg %d, code %d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) __func__, regread, xsdfec->config.code);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) /* Set AXIS enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) xsdfec_regwrite(xsdfec, XSDFEC_AXIS_ENABLE_ADDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) XSDFEC_AXIS_ENABLE_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) /* Done */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) xsdfec->state = XSDFEC_STARTED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) static int xsdfec_stop(struct xsdfec_dev *xsdfec)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) u32 regread;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) if (xsdfec->state != XSDFEC_STARTED)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) dev_dbg(xsdfec->dev, "Device not started correctly");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) /* Disable AXIS_ENABLE Input interfaces only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) regread = xsdfec_regread(xsdfec, XSDFEC_AXIS_ENABLE_ADDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) regread &= (~XSDFEC_AXIS_IN_ENABLE_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) xsdfec_regwrite(xsdfec, XSDFEC_AXIS_ENABLE_ADDR, regread);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) /* Stop */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) xsdfec->state = XSDFEC_STOPPED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) static int xsdfec_clear_stats(struct xsdfec_dev *xsdfec)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) spin_lock_irqsave(&xsdfec->error_data_lock, xsdfec->flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) xsdfec->isr_err_count = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) xsdfec->uecc_count = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) xsdfec->cecc_count = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) spin_unlock_irqrestore(&xsdfec->error_data_lock, xsdfec->flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) static int xsdfec_get_stats(struct xsdfec_dev *xsdfec, void __user *arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) struct xsdfec_stats user_stats;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) spin_lock_irqsave(&xsdfec->error_data_lock, xsdfec->flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) user_stats.isr_err_count = xsdfec->isr_err_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) user_stats.cecc_count = xsdfec->cecc_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) user_stats.uecc_count = xsdfec->uecc_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) xsdfec->stats_updated = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) spin_unlock_irqrestore(&xsdfec->error_data_lock, xsdfec->flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) err = copy_to_user(arg, &user_stats, sizeof(user_stats));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) err = -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) static int xsdfec_set_default_config(struct xsdfec_dev *xsdfec)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) /* Ensure registers are aligned with core configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) xsdfec_regwrite(xsdfec, XSDFEC_FEC_CODE_ADDR, xsdfec->config.code);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) xsdfec_cfg_axi_streams(xsdfec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) update_config_from_hw(xsdfec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) static long xsdfec_dev_ioctl(struct file *fptr, unsigned int cmd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) unsigned long data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) struct xsdfec_dev *xsdfec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) void __user *arg = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) int rval = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) xsdfec = container_of(fptr->private_data, struct xsdfec_dev, miscdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) /* In failed state allow only reset and get status IOCTLs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) if (xsdfec->state == XSDFEC_NEEDS_RESET &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) (cmd != XSDFEC_SET_DEFAULT_CONFIG && cmd != XSDFEC_GET_STATUS &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) cmd != XSDFEC_GET_STATS && cmd != XSDFEC_CLEAR_STATS)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) return -EPERM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) if (_IOC_TYPE(cmd) != XSDFEC_MAGIC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) return -ENOTTY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) /* check if ioctl argument is present and valid */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) if (_IOC_DIR(cmd) != _IOC_NONE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) arg = (void __user *)data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) if (!arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) return rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) switch (cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) case XSDFEC_START_DEV:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) rval = xsdfec_start(xsdfec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) case XSDFEC_STOP_DEV:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) rval = xsdfec_stop(xsdfec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) case XSDFEC_CLEAR_STATS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) rval = xsdfec_clear_stats(xsdfec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) case XSDFEC_GET_STATS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) rval = xsdfec_get_stats(xsdfec, arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) case XSDFEC_GET_STATUS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) rval = xsdfec_get_status(xsdfec, arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) case XSDFEC_GET_CONFIG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) rval = xsdfec_get_config(xsdfec, arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) case XSDFEC_SET_DEFAULT_CONFIG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) rval = xsdfec_set_default_config(xsdfec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) case XSDFEC_SET_IRQ:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) rval = xsdfec_set_irq(xsdfec, arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) case XSDFEC_SET_TURBO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) rval = xsdfec_set_turbo(xsdfec, arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) case XSDFEC_GET_TURBO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) rval = xsdfec_get_turbo(xsdfec, arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) case XSDFEC_ADD_LDPC_CODE_PARAMS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) rval = xsdfec_add_ldpc(xsdfec, arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) case XSDFEC_SET_ORDER:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) rval = xsdfec_set_order(xsdfec, arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) case XSDFEC_SET_BYPASS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) rval = xsdfec_set_bypass(xsdfec, arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) case XSDFEC_IS_ACTIVE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) rval = xsdfec_is_active(xsdfec, (bool __user *)arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) /* Should not get here */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) return rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) #ifdef CONFIG_COMPAT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) static long xsdfec_dev_compat_ioctl(struct file *file, unsigned int cmd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) unsigned long data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) return xsdfec_dev_ioctl(file, cmd, (unsigned long)compat_ptr(data));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) static __poll_t xsdfec_poll(struct file *file, poll_table *wait)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) __poll_t mask = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) struct xsdfec_dev *xsdfec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) xsdfec = container_of(file->private_data, struct xsdfec_dev, miscdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) if (!xsdfec)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) return EPOLLNVAL | EPOLLHUP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) poll_wait(file, &xsdfec->waitq, wait);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) /* XSDFEC ISR detected an error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) spin_lock_irqsave(&xsdfec->error_data_lock, xsdfec->flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) if (xsdfec->state_updated)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) mask |= EPOLLIN | EPOLLPRI;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) if (xsdfec->stats_updated)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) mask |= EPOLLIN | EPOLLRDNORM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) spin_unlock_irqrestore(&xsdfec->error_data_lock, xsdfec->flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) return mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) static const struct file_operations xsdfec_fops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) .open = xsdfec_dev_open,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) .release = xsdfec_dev_release,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) .unlocked_ioctl = xsdfec_dev_ioctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) .poll = xsdfec_poll,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) #ifdef CONFIG_COMPAT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) .compat_ioctl = xsdfec_dev_compat_ioctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) static int xsdfec_parse_of(struct xsdfec_dev *xsdfec)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) struct device *dev = xsdfec->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) struct device_node *node = dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) int rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) const char *fec_code;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) u32 din_width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) u32 din_word_include;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) u32 dout_width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) u32 dout_word_include;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) rval = of_property_read_string(node, "xlnx,sdfec-code", &fec_code);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) if (rval < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) return rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) if (!strcasecmp(fec_code, "ldpc"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) xsdfec->config.code = XSDFEC_LDPC_CODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) else if (!strcasecmp(fec_code, "turbo"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) xsdfec->config.code = XSDFEC_TURBO_CODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) rval = of_property_read_u32(node, "xlnx,sdfec-din-words",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) &din_word_include);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) if (rval < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) return rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) if (din_word_include < XSDFEC_AXIS_WORDS_INCLUDE_MAX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) xsdfec->config.din_word_include = din_word_include;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) rval = of_property_read_u32(node, "xlnx,sdfec-din-width", &din_width);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) if (rval < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) return rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) switch (din_width) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) /* Fall through and set for valid values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) case XSDFEC_1x128b:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) case XSDFEC_2x128b:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) case XSDFEC_4x128b:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) xsdfec->config.din_width = din_width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) rval = of_property_read_u32(node, "xlnx,sdfec-dout-words",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) &dout_word_include);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) if (rval < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) return rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) if (dout_word_include < XSDFEC_AXIS_WORDS_INCLUDE_MAX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) xsdfec->config.dout_word_include = dout_word_include;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) rval = of_property_read_u32(node, "xlnx,sdfec-dout-width", &dout_width);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) if (rval < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) return rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) switch (dout_width) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) /* Fall through and set for valid values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) case XSDFEC_1x128b:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) case XSDFEC_2x128b:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) case XSDFEC_4x128b:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) xsdfec->config.dout_width = dout_width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) /* Write LDPC to CODE Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) xsdfec_regwrite(xsdfec, XSDFEC_FEC_CODE_ADDR, xsdfec->config.code);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) xsdfec_cfg_axi_streams(xsdfec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) static irqreturn_t xsdfec_irq_thread(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) struct xsdfec_dev *xsdfec = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) irqreturn_t ret = IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) u32 ecc_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) u32 isr_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) u32 uecc_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) u32 cecc_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) u32 isr_err_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) u32 aecc_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) u32 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) WARN_ON(xsdfec->irq != irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) /* Mask Interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) xsdfec_isr_enable(xsdfec, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) xsdfec_ecc_isr_enable(xsdfec, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) /* Read ISR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) ecc_err = xsdfec_regread(xsdfec, XSDFEC_ECC_ISR_ADDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) isr_err = xsdfec_regread(xsdfec, XSDFEC_ISR_ADDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) /* Clear the interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) xsdfec_regwrite(xsdfec, XSDFEC_ECC_ISR_ADDR, ecc_err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) xsdfec_regwrite(xsdfec, XSDFEC_ISR_ADDR, isr_err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) tmp = ecc_err & XSDFEC_ALL_ECC_ISR_MBE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) /* Count uncorrectable 2-bit errors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) uecc_count = hweight32(tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) /* Count all ECC errors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) aecc_count = hweight32(ecc_err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) /* Number of correctable 1-bit ECC error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) cecc_count = aecc_count - 2 * uecc_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) /* Count ISR errors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) isr_err_count = hweight32(isr_err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) dev_dbg(xsdfec->dev, "tmp=%x, uecc=%x, aecc=%x, cecc=%x, isr=%x", tmp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) uecc_count, aecc_count, cecc_count, isr_err_count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) dev_dbg(xsdfec->dev, "uecc=%x, cecc=%x, isr=%x", xsdfec->uecc_count,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) xsdfec->cecc_count, xsdfec->isr_err_count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) spin_lock_irqsave(&xsdfec->error_data_lock, xsdfec->flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) /* Add new errors to a 2-bits counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) if (uecc_count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) xsdfec->uecc_count += uecc_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) /* Add new errors to a 1-bits counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) if (cecc_count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) xsdfec->cecc_count += cecc_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) /* Add new errors to a ISR counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) if (isr_err_count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) xsdfec->isr_err_count += isr_err_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) /* Update state/stats flag */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) if (uecc_count) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) if (ecc_err & XSDFEC_ECC_ISR_MBE_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) xsdfec->state = XSDFEC_NEEDS_RESET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) else if (ecc_err & XSDFEC_PL_INIT_ECC_ISR_MBE_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) xsdfec->state = XSDFEC_PL_RECONFIGURE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) xsdfec->stats_updated = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) xsdfec->state_updated = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) if (cecc_count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) xsdfec->stats_updated = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) if (isr_err_count) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) xsdfec->state = XSDFEC_NEEDS_RESET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) xsdfec->stats_updated = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) xsdfec->state_updated = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) spin_unlock_irqrestore(&xsdfec->error_data_lock, xsdfec->flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) dev_dbg(xsdfec->dev, "state=%x, stats=%x", xsdfec->state_updated,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) xsdfec->stats_updated);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) /* Enable another polling */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) if (xsdfec->state_updated || xsdfec->stats_updated)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) wake_up_interruptible(&xsdfec->waitq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) ret = IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) /* Unmask Interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) xsdfec_isr_enable(xsdfec, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) xsdfec_ecc_isr_enable(xsdfec, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) static int xsdfec_clk_init(struct platform_device *pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) struct xsdfec_clks *clks)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) clks->core_clk = devm_clk_get(&pdev->dev, "core_clk");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) if (IS_ERR(clks->core_clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) dev_err(&pdev->dev, "failed to get core_clk");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) return PTR_ERR(clks->core_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) clks->axi_clk = devm_clk_get(&pdev->dev, "s_axi_aclk");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) if (IS_ERR(clks->axi_clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) dev_err(&pdev->dev, "failed to get axi_clk");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) return PTR_ERR(clks->axi_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) clks->din_words_clk = devm_clk_get(&pdev->dev, "s_axis_din_words_aclk");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) if (IS_ERR(clks->din_words_clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) if (PTR_ERR(clks->din_words_clk) != -ENOENT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) err = PTR_ERR(clks->din_words_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) clks->din_words_clk = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) clks->din_clk = devm_clk_get(&pdev->dev, "s_axis_din_aclk");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) if (IS_ERR(clks->din_clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) if (PTR_ERR(clks->din_clk) != -ENOENT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) err = PTR_ERR(clks->din_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) clks->din_clk = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) clks->dout_clk = devm_clk_get(&pdev->dev, "m_axis_dout_aclk");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) if (IS_ERR(clks->dout_clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) if (PTR_ERR(clks->dout_clk) != -ENOENT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) err = PTR_ERR(clks->dout_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) clks->dout_clk = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) clks->dout_words_clk =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) devm_clk_get(&pdev->dev, "s_axis_dout_words_aclk");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) if (IS_ERR(clks->dout_words_clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) if (PTR_ERR(clks->dout_words_clk) != -ENOENT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) err = PTR_ERR(clks->dout_words_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) clks->dout_words_clk = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) clks->ctrl_clk = devm_clk_get(&pdev->dev, "s_axis_ctrl_aclk");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) if (IS_ERR(clks->ctrl_clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) if (PTR_ERR(clks->ctrl_clk) != -ENOENT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) err = PTR_ERR(clks->ctrl_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) clks->ctrl_clk = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) clks->status_clk = devm_clk_get(&pdev->dev, "m_axis_status_aclk");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) if (IS_ERR(clks->status_clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) if (PTR_ERR(clks->status_clk) != -ENOENT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) err = PTR_ERR(clks->status_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) clks->status_clk = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) err = clk_prepare_enable(clks->core_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) dev_err(&pdev->dev, "failed to enable core_clk (%d)", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) err = clk_prepare_enable(clks->axi_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) dev_err(&pdev->dev, "failed to enable axi_clk (%d)", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) goto err_disable_core_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) err = clk_prepare_enable(clks->din_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) dev_err(&pdev->dev, "failed to enable din_clk (%d)", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) goto err_disable_axi_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) err = clk_prepare_enable(clks->din_words_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) dev_err(&pdev->dev, "failed to enable din_words_clk (%d)", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) goto err_disable_din_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) err = clk_prepare_enable(clks->dout_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) dev_err(&pdev->dev, "failed to enable dout_clk (%d)", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) goto err_disable_din_words_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) err = clk_prepare_enable(clks->dout_words_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) dev_err(&pdev->dev, "failed to enable dout_words_clk (%d)",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) goto err_disable_dout_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) err = clk_prepare_enable(clks->ctrl_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) dev_err(&pdev->dev, "failed to enable ctrl_clk (%d)", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) goto err_disable_dout_words_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) err = clk_prepare_enable(clks->status_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) dev_err(&pdev->dev, "failed to enable status_clk (%d)\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) goto err_disable_ctrl_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) err_disable_ctrl_clk:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) clk_disable_unprepare(clks->ctrl_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) err_disable_dout_words_clk:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) clk_disable_unprepare(clks->dout_words_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) err_disable_dout_clk:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) clk_disable_unprepare(clks->dout_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) err_disable_din_words_clk:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) clk_disable_unprepare(clks->din_words_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) err_disable_din_clk:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) clk_disable_unprepare(clks->din_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) err_disable_axi_clk:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) clk_disable_unprepare(clks->axi_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) err_disable_core_clk:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) clk_disable_unprepare(clks->core_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) static void xsdfec_disable_all_clks(struct xsdfec_clks *clks)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) clk_disable_unprepare(clks->status_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) clk_disable_unprepare(clks->ctrl_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) clk_disable_unprepare(clks->dout_words_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) clk_disable_unprepare(clks->dout_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) clk_disable_unprepare(clks->din_words_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) clk_disable_unprepare(clks->din_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) clk_disable_unprepare(clks->core_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) clk_disable_unprepare(clks->axi_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) static int xsdfec_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) struct xsdfec_dev *xsdfec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) bool irq_enabled = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) xsdfec = devm_kzalloc(&pdev->dev, sizeof(*xsdfec), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) if (!xsdfec)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) xsdfec->dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) spin_lock_init(&xsdfec->error_data_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) err = xsdfec_clk_init(pdev, &xsdfec->clks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) dev = xsdfec->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) xsdfec->regs = devm_ioremap_resource(dev, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) if (IS_ERR(xsdfec->regs)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) err = PTR_ERR(xsdfec->regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) goto err_xsdfec_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) xsdfec->irq = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) if (xsdfec->irq < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) dev_dbg(dev, "platform_get_irq failed");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) irq_enabled = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) err = xsdfec_parse_of(xsdfec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) goto err_xsdfec_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) update_config_from_hw(xsdfec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) /* Save driver private data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) platform_set_drvdata(pdev, xsdfec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) if (irq_enabled) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) init_waitqueue_head(&xsdfec->waitq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) /* Register IRQ thread */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) err = devm_request_threaded_irq(dev, xsdfec->irq, NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) xsdfec_irq_thread, IRQF_ONESHOT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) "xilinx-sdfec16", xsdfec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) dev_err(dev, "unable to request IRQ%d", xsdfec->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) goto err_xsdfec_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) err = ida_alloc(&dev_nrs, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) goto err_xsdfec_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) xsdfec->dev_id = err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) snprintf(xsdfec->dev_name, DEV_NAME_LEN, "xsdfec%d", xsdfec->dev_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) xsdfec->miscdev.minor = MISC_DYNAMIC_MINOR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) xsdfec->miscdev.name = xsdfec->dev_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) xsdfec->miscdev.fops = &xsdfec_fops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) xsdfec->miscdev.parent = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) err = misc_register(&xsdfec->miscdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) dev_err(dev, "error:%d. Unable to register device", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) goto err_xsdfec_ida;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) err_xsdfec_ida:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) ida_free(&dev_nrs, xsdfec->dev_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) err_xsdfec_dev:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) xsdfec_disable_all_clks(&xsdfec->clks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) static int xsdfec_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) struct xsdfec_dev *xsdfec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) xsdfec = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) misc_deregister(&xsdfec->miscdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) ida_free(&dev_nrs, xsdfec->dev_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) xsdfec_disable_all_clks(&xsdfec->clks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) static const struct of_device_id xsdfec_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) .compatible = "xlnx,sd-fec-1.1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) { /* end of table */ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) MODULE_DEVICE_TABLE(of, xsdfec_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) static struct platform_driver xsdfec_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) .name = "xilinx-sdfec",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) .of_match_table = xsdfec_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) .probe = xsdfec_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) .remove = xsdfec_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) module_platform_driver(xsdfec_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) MODULE_AUTHOR("Xilinx, Inc");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) MODULE_DESCRIPTION("Xilinx SD-FEC16 Driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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