^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-or-later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * SN Platform GRU Driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * GRU HANDLE DEFINITION
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Copyright (c) 2008 Silicon Graphics, Inc. All Rights Reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #ifndef __GRUHANDLES_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define __GRUHANDLES_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include "gru_instructions.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * Manifest constants for GRU Memory Map
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define GRU_GSEG0_BASE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define GRU_MCS_BASE (64 * 1024 * 1024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define GRU_SIZE (128UL * 1024 * 1024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) /* Handle & resource counts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define GRU_NUM_CB 128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define GRU_NUM_DSR_BYTES (32 * 1024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define GRU_NUM_TFM 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define GRU_NUM_TGH 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define GRU_NUM_CBE 128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define GRU_NUM_TFH 128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define GRU_NUM_CCH 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) /* Maximum resource counts that can be reserved by user programs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define GRU_NUM_USER_CBR GRU_NUM_CBE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define GRU_NUM_USER_DSR_BYTES GRU_NUM_DSR_BYTES
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) /* Bytes per handle & handle stride. Code assumes all cb, tfh, cbe handles
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) * are the same */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define GRU_HANDLE_BYTES 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define GRU_HANDLE_STRIDE 256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) /* Base addresses of handles */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define GRU_TFM_BASE (GRU_MCS_BASE + 0x00000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define GRU_TGH_BASE (GRU_MCS_BASE + 0x08000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define GRU_CBE_BASE (GRU_MCS_BASE + 0x10000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define GRU_TFH_BASE (GRU_MCS_BASE + 0x18000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define GRU_CCH_BASE (GRU_MCS_BASE + 0x20000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) /* User gseg constants */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define GRU_GSEG_STRIDE (4 * 1024 * 1024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define GSEG_BASE(a) ((a) & ~(GRU_GSEG_PAGESIZE - 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) /* Data segment constants */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define GRU_DSR_AU_BYTES 1024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define GRU_DSR_CL (GRU_NUM_DSR_BYTES / GRU_CACHE_LINE_BYTES)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define GRU_DSR_AU_CL (GRU_DSR_AU_BYTES / GRU_CACHE_LINE_BYTES)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define GRU_DSR_AU (GRU_NUM_DSR_BYTES / GRU_DSR_AU_BYTES)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) /* Control block constants */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define GRU_CBR_AU_SIZE 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define GRU_CBR_AU (GRU_NUM_CBE / GRU_CBR_AU_SIZE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) /* Convert resource counts to the number of AU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define GRU_DS_BYTES_TO_AU(n) DIV_ROUND_UP(n, GRU_DSR_AU_BYTES)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define GRU_CB_COUNT_TO_AU(n) DIV_ROUND_UP(n, GRU_CBR_AU_SIZE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) /* UV limits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define GRU_CHIPLETS_PER_HUB 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define GRU_HUBS_PER_BLADE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define GRU_CHIPLETS_PER_BLADE (GRU_HUBS_PER_BLADE * GRU_CHIPLETS_PER_HUB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) /* User GRU Gseg offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define GRU_CB_BASE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define GRU_CB_LIMIT (GRU_CB_BASE + GRU_HANDLE_STRIDE * GRU_NUM_CBE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define GRU_DS_BASE 0x20000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define GRU_DS_LIMIT (GRU_DS_BASE + GRU_NUM_DSR_BYTES)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) /* Convert a GRU physical address to the chiplet offset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define GSEGPOFF(h) ((h) & (GRU_SIZE - 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) /* Convert an arbitrary handle address to the beginning of the GRU segment */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define GRUBASE(h) ((void *)((unsigned long)(h) & ~(GRU_SIZE - 1)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) /* Test a valid handle address to determine the type */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define TYPE_IS(hn, h) ((h) >= GRU_##hn##_BASE && (h) < \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) GRU_##hn##_BASE + GRU_NUM_##hn * GRU_HANDLE_STRIDE && \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) (((h) & (GRU_HANDLE_STRIDE - 1)) == 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) /* General addressing macros. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) static inline void *get_gseg_base_address(void *base, int ctxnum)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) return (void *)(base + GRU_GSEG0_BASE + GRU_GSEG_STRIDE * ctxnum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) static inline void *get_gseg_base_address_cb(void *base, int ctxnum, int line)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) return (void *)(get_gseg_base_address(base, ctxnum) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) GRU_CB_BASE + GRU_HANDLE_STRIDE * line);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) static inline void *get_gseg_base_address_ds(void *base, int ctxnum, int line)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) return (void *)(get_gseg_base_address(base, ctxnum) + GRU_DS_BASE +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) GRU_CACHE_LINE_BYTES * line);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) static inline struct gru_tlb_fault_map *get_tfm(void *base, int ctxnum)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) return (struct gru_tlb_fault_map *)(base + GRU_TFM_BASE +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) ctxnum * GRU_HANDLE_STRIDE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) static inline struct gru_tlb_global_handle *get_tgh(void *base, int ctxnum)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) return (struct gru_tlb_global_handle *)(base + GRU_TGH_BASE +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) ctxnum * GRU_HANDLE_STRIDE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) static inline struct gru_control_block_extended *get_cbe(void *base, int ctxnum)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) return (struct gru_control_block_extended *)(base + GRU_CBE_BASE +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) ctxnum * GRU_HANDLE_STRIDE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) static inline struct gru_tlb_fault_handle *get_tfh(void *base, int ctxnum)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) return (struct gru_tlb_fault_handle *)(base + GRU_TFH_BASE +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) ctxnum * GRU_HANDLE_STRIDE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) static inline struct gru_context_configuration_handle *get_cch(void *base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) int ctxnum)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) return (struct gru_context_configuration_handle *)(base +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) GRU_CCH_BASE + ctxnum * GRU_HANDLE_STRIDE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) static inline unsigned long get_cb_number(void *cb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) return (((unsigned long)cb - GRU_CB_BASE) % GRU_GSEG_PAGESIZE) /
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) GRU_HANDLE_STRIDE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) /* byte offset to a specific GRU chiplet. (p=pnode, c=chiplet (0 or 1)*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) static inline unsigned long gru_chiplet_paddr(unsigned long paddr, int pnode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) int chiplet)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) return paddr + GRU_SIZE * (2 * pnode + chiplet);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) static inline void *gru_chiplet_vaddr(void *vaddr, int pnode, int chiplet)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) return vaddr + GRU_SIZE * (2 * pnode + chiplet);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) static inline struct gru_control_block_extended *gru_tfh_to_cbe(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) struct gru_tlb_fault_handle *tfh)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) unsigned long cbe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) cbe = (unsigned long)tfh - GRU_TFH_BASE + GRU_CBE_BASE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) return (struct gru_control_block_extended*)cbe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) * Global TLB Fault Map
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) * Bitmap of outstanding TLB misses needing interrupt/polling service.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) struct gru_tlb_fault_map {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) unsigned long fault_bits[BITS_TO_LONGS(GRU_NUM_CBE)];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) unsigned long fill0[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) unsigned long done_bits[BITS_TO_LONGS(GRU_NUM_CBE)];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) unsigned long fill1[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) * TGH - TLB Global Handle
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) * Used for TLB flushing.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) struct gru_tlb_global_handle {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) unsigned int cmd:1; /* DW 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) unsigned int delresp:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) unsigned int opc:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) unsigned int fill1:5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) unsigned int fill2:8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) unsigned int status:2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) unsigned long fill3:2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) unsigned int state:3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) unsigned long fill4:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) unsigned int cause:3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) unsigned long fill5:37;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) unsigned long vaddr:64; /* DW 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) unsigned int asid:24; /* DW 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) unsigned int fill6:8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) unsigned int pagesize:5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) unsigned int fill7:11;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) unsigned int global:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) unsigned int fill8:15;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) unsigned long vaddrmask:39; /* DW 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) unsigned int fill9:9;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) unsigned int n:10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) unsigned int fill10:6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) unsigned int ctxbitmap:16; /* DW4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) unsigned long fill11[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) enum gru_tgh_cmd {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) TGHCMD_START
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) enum gru_tgh_opc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) TGHOP_TLBNOP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) TGHOP_TLBINV
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) enum gru_tgh_status {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) TGHSTATUS_IDLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) TGHSTATUS_EXCEPTION,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) TGHSTATUS_ACTIVE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) enum gru_tgh_state {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) TGHSTATE_IDLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) TGHSTATE_PE_INVAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) TGHSTATE_INTERRUPT_INVAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) TGHSTATE_WAITDONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) TGHSTATE_RESTART_CTX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) enum gru_tgh_cause {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) TGHCAUSE_RR_ECC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) TGHCAUSE_TLB_ECC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) TGHCAUSE_LRU_ECC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) TGHCAUSE_PS_ECC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) TGHCAUSE_MUL_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) TGHCAUSE_DATA_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) TGHCAUSE_SW_FORCE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) * TFH - TLB Global Handle
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) * Used for TLB dropins into the GRU TLB.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) struct gru_tlb_fault_handle {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) unsigned int cmd:1; /* DW 0 - low 32*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) unsigned int delresp:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) unsigned int fill0:2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) unsigned int opc:3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) unsigned int fill1:9;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) unsigned int status:2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) unsigned int fill2:2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) unsigned int state:3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) unsigned int fill3:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) unsigned int cause:6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) unsigned int cb_int:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) unsigned int fill4:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) unsigned int indexway:12; /* DW 0 - high 32 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) unsigned int fill5:4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) unsigned int ctxnum:4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) unsigned int fill6:12;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) unsigned long missvaddr:64; /* DW 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) unsigned int missasid:24; /* DW 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) unsigned int fill7:8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) unsigned int fillasid:24;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) unsigned int dirty:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) unsigned int gaa:2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) unsigned long fill8:5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) unsigned long pfn:41; /* DW 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) unsigned int fill9:7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) unsigned int pagesize:5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) unsigned int fill10:11;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) unsigned long fillvaddr:64; /* DW 4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) unsigned long fill11[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) enum gru_tfh_opc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) TFHOP_NOOP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) TFHOP_RESTART,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) TFHOP_WRITE_ONLY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) TFHOP_WRITE_RESTART,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) TFHOP_EXCEPTION,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) TFHOP_USER_POLLING_MODE = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) enum tfh_status {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) TFHSTATUS_IDLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) TFHSTATUS_EXCEPTION,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) TFHSTATUS_ACTIVE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) enum tfh_state {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) TFHSTATE_INACTIVE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) TFHSTATE_IDLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) TFHSTATE_MISS_UPM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) TFHSTATE_MISS_FMM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) TFHSTATE_HW_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) TFHSTATE_WRITE_TLB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) TFHSTATE_RESTART_CBR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) /* TFH cause bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) enum tfh_cause {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) TFHCAUSE_NONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) TFHCAUSE_TLB_MISS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) TFHCAUSE_TLB_MOD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) TFHCAUSE_HW_ERROR_RR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) TFHCAUSE_HW_ERROR_MAIN_ARRAY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) TFHCAUSE_HW_ERROR_VALID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) TFHCAUSE_HW_ERROR_PAGESIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) TFHCAUSE_INSTRUCTION_EXCEPTION,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) TFHCAUSE_UNCORRECTIBLE_ERROR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) /* GAA values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) #define GAA_RAM 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) #define GAA_NCRAM 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) #define GAA_MMIO 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) #define GAA_REGISTER 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) /* GRU paddr shift for pfn. (NOTE: shift is NOT by actual pagesize) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) #define GRU_PADDR_SHIFT 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) * Context Configuration handle
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) * Used to allocate resources to a GSEG context.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) struct gru_context_configuration_handle {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) unsigned int cmd:1; /* DW0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) unsigned int delresp:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) unsigned int opc:3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) unsigned int unmap_enable:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) unsigned int req_slice_set_enable:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) unsigned int req_slice:2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) unsigned int cb_int_enable:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) unsigned int tlb_int_enable:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) unsigned int tfm_fault_bit_enable:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) unsigned int tlb_int_select:4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) unsigned int status:2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) unsigned int state:2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) unsigned int reserved2:4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) unsigned int cause:4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) unsigned int tfm_done_bit_enable:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) unsigned int unused:3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) unsigned int dsr_allocation_map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) unsigned long cbr_allocation_map; /* DW1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) unsigned int asid[8]; /* DW 2 - 5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) unsigned short sizeavail[8]; /* DW 6 - 7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) } __attribute__ ((packed));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) enum gru_cch_opc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) CCHOP_START = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) CCHOP_ALLOCATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) CCHOP_INTERRUPT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) CCHOP_DEALLOCATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) CCHOP_INTERRUPT_SYNC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) enum gru_cch_status {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) CCHSTATUS_IDLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) CCHSTATUS_EXCEPTION,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) CCHSTATUS_ACTIVE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) enum gru_cch_state {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) CCHSTATE_INACTIVE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) CCHSTATE_MAPPED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) CCHSTATE_ACTIVE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) CCHSTATE_INTERRUPTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) /* CCH Exception cause */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) enum gru_cch_cause {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) CCHCAUSE_REGION_REGISTER_WRITE_ERROR = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) CCHCAUSE_ILLEGAL_OPCODE = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) CCHCAUSE_INVALID_START_REQUEST = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) CCHCAUSE_INVALID_ALLOCATION_REQUEST = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) CCHCAUSE_INVALID_DEALLOCATION_REQUEST = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) CCHCAUSE_INVALID_INTERRUPT_REQUEST = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) CCHCAUSE_CCH_BUSY = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) CCHCAUSE_NO_CBRS_TO_ALLOCATE = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) CCHCAUSE_BAD_TFM_CONFIG = 9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) CCHCAUSE_CBR_RESOURCES_OVERSUBSCRIPED = 10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) CCHCAUSE_DSR_RESOURCES_OVERSUBSCRIPED = 11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) CCHCAUSE_CBR_DEALLOCATION_ERROR = 12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) * CBE - Control Block Extended
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) * Maintains internal GRU state for active CBs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) struct gru_control_block_extended {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) unsigned int reserved0:1; /* DW 0 - low */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) unsigned int imacpy:3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) unsigned int reserved1:4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) unsigned int xtypecpy:3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) unsigned int iaa0cpy:2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) unsigned int iaa1cpy:2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) unsigned int reserved2:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) unsigned int opccpy:8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) unsigned int exopccpy:8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) unsigned int idef2cpy:22; /* DW 0 - high */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) unsigned int reserved3:10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) unsigned int idef4cpy:22; /* DW 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) unsigned int reserved4:10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) unsigned int idef4upd:22;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) unsigned int reserved5:10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) unsigned long idef1upd:64; /* DW 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) unsigned long idef5cpy:64; /* DW 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) unsigned long idef6cpy:64; /* DW 4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) unsigned long idef3upd:64; /* DW 5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) unsigned long idef5upd:64; /* DW 6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) unsigned int idef2upd:22; /* DW 7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) unsigned int reserved6:10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) unsigned int ecause:20;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) unsigned int cbrstate:4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) unsigned int cbrexecstatus:8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) /* CBE fields for active BCOPY instructions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) #define cbe_baddr0 idef1upd
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) #define cbe_baddr1 idef3upd
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) #define cbe_src_cl idef6cpy
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) #define cbe_nelemcur idef5upd
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) enum gru_cbr_state {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) CBRSTATE_INACTIVE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) CBRSTATE_IDLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) CBRSTATE_PE_CHECK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) CBRSTATE_QUEUED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) CBRSTATE_WAIT_RESPONSE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) CBRSTATE_INTERRUPTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) CBRSTATE_INTERRUPTED_MISS_FMM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) CBRSTATE_BUSY_INTERRUPT_MISS_FMM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) CBRSTATE_INTERRUPTED_MISS_UPM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) CBRSTATE_BUSY_INTERRUPTED_MISS_UPM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) CBRSTATE_REQUEST_ISSUE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) CBRSTATE_BUSY_INTERRUPT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) /* CBE cbrexecstatus bits - defined in gru_instructions.h*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) /* CBE ecause bits - defined in gru_instructions.h */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) * Convert a processor pagesize into the strange encoded pagesize used by the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) * GRU. Processor pagesize is encoded as log of bytes per page. (or PAGE_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) * pagesize log pagesize grupagesize
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) * 4k 12 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) * 16k 14 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) * 64k 16 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) * 256k 18 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) * 1m 20 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) * 2m 21 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) * 4m 22 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) * 16m 24 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) * 64m 26 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) * ...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) #define GRU_PAGESIZE(sh) ((((sh) > 20 ? (sh) + 2 : (sh)) >> 1) - 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) #define GRU_SIZEAVAIL(sh) (1UL << GRU_PAGESIZE(sh))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) /* minimum TLB purge count to ensure a full purge */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) #define GRUMAXINVAL 1024UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) int cch_allocate(struct gru_context_configuration_handle *cch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) int cch_start(struct gru_context_configuration_handle *cch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) int cch_interrupt(struct gru_context_configuration_handle *cch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) int cch_deallocate(struct gru_context_configuration_handle *cch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) int cch_interrupt_sync(struct gru_context_configuration_handle *cch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) int tgh_invalidate(struct gru_tlb_global_handle *tgh, unsigned long vaddr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) unsigned long vaddrmask, int asid, int pagesize, int global, int n,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) unsigned short ctxbitmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) int tfh_write_only(struct gru_tlb_fault_handle *tfh, unsigned long paddr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) int gaa, unsigned long vaddr, int asid, int dirty, int pagesize);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) void tfh_write_restart(struct gru_tlb_fault_handle *tfh, unsigned long paddr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) int gaa, unsigned long vaddr, int asid, int dirty, int pagesize);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) void tfh_user_polling_mode(struct gru_tlb_fault_handle *tfh);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) void tfh_exception(struct gru_tlb_fault_handle *tfh);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) #endif /* __GRUHANDLES_H__ */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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