^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * Copyright (c) 2008 Silicon Graphics, Inc. All Rights Reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * This program is free software; you can redistribute it and/or modify
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * it under the terms of the GNU Lesser General Public License as published by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * the Free Software Foundation; either version 2.1 of the License, or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * (at your option) any later version.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * This program is distributed in the hope that it will be useful,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * but WITHOUT ANY WARRANTY; without even the implied warranty of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * GNU Lesser General Public License for more details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * You should have received a copy of the GNU Lesser General Public License
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * along with this program; if not, write to the Free Software
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #ifndef __GRU_INSTRUCTIONS_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define __GRU_INSTRUCTIONS_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) extern int gru_check_status_proc(void *cb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) extern int gru_wait_proc(void *cb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) extern void gru_wait_abort_proc(void *cb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) * Architecture dependent functions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #if defined(CONFIG_IA64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #include <linux/compiler.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #include <asm/intrinsics.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define __flush_cache(p) ia64_fc((unsigned long)p)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) /* Use volatile on IA64 to ensure ordering via st4.rel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define gru_ordered_store_ulong(p, v) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) do { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) barrier(); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) *((volatile unsigned long *)(p)) = v; /* force st.rel */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) } while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #elif defined(CONFIG_X86_64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #include <asm/cacheflush.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define __flush_cache(p) clflush(p)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define gru_ordered_store_ulong(p, v) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) do { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) barrier(); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) *(unsigned long *)p = v; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) } while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #error "Unsupported architecture"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) * Control block status and exception codes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define CBS_IDLE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define CBS_EXCEPTION 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define CBS_ACTIVE 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define CBS_CALL_OS 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) /* CB substatus bitmasks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define CBSS_MSG_QUEUE_MASK 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define CBSS_IMPLICIT_ABORT_ACTIVE_MASK 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) /* CB substatus message queue values (low 3 bits of substatus) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define CBSS_NO_ERROR 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define CBSS_LB_OVERFLOWED 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define CBSS_QLIMIT_REACHED 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define CBSS_PAGE_OVERFLOW 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define CBSS_AMO_NACKED 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define CBSS_PUT_NACKED 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) * Structure used to fetch exception detail for CBs that terminate with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) * CBS_EXCEPTION
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) struct control_block_extended_exc_detail {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) unsigned long cb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) int opc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) int ecause;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) int exopc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) long exceptdet0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) int exceptdet1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) int cbrstate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) int cbrexecstatus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) * Instruction formats
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) * Generic instruction format.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) * This definition has precise bit field definitions.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) struct gru_instruction_bits {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) /* DW 0 - low */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) unsigned int icmd: 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) unsigned char ima: 3; /* CB_DelRep, unmapped mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) unsigned char reserved0: 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) unsigned int xtype: 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) unsigned int iaa0: 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) unsigned int iaa1: 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) unsigned char reserved1: 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) unsigned char opc: 8; /* opcode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) unsigned char exopc: 8; /* extended opcode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) /* DW 0 - high */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) unsigned int idef2: 22; /* TRi0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) unsigned char reserved2: 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) unsigned char istatus: 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) unsigned char isubstatus:4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) unsigned char reserved3: 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) unsigned char tlb_fault_color: 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) /* DW 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) unsigned long idef4; /* 42 bits: TRi1, BufSize */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) /* DW 2-6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) unsigned long idef1; /* BAddr0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) unsigned long idef5; /* Nelem */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) unsigned long idef6; /* Stride, Operand1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) unsigned long idef3; /* BAddr1, Value, Operand2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) unsigned long reserved4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) /* DW 7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) unsigned long avalue; /* AValue */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) * Generic instruction with friendlier names. This format is used
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) * for inline instructions.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) struct gru_instruction {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) /* DW 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) unsigned long op64; /* icmd,xtype,iaa0,ima,opc,tri0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) unsigned int op32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) unsigned int tri0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) unsigned long tri1_bufsize; /* DW 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) unsigned long baddr0; /* DW 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) unsigned long nelem; /* DW 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) unsigned long op1_stride; /* DW 4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) unsigned long op2_value_baddr1; /* DW 5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) unsigned long reserved0; /* DW 6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) unsigned long avalue; /* DW 7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) /* Some shifts and masks for the low 64 bits of a GRU command */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define GRU_CB_ICMD_SHFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define GRU_CB_ICMD_MASK 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define GRU_CB_XTYPE_SHFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define GRU_CB_XTYPE_MASK 0x7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define GRU_CB_IAA0_SHFT 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define GRU_CB_IAA0_MASK 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define GRU_CB_IAA1_SHFT 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define GRU_CB_IAA1_MASK 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define GRU_CB_IMA_SHFT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define GRU_CB_IMA_MASK 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define GRU_CB_OPC_SHFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define GRU_CB_OPC_MASK 0xff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define GRU_CB_EXOPC_SHFT 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define GRU_CB_EXOPC_MASK 0xff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define GRU_IDEF2_SHFT 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define GRU_IDEF2_MASK 0x3ffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define GRU_ISTATUS_SHFT 56
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define GRU_ISTATUS_MASK 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) /* GRU instruction opcodes (opc field) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define OP_NOP 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define OP_BCOPY 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define OP_VLOAD 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define OP_IVLOAD 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define OP_VSTORE 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define OP_IVSTORE 0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define OP_VSET 0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define OP_IVSET 0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define OP_MESQ 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define OP_GAMXR 0x09
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define OP_GAMIR 0x0a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define OP_GAMIRR 0x0b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define OP_GAMER 0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define OP_GAMERR 0x0d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define OP_BSTORE 0x0e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define OP_VFLUSH 0x0f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) /* Extended opcodes values (exopc field) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) /* GAMIR - AMOs with implicit operands */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define EOP_IR_FETCH 0x01 /* Plain fetch of memory */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define EOP_IR_CLR 0x02 /* Fetch and clear */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define EOP_IR_INC 0x05 /* Fetch and increment */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define EOP_IR_DEC 0x07 /* Fetch and decrement */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define EOP_IR_QCHK1 0x0d /* Queue check, 64 byte msg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define EOP_IR_QCHK2 0x0e /* Queue check, 128 byte msg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) /* GAMIRR - Registered AMOs with implicit operands */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define EOP_IRR_FETCH 0x01 /* Registered fetch of memory */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define EOP_IRR_CLR 0x02 /* Registered fetch and clear */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define EOP_IRR_INC 0x05 /* Registered fetch and increment */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define EOP_IRR_DEC 0x07 /* Registered fetch and decrement */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define EOP_IRR_DECZ 0x0f /* Registered fetch and decrement, update on zero*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) /* GAMER - AMOs with explicit operands */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define EOP_ER_SWAP 0x00 /* Exchange argument and memory */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #define EOP_ER_OR 0x01 /* Logical OR with memory */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define EOP_ER_AND 0x02 /* Logical AND with memory */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define EOP_ER_XOR 0x03 /* Logical XOR with memory */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define EOP_ER_ADD 0x04 /* Add value to memory */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #define EOP_ER_CSWAP 0x08 /* Compare with operand2, write operand1 if match*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #define EOP_ER_CADD 0x0c /* Queue check, operand1*64 byte msg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) /* GAMERR - Registered AMOs with explicit operands */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #define EOP_ERR_SWAP 0x00 /* Exchange argument and memory */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define EOP_ERR_OR 0x01 /* Logical OR with memory */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #define EOP_ERR_AND 0x02 /* Logical AND with memory */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) #define EOP_ERR_XOR 0x03 /* Logical XOR with memory */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #define EOP_ERR_ADD 0x04 /* Add value to memory */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define EOP_ERR_CSWAP 0x08 /* Compare with operand2, write operand1 if match*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #define EOP_ERR_EPOLL 0x09 /* Poll for equality */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define EOP_ERR_NPOLL 0x0a /* Poll for inequality */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) /* GAMXR - SGI Arithmetic unit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #define EOP_XR_CSWAP 0x0b /* Masked compare exchange */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) /* Transfer types (xtype field) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) #define XTYPE_B 0x0 /* byte */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) #define XTYPE_S 0x1 /* short (2-byte) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) #define XTYPE_W 0x2 /* word (4-byte) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) #define XTYPE_DW 0x3 /* doubleword (8-byte) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) #define XTYPE_CL 0x6 /* cacheline (64-byte) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) /* Instruction access attributes (iaa0, iaa1 fields) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) #define IAA_RAM 0x0 /* normal cached RAM access */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) #define IAA_NCRAM 0x2 /* noncoherent RAM access */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) #define IAA_MMIO 0x1 /* noncoherent memory-mapped I/O space */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) #define IAA_REGISTER 0x3 /* memory-mapped registers, etc. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) /* Instruction mode attributes (ima field) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) #define IMA_MAPPED 0x0 /* Virtual mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) #define IMA_CB_DELAY 0x1 /* hold read responses until status changes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) #define IMA_UNMAPPED 0x2 /* bypass the TLBs (OS only) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) #define IMA_INTERRUPT 0x4 /* Interrupt when instruction completes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) /* CBE ecause bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) #define CBE_CAUSE_RI (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) #define CBE_CAUSE_INVALID_INSTRUCTION (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) #define CBE_CAUSE_UNMAPPED_MODE_FORBIDDEN (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) #define CBE_CAUSE_PE_CHECK_DATA_ERROR (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) #define CBE_CAUSE_IAA_GAA_MISMATCH (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) #define CBE_CAUSE_DATA_SEGMENT_LIMIT_EXCEPTION (1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) #define CBE_CAUSE_OS_FATAL_TLB_FAULT (1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) #define CBE_CAUSE_EXECUTION_HW_ERROR (1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) #define CBE_CAUSE_TLBHW_ERROR (1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) #define CBE_CAUSE_RA_REQUEST_TIMEOUT (1 << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) #define CBE_CAUSE_HA_REQUEST_TIMEOUT (1 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) #define CBE_CAUSE_RA_RESPONSE_FATAL (1 << 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) #define CBE_CAUSE_RA_RESPONSE_NON_FATAL (1 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) #define CBE_CAUSE_HA_RESPONSE_FATAL (1 << 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) #define CBE_CAUSE_HA_RESPONSE_NON_FATAL (1 << 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) #define CBE_CAUSE_ADDRESS_SPACE_DECODE_ERROR (1 << 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) #define CBE_CAUSE_PROTOCOL_STATE_DATA_ERROR (1 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) #define CBE_CAUSE_RA_RESPONSE_DATA_ERROR (1 << 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) #define CBE_CAUSE_HA_RESPONSE_DATA_ERROR (1 << 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) #define CBE_CAUSE_FORCED_ERROR (1 << 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) /* CBE cbrexecstatus bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) #define CBR_EXS_ABORT_OCC_BIT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) #define CBR_EXS_INT_OCC_BIT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) #define CBR_EXS_PENDING_BIT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) #define CBR_EXS_QUEUED_BIT 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) #define CBR_EXS_TLB_INVAL_BIT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) #define CBR_EXS_EXCEPTION_BIT 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) #define CBR_EXS_CB_INT_PENDING_BIT 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) #define CBR_EXS_ABORT_OCC (1 << CBR_EXS_ABORT_OCC_BIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) #define CBR_EXS_INT_OCC (1 << CBR_EXS_INT_OCC_BIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) #define CBR_EXS_PENDING (1 << CBR_EXS_PENDING_BIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) #define CBR_EXS_QUEUED (1 << CBR_EXS_QUEUED_BIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) #define CBR_EXS_TLB_INVAL (1 << CBR_EXS_TLB_INVAL_BIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) #define CBR_EXS_EXCEPTION (1 << CBR_EXS_EXCEPTION_BIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) #define CBR_EXS_CB_INT_PENDING (1 << CBR_EXS_CB_INT_PENDING_BIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) * Exceptions are retried for the following cases. If any OTHER bits are set
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) * in ecause, the exception is not retryable.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) #define EXCEPTION_RETRY_BITS (CBE_CAUSE_EXECUTION_HW_ERROR | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) CBE_CAUSE_TLBHW_ERROR | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) CBE_CAUSE_RA_REQUEST_TIMEOUT | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) CBE_CAUSE_RA_RESPONSE_NON_FATAL | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) CBE_CAUSE_HA_RESPONSE_NON_FATAL | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) CBE_CAUSE_RA_RESPONSE_DATA_ERROR | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) CBE_CAUSE_HA_RESPONSE_DATA_ERROR \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) /* Message queue head structure */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) union gru_mesqhead {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) unsigned long val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) unsigned int head;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) unsigned int limit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) /* Generate the low word of a GRU instruction */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) static inline unsigned long
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) __opdword(unsigned char opcode, unsigned char exopc, unsigned char xtype,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) unsigned char iaa0, unsigned char iaa1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) unsigned long idef2, unsigned char ima)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) return (1 << GRU_CB_ICMD_SHFT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) ((unsigned long)CBS_ACTIVE << GRU_ISTATUS_SHFT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) (idef2<< GRU_IDEF2_SHFT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) (iaa0 << GRU_CB_IAA0_SHFT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) (iaa1 << GRU_CB_IAA1_SHFT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) (ima << GRU_CB_IMA_SHFT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) (xtype << GRU_CB_XTYPE_SHFT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) (opcode << GRU_CB_OPC_SHFT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) (exopc << GRU_CB_EXOPC_SHFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) * Architecture specific intrinsics
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) static inline void gru_flush_cache(void *p)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) __flush_cache(p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) * Store the lower 64 bits of the command including the "start" bit. Then
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) * start the instruction executing.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) static inline void gru_start_instruction(struct gru_instruction *ins, unsigned long op64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) gru_ordered_store_ulong(ins, op64);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) mb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) gru_flush_cache(ins);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) /* Convert "hints" to IMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) #define CB_IMA(h) ((h) | IMA_UNMAPPED)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) /* Convert data segment cache line index into TRI0 / TRI1 value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) #define GRU_DINDEX(i) ((i) * GRU_CACHE_LINE_BYTES)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) /* Inline functions for GRU instructions.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) * Note:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) * - nelem and stride are in elements
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) * - tri0/tri1 is in bytes for the beginning of the data segment.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) static inline void gru_vload_phys(void *cb, unsigned long gpa,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) unsigned int tri0, int iaa, unsigned long hints)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) struct gru_instruction *ins = (struct gru_instruction *)cb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) ins->baddr0 = (long)gpa | ((unsigned long)iaa << 62);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) ins->nelem = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) ins->op1_stride = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) gru_start_instruction(ins, __opdword(OP_VLOAD, 0, XTYPE_DW, iaa, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) (unsigned long)tri0, CB_IMA(hints)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) static inline void gru_vstore_phys(void *cb, unsigned long gpa,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) unsigned int tri0, int iaa, unsigned long hints)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) struct gru_instruction *ins = (struct gru_instruction *)cb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) ins->baddr0 = (long)gpa | ((unsigned long)iaa << 62);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) ins->nelem = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) ins->op1_stride = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) gru_start_instruction(ins, __opdword(OP_VSTORE, 0, XTYPE_DW, iaa, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) (unsigned long)tri0, CB_IMA(hints)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) static inline void gru_vload(void *cb, unsigned long mem_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) unsigned int tri0, unsigned char xtype, unsigned long nelem,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) unsigned long stride, unsigned long hints)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) struct gru_instruction *ins = (struct gru_instruction *)cb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) ins->baddr0 = (long)mem_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) ins->nelem = nelem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) ins->op1_stride = stride;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) gru_start_instruction(ins, __opdword(OP_VLOAD, 0, xtype, IAA_RAM, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) (unsigned long)tri0, CB_IMA(hints)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) static inline void gru_vstore(void *cb, unsigned long mem_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) unsigned int tri0, unsigned char xtype, unsigned long nelem,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) unsigned long stride, unsigned long hints)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) struct gru_instruction *ins = (void *)cb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) ins->baddr0 = (long)mem_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) ins->nelem = nelem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) ins->op1_stride = stride;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) gru_start_instruction(ins, __opdword(OP_VSTORE, 0, xtype, IAA_RAM, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) tri0, CB_IMA(hints)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) static inline void gru_ivload(void *cb, unsigned long mem_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) unsigned int tri0, unsigned int tri1, unsigned char xtype,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) unsigned long nelem, unsigned long hints)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) struct gru_instruction *ins = (void *)cb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) ins->baddr0 = (long)mem_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) ins->nelem = nelem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) ins->tri1_bufsize = tri1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) gru_start_instruction(ins, __opdword(OP_IVLOAD, 0, xtype, IAA_RAM, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) tri0, CB_IMA(hints)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) static inline void gru_ivstore(void *cb, unsigned long mem_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) unsigned int tri0, unsigned int tri1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) unsigned char xtype, unsigned long nelem, unsigned long hints)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) struct gru_instruction *ins = (void *)cb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) ins->baddr0 = (long)mem_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) ins->nelem = nelem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) ins->tri1_bufsize = tri1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) gru_start_instruction(ins, __opdword(OP_IVSTORE, 0, xtype, IAA_RAM, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) tri0, CB_IMA(hints)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) static inline void gru_vset(void *cb, unsigned long mem_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) unsigned long value, unsigned char xtype, unsigned long nelem,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) unsigned long stride, unsigned long hints)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) struct gru_instruction *ins = (void *)cb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) ins->baddr0 = (long)mem_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) ins->op2_value_baddr1 = value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) ins->nelem = nelem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) ins->op1_stride = stride;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) gru_start_instruction(ins, __opdword(OP_VSET, 0, xtype, IAA_RAM, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) 0, CB_IMA(hints)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) static inline void gru_ivset(void *cb, unsigned long mem_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) unsigned int tri1, unsigned long value, unsigned char xtype,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) unsigned long nelem, unsigned long hints)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) struct gru_instruction *ins = (void *)cb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) ins->baddr0 = (long)mem_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) ins->op2_value_baddr1 = value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) ins->nelem = nelem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) ins->tri1_bufsize = tri1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) gru_start_instruction(ins, __opdword(OP_IVSET, 0, xtype, IAA_RAM, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) 0, CB_IMA(hints)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) static inline void gru_vflush(void *cb, unsigned long mem_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) unsigned long nelem, unsigned char xtype, unsigned long stride,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) unsigned long hints)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) struct gru_instruction *ins = (void *)cb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) ins->baddr0 = (long)mem_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) ins->op1_stride = stride;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) ins->nelem = nelem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) gru_start_instruction(ins, __opdword(OP_VFLUSH, 0, xtype, IAA_RAM, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) 0, CB_IMA(hints)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) static inline void gru_nop(void *cb, int hints)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) struct gru_instruction *ins = (void *)cb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) gru_start_instruction(ins, __opdword(OP_NOP, 0, 0, 0, 0, 0, CB_IMA(hints)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) static inline void gru_bcopy(void *cb, const unsigned long src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) unsigned long dest,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) unsigned int tri0, unsigned int xtype, unsigned long nelem,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) unsigned int bufsize, unsigned long hints)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) struct gru_instruction *ins = (void *)cb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) ins->baddr0 = (long)src;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) ins->op2_value_baddr1 = (long)dest;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) ins->nelem = nelem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) ins->tri1_bufsize = bufsize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) gru_start_instruction(ins, __opdword(OP_BCOPY, 0, xtype, IAA_RAM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) IAA_RAM, tri0, CB_IMA(hints)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) static inline void gru_bstore(void *cb, const unsigned long src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) unsigned long dest, unsigned int tri0, unsigned int xtype,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) unsigned long nelem, unsigned long hints)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) struct gru_instruction *ins = (void *)cb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) ins->baddr0 = (long)src;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) ins->op2_value_baddr1 = (long)dest;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) ins->nelem = nelem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) gru_start_instruction(ins, __opdword(OP_BSTORE, 0, xtype, 0, IAA_RAM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) tri0, CB_IMA(hints)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) static inline void gru_gamir(void *cb, int exopc, unsigned long src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) unsigned int xtype, unsigned long hints)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) struct gru_instruction *ins = (void *)cb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) ins->baddr0 = (long)src;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) gru_start_instruction(ins, __opdword(OP_GAMIR, exopc, xtype, IAA_RAM, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) 0, CB_IMA(hints)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) static inline void gru_gamirr(void *cb, int exopc, unsigned long src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) unsigned int xtype, unsigned long hints)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) struct gru_instruction *ins = (void *)cb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) ins->baddr0 = (long)src;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) gru_start_instruction(ins, __opdword(OP_GAMIRR, exopc, xtype, IAA_RAM, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) 0, CB_IMA(hints)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) static inline void gru_gamer(void *cb, int exopc, unsigned long src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) unsigned int xtype,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) unsigned long operand1, unsigned long operand2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) unsigned long hints)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) struct gru_instruction *ins = (void *)cb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) ins->baddr0 = (long)src;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) ins->op1_stride = operand1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) ins->op2_value_baddr1 = operand2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) gru_start_instruction(ins, __opdword(OP_GAMER, exopc, xtype, IAA_RAM, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) 0, CB_IMA(hints)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) static inline void gru_gamerr(void *cb, int exopc, unsigned long src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) unsigned int xtype, unsigned long operand1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) unsigned long operand2, unsigned long hints)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) struct gru_instruction *ins = (void *)cb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) ins->baddr0 = (long)src;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) ins->op1_stride = operand1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) ins->op2_value_baddr1 = operand2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) gru_start_instruction(ins, __opdword(OP_GAMERR, exopc, xtype, IAA_RAM, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) 0, CB_IMA(hints)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) static inline void gru_gamxr(void *cb, unsigned long src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) unsigned int tri0, unsigned long hints)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) struct gru_instruction *ins = (void *)cb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) ins->baddr0 = (long)src;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) ins->nelem = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) gru_start_instruction(ins, __opdword(OP_GAMXR, EOP_XR_CSWAP, XTYPE_DW,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) IAA_RAM, 0, 0, CB_IMA(hints)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) static inline void gru_mesq(void *cb, unsigned long queue,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) unsigned long tri0, unsigned long nelem,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) unsigned long hints)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) struct gru_instruction *ins = (void *)cb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) ins->baddr0 = (long)queue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) ins->nelem = nelem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) gru_start_instruction(ins, __opdword(OP_MESQ, 0, XTYPE_CL, IAA_RAM, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) tri0, CB_IMA(hints)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) static inline unsigned long gru_get_amo_value(void *cb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) struct gru_instruction *ins = (void *)cb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) return ins->avalue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) static inline int gru_get_amo_value_head(void *cb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) struct gru_instruction *ins = (void *)cb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) return ins->avalue & 0xffffffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) static inline int gru_get_amo_value_limit(void *cb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) struct gru_instruction *ins = (void *)cb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) return ins->avalue >> 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) static inline union gru_mesqhead gru_mesq_head(int head, int limit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) union gru_mesqhead mqh;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) mqh.head = head;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) mqh.limit = limit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) return mqh;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) * Get struct control_block_extended_exc_detail for CB.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) extern int gru_get_cb_exception_detail(void *cb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) struct control_block_extended_exc_detail *excdet);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) #define GRU_EXC_STR_SIZE 256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) * Control block definition for checking status
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) struct gru_control_block_status {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) unsigned int icmd :1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) unsigned int ima :3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) unsigned int reserved0 :4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) unsigned int unused1 :24;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) unsigned int unused2 :24;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) unsigned int istatus :2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) unsigned int isubstatus :4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) unsigned int unused3 :2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) /* Get CB status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) static inline int gru_get_cb_status(void *cb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) struct gru_control_block_status *cbs = (void *)cb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) return cbs->istatus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) /* Get CB message queue substatus */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) static inline int gru_get_cb_message_queue_substatus(void *cb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) struct gru_control_block_status *cbs = (void *)cb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) return cbs->isubstatus & CBSS_MSG_QUEUE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) /* Get CB substatus */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) static inline int gru_get_cb_substatus(void *cb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) struct gru_control_block_status *cbs = (void *)cb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) return cbs->isubstatus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) * User interface to check an instruction status. UPM and exceptions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) * are handled automatically. However, this function does NOT wait
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) * for an active instruction to complete.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) static inline int gru_check_status(void *cb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) struct gru_control_block_status *cbs = (void *)cb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) ret = cbs->istatus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) if (ret != CBS_ACTIVE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) ret = gru_check_status_proc(cb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) * User interface (via inline function) to wait for an instruction
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) * to complete. Completion status (IDLE or EXCEPTION is returned
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) * to the user. Exception due to hardware errors are automatically
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) * retried before returning an exception.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) static inline int gru_wait(void *cb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) return gru_wait_proc(cb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) * Wait for CB to complete. Aborts program if error. (Note: error does NOT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) * mean TLB mis - only fatal errors such as memory parity error or user
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) * bugs will cause termination.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) static inline void gru_wait_abort(void *cb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) gru_wait_abort_proc(cb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) * Get a pointer to the start of a gseg
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) * p - Any valid pointer within the gseg
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) static inline void *gru_get_gseg_pointer (void *p)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) return (void *)((unsigned long)p & ~(GRU_GSEG_PAGESIZE - 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) * Get a pointer to a control block
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) * gseg - GSeg address returned from gru_get_thread_gru_segment()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) * index - index of desired CB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) static inline void *gru_get_cb_pointer(void *gseg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) int index)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) return gseg + GRU_CB_BASE + index * GRU_HANDLE_STRIDE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) * Get a pointer to a cacheline in the data segment portion of a GSeg
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) * gseg - GSeg address returned from gru_get_thread_gru_segment()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) * index - index of desired cache line
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) static inline void *gru_get_data_pointer(void *gseg, int index)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) return gseg + GRU_DS_BASE + index * GRU_CACHE_LINE_BYTES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) * Convert a vaddr into the tri index within the GSEG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) * vaddr - virtual address of within gseg
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) static inline int gru_get_tri(void *vaddr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) return ((unsigned long)vaddr & (GRU_GSEG_PAGESIZE - 1)) - GRU_DS_BASE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) #endif /* __GRU_INSTRUCTIONS_H__ */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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