^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * Driver for Rockchip Smart Card Reader Controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (C) 2012-2016 ROCKCHIP, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * This software is licensed under the terms of the GNU General Public
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * License version 2, as published by the Free Software Foundation, and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * may be copied, distributed, and modified under those terms.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * This program is distributed in the hope that it will be useful,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * but WITHOUT ANY WARRANTY; without even the implied warranty of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * GNU General Public License for more details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #ifndef __RK_SCR_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define __RK_SCR_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) /* CTRL1 bit fields */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define INVLEV BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define INVORD BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define PECH2FIFO BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define CLKSTOP BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define CLKSTOPVAL BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define TXEN BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define RXEN BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define TS2FIFO BIT(10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define T0T1 BIT(11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define ATRSTFLUSH BIT(12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define TCKEN BIT(13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define GINTEN BIT(15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) /* CTRL2 bit fields */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define WARMRST BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define ACT BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define DEACT BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define VCC18 BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define VCC33 BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define VCC50 BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) /* SCPADS bit fields */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define DIRACCPADS BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define DSCIO BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define DSCCLK BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define DSCRST BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define DSCVCC BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define AUTOADEAVPP BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define DSCVPPEN BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define DSCVPPP BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define DSCFCB BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define SCPRESENT BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) /* INTEN1 & INTSTAT1 bit fields */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define TXFIDONE BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define TXFIEMPTY BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define RXFIFULL BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define CLKSTOPRUN BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define TXDONE BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define RXDONE BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define TXPERR BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define RXPERR BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define C2CFULL BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define RXTHRESHOLD BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define ATRFAIL BIT(10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define ATRDONE BIT(11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define SCREM BIT(12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define SCINS BIT(13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define SCACT BIT(14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define SCDEACT BIT(15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) /* INTEN2 & INTSTAT2 bit fields */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define TXTHRESHOLD BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define TCLKERR BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) /* FIFOCTRL bit fields */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define FC_TXFIEMPTY BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define FC_TXFIFULL BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define FC_TXFIFLUSH BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define FC_RXFIEMPTY BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define FC_RXFIFULL BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define FC_RXFIFLUSH BIT(10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) /* FIFO_DEPTH must >= 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define FIFO_DEPTH 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define MAX_RXTHR (3 * FIFO_DEPTH / 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define MAX_TXTHR (256) /* at least, one less than FIFO_DEPTH */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define RK_SCR_NUM (2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define SMC_ATR_MAX_LENGTH (512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define SMC_ATR_MIN_LENGTH (2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define SMC_SUCCESSFUL (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define SMC_ERROR_CARD_NOT_INSERT BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define SMC_ERROR_NO_ANSWER BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define SMC_ERROR_TX_ERR BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define SMC_ERROR_RX_ERR BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define SMC_ERROR_CONFLICT_ERR BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define SMC_ERROR_WRITE_FULL_RECV_FIFO_ERR BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define SMC_ERROR_BWT_ERR BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define SMC_ERROR_CWT_ERR BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define SMC_ERROR_BAD_PARAMETER BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define SMC_ERROR_ATR_ERR BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define SMC_ERROR_NO_MEMERY BIT(10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define SMC_ERROR_TIMEOUT BIT(11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) SC_DRV_INT_CARDOUT = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) SC_DRV_INT_CARDIN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) /* card convention */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) SC_CONV_DIRECT = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) SC_CONV_INVERSE = 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) SC_CARD_INDEX_0 = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) SC_CARD_INDEX_1 = 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) /* card protocol */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) SC_PROTOCOL_INVALID = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) SC_PROTOCOL_T0 = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) SC_PROTOCOL_T1 = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) SC_PROTOCOL_T14 = 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) /* enumerated constants */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) enum status_code_e {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) SUCCESSFUL = 0, /* successful completion */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) TASK_EXITTED = 1, /* returned from a thread */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) MP_NOT_CONFIGURED = 2, /* multiprocessing not configured */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) INVALID_NAME = 3, /* invalid object name */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) INVALID_ID = 4, /* invalid object id */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) TOO_MANY = 5, /* too many */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) TIMEOUT = 6, /* timed out waiting */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) OBJECT_WAS_DELETED = 7, /* object deleted while waiting */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) INVALID_SIZE = 8, /* specified size was invalid */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) INVALID_ADDRESS = 9, /* address specified is invalid */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) INVALID_NUMBER = 10, /* number was invalid */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) NOT_DEFINED = 11, /* item has not been initialized */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) RESOURCE_IN_USE = 12, /* resources still outstanding */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) UNSATISFIED = 13, /* request not satisfied */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) INCORRECT_STATE = 14, /* thread is in wrong state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) ALREADY_SUSPENDED = 15, /* thread already in state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) ILLEGAL_ON_SELF = 16, /* illegal on calling thread */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) ILLEGAL_ON_REMOTE_OBJECT = 17, /* illegal for remote object */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) CALLED_FROM_ISR = 18, /* called from wrong environment */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) INVALID_PRIORITY = 19, /* invalid thread priority */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) INVALID_CLOCK = 20, /* invalid date/time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) INVALID_NODE = 21, /* invalid node id */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) NOT_CONFIGURED = 22, /* directive not configured */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) NOT_OWNER_OF_RESOURCE = 23, /* not owner of resource */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) NOT_IMPLEMENTED = 24, /* directive not implemented */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) INTERNAL_ERROR = 25, /* inconsistency detected */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) NO_MEMORY = 26, /* could not get enough memory */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) IO_ERROR = 27, /* driver IO error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) PROXY_BLOCKING = 28 /* internal error only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) struct scr_reg_t {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) unsigned int CTRL1; /* Control Reg 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) unsigned int CTRL2; /* Control Reg 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) unsigned int SCPADS; /* Direct access to Smart Card pads*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) unsigned int INTEN1; /* Interrupt Enable Reg 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) unsigned int INTSTAT1; /* Interrupt Status Reg 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) unsigned int FIFOCTRL; /* FIFO control register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) unsigned int LGCYCNT; /* Legacy TX & RX FIFO Counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) unsigned int RXFIFOTH; /* RXFIFO threshold */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) unsigned int REPEAT; /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) * number of repeating after
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) * unsuccessful transaction
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) unsigned int CGSCDIV; /* SmartCard clock divisor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) unsigned int CGBITDIV; /* Bit clock divisor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) unsigned int SCGT; /* SmartCard GuardTime */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) unsigned int ADEATIME; /* Activation/deactivation time (cc)*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) unsigned int LOWRSTTIME; /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) * Duration of low state during
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) * Smart Card reset sequence
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) unsigned int ATRSTARTLIMIT; /* ATR start limit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) unsigned int C2CLIM; /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) * leading edge to leading edge of two
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) * consecutive characters delay limit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) unsigned int INTEN2; /* Interrupt Enable Reg 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) unsigned int INTSTAT2; /* Interrupt Status R */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) unsigned int TXFIFOTH; /* TXFIFO threshold */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) unsigned int TXFIFOCNT; /* TXFIFO counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) unsigned int RXFIFOCNT; /* RXFIFO counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) unsigned int CGBITTUNE; /* Bit tune register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) unsigned int reserved[0x200 / 4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) unsigned int FIFODATA; /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) * FIFODATA space start
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) * - RX FIFO and TX FIFO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) enum hal_scr_id_e {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) HAL_SCR_ID0 = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) HAL_SCR_ID1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) HAL_SCR_ID_MAX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) enum hal_scr_clock_stop_mode_e {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) /* Continuous clock mode, the autostop is disabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) HAL_SCR_CLOCK_NO_STOP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) /* Automatic clock stop mode, stopped at low-level */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) HAL_SCR_CLOCK_STOP_L,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) /* Automatic clock stop mode, stopped at high-level */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) HAL_SCR_CLOCK_STOP_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) enum hal_scr_etu_duration_e {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) /* F and D to default value F=372, D=1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) HAL_SCR_ETU_F_372_AND_D_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) /* F=512 and D=8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) HAL_SCR_ETU_F_512_AND_D_8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) /* F=512 and D=4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) HAL_SCR_ETU_F_512_AND_D_4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) struct hal_scr_irq_status_t {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) /* When the reset time-outs. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) unsigned char reset_timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) /* When a parity error occurs. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) unsigned char parity_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) /* When a bad ts character is received. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) unsigned char bad_ts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) /* When the auto-reset is successful. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) unsigned char atr_success;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) /* When a rx transfer has been finished */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) unsigned char rx_success;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) /* When an auto-reset has been started. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) unsigned char atr_start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) /* When a work waiting time factor time-outs. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) unsigned char wwt_timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) * When the number of received character exceeds the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) * number of awaited bytes:1; (set in the SCI Rx counter register)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) unsigned char extra_rx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) /*check card is in or out*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) enum hal_scr_detect_status_e {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) SMC_DRV_INT_CARDOUT = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) SMC_DRV_INT_CARDIN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) enum hal_scr_irq_cause_e {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) HAL_SCR_RESET_TIMEOUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) HAL_SCR_PARITY_ERROR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) HAL_SCR_BAD_TS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) HAL_SCR_ATR_SUCCESS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) HAL_SCR_RX_SUCCESS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) HAL_SCR_WWT_TIMEOUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) HAL_SCR_EXTRA_RX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) HAL_SCR_IRQ_INVALID = 0x0fffffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) enum hal_scr_voltage_e {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) /* 5V */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) HAL_SCR_VOLTAGE_CLASS_A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) /* 3V */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) HAL_SCR_VOLTAGE_CLASS_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) /* 1.8V */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) HAL_SCR_VOLTAGE_CLASS_C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) /* 0V */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) HAL_SCR_VOLTAGE_NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) /* card protocol */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) SMC_PROTOCOL_INVALID = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) SMC_PROTOCOL_T0 = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) SMC_PROTOCOL_T1 = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) SMC_PROTOCOL_T14 = 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) /* card convention */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) SMC_CONV_DIRECT = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) SMC_CONV_INVERSE = 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) /*card index*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) SMC_CARD_INDEX_0 = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) SMC_CARD_INDEX_1 = 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) typedef void (*hal_scr_irq_handler_t) (enum hal_scr_irq_cause_e);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) struct scr_chip_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) struct scr_reg_t *reg_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) const char *clk_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) struct rk_scr {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) const struct scr_chip_info *hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) hal_scr_irq_handler_t user_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) struct hal_scr_irq_status_t user_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) bool is_open;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) bool is_active;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) bool in_process;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) unsigned char *rx_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) unsigned int rx_expected;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) unsigned int rx_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) const unsigned char *tx_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) unsigned int tx_expected;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) unsigned int tx_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) unsigned int F;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) unsigned int D;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) struct notifier_block freq_changed_notifier;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) #endif /* __RK_SCR_H__ */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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