^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * Driver for Rockchip Smart Card Reader Controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (C) 2012-2016 ROCKCHIP, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * This software is licensed under the terms of the GNU General Public
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * License version 2, as published by the Free Software Foundation, and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * may be copied, distributed, and modified under those terms.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * This program is distributed in the hope that it will be useful,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * but WITHOUT ANY WARRANTY; without even the implied warranty of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * GNU General Public License for more details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/list.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/time.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <linux/kobject.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <linux/sysfs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <linux/kthread.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #include "rk_scr.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #undef DEBUG_RK_SCR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define DEBUG_RK_SCR 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #if DEBUG_RK_SCR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define DAL_LOGV(x...) pr_info("RK_SCR: "x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define DAL_LOGV(x...) do { } while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define SMC_DEFAULT_TIMEOUT 2000 /*ms*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define SMC_RECEIVE_BUF_LEN (64 * 1024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) struct rk_scr_device {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) struct clk *clk_scr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) void __iomem *regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) struct scr_chip_info chip_info[RK_SCR_NUM];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) struct rk_scr scr[RK_SCR_NUM];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) struct completion is_done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) struct mutex scr_mutex; /* mutex for scr operation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) unsigned char *recv_buffer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) unsigned recv_data_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) unsigned recv_data_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) unsigned char atr_buffer[SMC_ATR_MAX_LENGTH];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) unsigned char atr_length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) static struct rk_scr_device *rk_scr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) static struct rk_scr *to_rk_scr(int id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) if (id < RK_SCR_NUM)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) return &rk_scr->scr[id];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) static struct rk_scr *to_opened_rk_scr(int id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) struct rk_scr *scr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) scr = to_rk_scr(id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) if (scr && scr->is_open)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) return scr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) static void rk_scr_deactive(struct rk_scr *scr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) struct scr_reg_t *scr_reg = scr->hw->reg_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) DAL_LOGV("Deactive card\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) scr_reg->CTRL2 |= DEACT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) scr_reg->CTRL1 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) scr->is_active = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) static void rk_scr_set_clk(struct rk_scr *scr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) struct scr_reg_t *scr_reg = scr->hw->reg_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) unsigned int freq_mhz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) freq_mhz = clk_get_rate(scr->clk) / 1000 / 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) DAL_LOGV("freq_mhz = %d\n", freq_mhz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) scr_reg->CGSCDIV = ((2 * freq_mhz / 13 - 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) + (freq_mhz / 8 - 1) + 1) / 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) DAL_LOGV("scr_reg->CGSCDIV = %d\n", scr_reg->CGSCDIV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) static void rk_scr_set_work_waitingtime(struct rk_scr *scr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) unsigned char wi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) struct scr_reg_t *scr_reg = scr->hw->reg_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) unsigned int wt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) DAL_LOGV("WI: %d\n", wi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) wt = 960 * wi * scr->D;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) scr_reg->C2CLIM = (wt > 0x0FFFF) ? 0x0FFFF : wt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) static void rk_scr_set_etu_duration(struct rk_scr *scr, unsigned int F,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) unsigned int D)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) struct scr_reg_t *scr_reg = scr->hw->reg_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) DAL_LOGV("Set Etu F: %d D: %d\n", F, D);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) scr->F = F;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) scr->D = D;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) scr_reg->CGBITDIV = (scr_reg->CGSCDIV + 1) * (F / D) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) DAL_LOGV("scr_reg->CGBITDIV = %d\n", scr_reg->CGBITDIV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) scr_reg->CGBITTUNE = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) rk_scr_set_work_waitingtime(scr, 10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) static void rk_scr_set_scr_voltage(struct rk_scr *scr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) enum hal_scr_voltage_e level)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) struct scr_reg_t *scr_reg = scr->hw->reg_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) scr_reg->CTRL2 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) switch (level) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) case HAL_SCR_VOLTAGE_CLASS_A:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) scr_reg->CTRL2 |= VCC50;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) case HAL_SCR_VOLTAGE_CLASS_B:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) scr_reg->CTRL2 |= VCC33;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) case HAL_SCR_VOLTAGE_CLASS_C:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) scr_reg->CTRL2 |= VCC18;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) case HAL_SCR_VOLTAGE_NULL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) static void rk_scr_powerdown(struct rk_scr *scr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) rk_scr_set_scr_voltage(scr, HAL_SCR_VOLTAGE_NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) static void rk_scr_set_clockstop_mode(struct rk_scr *scr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) enum hal_scr_clock_stop_mode_e mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) struct scr_reg_t *scr_reg = scr->hw->reg_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) if (mode == HAL_SCR_CLOCK_STOP_L)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) scr_reg->CTRL1 &= ~CLKSTOPVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) else if (mode == HAL_SCR_CLOCK_STOP_H)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) scr_reg->CTRL1 |= CLKSTOPVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) static void rk_scr_clock_start(struct rk_scr *scr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) struct scr_reg_t *scr_reg = scr->hw->reg_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) int time_out = 10000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #ifdef SCR_DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) scr_reg->INTEN1 = CLKSTOPRUN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) scr_reg->CTRL1 &= ~CLKSTOP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #ifdef SCR_DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) if (scr_reg->CTRL1 & CLKSTOP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) DAL_LOGV("Before clock is Stopped\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) DAL_LOGV("Before clock is running\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) while ((scr_reg->CTRL1 & CLKSTOP) && (time_out-- > 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) usleep_range(100, 110);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) static void rk_scr_clock_stop(struct rk_scr *scr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) struct scr_reg_t *scr_reg = scr->hw->reg_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) int time_out = 10000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #ifdef SCR_DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) scr_reg->INTEN1 = CLKSTOPRUN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) scr_reg->CTRL1 |= CLKSTOP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) DAL_LOGV("Stop Clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) if (scr->is_active) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) while ((!(scr_reg->CTRL1 & CLKSTOP)) && (time_out-- > 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) usleep_range(100, 110);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) static void rk_scr_reset(struct rk_scr *scr, unsigned char *rx_buffer)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) struct scr_reg_t *scr_reg = scr->hw->reg_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) if (!rx_buffer)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) DAL_LOGV("_scr_reset: invalid argument\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) * must disable all SCR interrupts.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) * It will protect the global data.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) scr_reg->INTEN1 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) scr->rx_buf = rx_buffer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) scr->rx_expected = 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) scr->rx_cnt = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) * must in the critical section. If we don't, when we have written CTRL2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) * before enable expected interrupts, other interrupts occurred,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) * we may miss expected interrupts.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) if (scr->is_active) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) DAL_LOGV("Warm Reset\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) scr_reg->CTRL2 |= WARMRST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) DAL_LOGV("Active & Cold Reset\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) scr->is_active = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) scr_reg->CTRL1 = TXEN | RXEN | TS2FIFO | ATRSTFLUSH | GINTEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) scr_reg->CTRL2 |= ACT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) * If we enable the interrupts before write CTRL2, we may get
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) * expected interrupts which belong to the last transfer not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) * for the reset.This may damage the global data.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) scr_reg->RXFIFOTH = MAX_RXTHR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) scr_reg->TXFIFOTH = MAX_TXTHR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) scr_reg->INTEN1 = RXTHRESHOLD | RXFIFULL | RXPERR |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) C2CFULL | ATRFAIL | ATRDONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) DAL_LOGV("Start Rx\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) static void rk_scr_write_bytes(struct rk_scr *scr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) struct scr_reg_t *scr_reg = scr->hw->reg_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) int count = FIFO_DEPTH - scr_reg->TXFIFOCNT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) int remainder = scr->tx_expected - scr->tx_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) int i = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) if (remainder < count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) count = remainder;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) while (i++ < count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) scr_reg->FIFODATA = scr->tx_buf[scr->tx_cnt++];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) static void rk_scr_read_bytes(struct rk_scr *scr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) struct scr_reg_t *scr_reg = scr->hw->reg_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) int count = scr_reg->RXFIFOCNT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) int remainder = scr->rx_expected - scr->rx_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) int i = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) if (remainder < count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) count = remainder;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) while (i++ < count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) scr->rx_buf[scr->rx_cnt++] = (unsigned char)scr_reg->FIFODATA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) static irqreturn_t rk_scr_irqhandler(int irq, void *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) struct rk_scr *scr = (struct rk_scr *)priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) struct scr_reg_t *scr_reg = scr->hw->reg_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) enum hal_scr_irq_cause_e user_cause = HAL_SCR_IRQ_INVALID;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) unsigned int stat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) stat = (unsigned int)scr_reg->INTSTAT1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) if (!stat)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) if (stat & TXFIEMPTY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) scr_reg->INTSTAT1 |= TXFIEMPTY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) /* during this period, TXFIEMPTY may occurred. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) rk_scr_write_bytes(scr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) if (scr->tx_cnt == scr->tx_expected) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) scr_reg->INTEN1 &= ~TXFIEMPTY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) scr_reg->INTSTAT1 |= TXFIEMPTY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) #ifdef SCR_DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) else if (stat & CLKSTOPRUN) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) scr_reg->INTSTAT1 |= CLKSTOPRUN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) if (scr_reg->CTRL1 & CLKSTOP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) DAL_LOGV("Clock is stopped\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) DAL_LOGV("Clock is started\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) else if ((stat & RXTHRESHOLD) || (stat & RXFIFULL)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) unsigned int threshold;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) scr_reg->INTEN1 &= ~RXTHRESHOLD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) scr_reg->INTSTAT1 |= RXTHRESHOLD | RXFIFULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) if (scr->rx_cnt < scr->rx_expected) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) rk_scr_read_bytes(scr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) if (scr->rx_cnt < scr->rx_expected) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) unsigned int remainder =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) scr->rx_expected - scr->rx_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) threshold = (remainder < MAX_RXTHR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) ? remainder : MAX_RXTHR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) scr_reg->INTEN1 &= ~C2CFULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) threshold = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) if (scr->user_mask.rx_success)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) user_cause = HAL_SCR_RX_SUCCESS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) threshold = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) scr->rx_buf[scr->rx_cnt++] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) (unsigned char)scr_reg->FIFODATA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) if (scr->user_mask.extra_rx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) user_cause = HAL_SCR_EXTRA_RX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) scr_reg->INTEN1 |= RXTHRESHOLD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) * when RX FIFO now is FULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) * that will not generate RXTHRESHOLD interrupt.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) * But it will generate RXFIFULL interrupt.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) scr_reg->RXFIFOTH = FIFO_DEPTH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) scr_reg->RXFIFOTH = threshold;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) } else if (stat & ATRDONE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) DAL_LOGV("ATR Done\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) scr_reg->INTSTAT1 |= ATRDONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) scr_reg->INTEN1 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) rk_scr_read_bytes(scr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) if (scr->user_mask.atr_success)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) user_cause = HAL_SCR_ATR_SUCCESS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) } else if (stat & ATRFAIL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) DAL_LOGV("ATR Fail\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) scr_reg->INTSTAT1 |= ATRFAIL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) scr_reg->INTEN1 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) if (scr->user_mask.reset_timeout)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) user_cause = HAL_SCR_RESET_TIMEOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) } else if (stat & TXPERR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) DAL_LOGV("TXPERR\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) scr_reg->INTSTAT1 |= TXPERR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) scr_reg->INTEN1 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) if (scr->user_mask.parity_error)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) user_cause = HAL_SCR_PARITY_ERROR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) } else if (stat & RXPERR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) DAL_LOGV("RXPERR\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) scr_reg->INTSTAT1 |= RXPERR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) scr_reg->INTEN1 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) rk_scr_read_bytes(scr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) if (scr->user_mask.parity_error)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) user_cause = HAL_SCR_PARITY_ERROR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) } else if (stat & C2CFULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) DAL_LOGV("Timeout\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) scr_reg->INTSTAT1 |= C2CFULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) scr_reg->INTEN1 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) rk_scr_read_bytes(scr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) if (scr->user_mask.wwt_timeout)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) user_cause = HAL_SCR_WWT_TIMEOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) if (user_cause != HAL_SCR_IRQ_INVALID) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) scr->in_process = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) if (scr->user_handler)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) scr->user_handler(user_cause);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) static void _rk_scr_init(struct rk_scr *scr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) struct scr_reg_t *scr_reg = scr->hw->reg_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) rk_scr_deactive(scr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) rk_scr_set_clk(scr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) rk_scr_set_etu_duration(scr, 372, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) /* TXREPEAT = 3 & RXREPEAT = 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) scr_reg->REPEAT = 0x33;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) * Character LeadEdge to Character LeadEdge minimum waiting time
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) * in terms of ETUs. (GT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) scr_reg->SCGT = 12;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) * Character LeadEdge to Character LeadEdge maximum waiting time
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) * in terms of ETUs. (WT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) scr_reg->C2CLIM = 9600;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) * If no Vpp is necessary, the activation and deactivation part of Vpp
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) * can be omitted by clearing the AUTOADEAVPP bit in SCPADS register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) scr_reg->SCPADS = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) * Activation / deactivation step time
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) * in terms of SmartCard Clock Cycles
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) scr_reg->ADEATIME = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) * Duration of low state during Smart Card reset sequence
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) * in terms of smart card clock cycles
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) * require >
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) scr_reg->LOWRSTTIME = 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) * ATR start limit - in terms of SmartCard Clock Cycles
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) * require 400 ~ 40000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) scr_reg->ATRSTARTLIMIT = 40000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) /* enable the detect interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) scr_reg->INTEN1 = SCINS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) scr_reg->INTEN2 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) scr_reg->INTSTAT1 = 0xffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) scr_reg->INTSTAT2 = 0xffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) scr_reg->FIFOCTRL = FC_TXFIFLUSH | FC_RXFIFLUSH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) scr_reg->TXFIFOTH = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) scr_reg->RXFIFOTH = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) scr_reg->CTRL1 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) scr_reg->CTRL2 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) static void _rk_scr_deinit(struct rk_scr *scr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) struct scr_reg_t *scr_reg = scr->hw->reg_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) /* disable all interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) scr_reg->INTEN1 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) scr_reg->INTEN2 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) rk_scr_deactive(scr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) rk_scr_powerdown(scr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) int rk_scr_freqchanged_notifiy(struct notifier_block *nb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) unsigned long action, void *data, int len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) int idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) struct rk_scr *scr = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) /*alter by xieshufa not sure*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) struct clk_notifier_data *msg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) switch (action) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) /*case ABORT_RATE_CHANGE:*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) case POST_RATE_CHANGE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) msg = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) for (idx = 0; idx < RK_SCR_NUM; idx++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) struct rk_scr *p = to_rk_scr(idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) if (msg->clk == p->clk) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) scr = p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) if (scr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) rk_scr_set_clk(scr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) rk_scr_set_etu_duration(scr, scr->F, scr->D);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) static int rk_scr_open(int id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) struct rk_scr_device *rk_scr_dev = rk_scr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) struct rk_scr *scr = to_rk_scr(id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) struct hal_scr_irq_status_t
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) default_scr_user_mask = {1, 1, 1, 1, 1, 1, 1, 1};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) int result = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) if (!scr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) rk_scr_dev->chip_info[id].reg_base = rk_scr_dev->regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) rk_scr_dev->chip_info[id].irq = rk_scr_dev->irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) scr->hw = &rk_scr_dev->chip_info[id];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) scr->clk = rk_scr_dev->clk_scr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) result = clk_prepare_enable(scr->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) DAL_LOGV("scr clk_enable result = %d\n", result);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) (&scr->freq_changed_notifier)->priority = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) clk_notifier_register(scr->clk, &scr->freq_changed_notifier);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) scr->user_mask = default_scr_user_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) _rk_scr_init(scr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) scr->is_open = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) static void rk_scr_close(int id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) struct rk_scr *scr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) scr = to_opened_rk_scr(id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) if (!scr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) scr->is_open = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) _rk_scr_deinit(scr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) if (scr->clk) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) clk_disable(scr->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) clk_notifier_unregister(scr->clk, &scr->freq_changed_notifier);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) static int rk_scr_read(int id, unsigned int n_rx_byte,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) unsigned char *p_rx_byte)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) struct rk_scr *scr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) struct scr_reg_t *scr_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) unsigned int inten1 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) scr = to_opened_rk_scr(id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) if (!scr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) if (!((n_rx_byte != 0) && (p_rx_byte))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) DAL_LOGV("rk_scr_read: invalid argument\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) scr_reg = scr->hw->reg_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) * must disable all SCR interrupts.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) * It will protect the global data.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) scr_reg->INTEN1 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) scr->rx_buf = p_rx_byte;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) scr->rx_expected = n_rx_byte;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) scr->rx_cnt = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) scr_reg->RXFIFOTH = (scr->rx_expected < MAX_RXTHR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) ? scr->rx_expected : MAX_RXTHR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) inten1 = RXTHRESHOLD | RXFIFULL | RXPERR | C2CFULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) scr_reg->INTEN1 = inten1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) static int rk_scr_write(int id, unsigned int n_tx_byte,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) const unsigned char *p_tx_byte)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) struct rk_scr *scr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) struct scr_reg_t *scr_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) unsigned int inten1 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) unsigned timeout_count = 1500;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) unsigned long udelay = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) timeout_count = 1500;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) udelay = msecs_to_jiffies(timeout_count) + jiffies;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) scr = to_opened_rk_scr(id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) if (!scr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) if (!((n_tx_byte != 0) && (p_tx_byte))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) DAL_LOGV("rk_scr_write: invalid argument\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) scr_reg = scr->hw->reg_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) * must disable all SCR interrupts.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) * It will protect the global data.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) scr_reg->INTEN1 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) scr->tx_buf = p_tx_byte;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) scr->tx_expected = n_tx_byte;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) scr->tx_cnt = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) scr_reg->FIFOCTRL = FC_TXFIFLUSH | FC_RXFIFLUSH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) /* send data until FIFO full or send over. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) while ((scr->tx_cnt < scr->tx_expected) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) (time_before(jiffies, udelay))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) if (!(scr_reg->FIFOCTRL & FC_TXFIFULL))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) scr_reg->FIFODATA = scr->tx_buf[scr->tx_cnt++];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) /* need enable tx interrupt to continue */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) if (scr->tx_cnt < scr->tx_expected) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) pr_err("\n@rk_scr_write: FC_TXFIFULL@\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) inten1 |= TXFIEMPTY | TXPERR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) scr_reg->INTEN1 = inten1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) int rk_scr_transfer(int id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) unsigned int n_tx_byte, unsigned char *p_tx_byte,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) unsigned int n_rx_byte, unsigned char *p_rx_byte)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) struct rk_scr *scr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) struct scr_reg_t *scr_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) unsigned int inten1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) scr = to_opened_rk_scr(id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) if (!scr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) if (!((n_tx_byte != 0) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) (p_tx_byte) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) (n_rx_byte != 0) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) (p_rx_byte))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) DAL_LOGV("rk_scr_transfer: invalid argument\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) if (scr->in_process)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) scr->in_process = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) scr_reg = scr->hw->reg_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) * must disable all SCR interrupts.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) * It will protect the global data.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) scr_reg->INTEN1 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) rk_scr_clock_start(scr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) scr->tx_buf = p_tx_byte;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) scr->tx_expected = n_tx_byte;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) scr->tx_cnt = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) scr->rx_buf = p_rx_byte;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) scr->rx_expected = n_rx_byte;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) scr->rx_cnt = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) scr_reg->FIFOCTRL = FC_TXFIFLUSH | FC_RXFIFLUSH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) scr_reg->RXFIFOTH = (scr->rx_expected < MAX_RXTHR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) ? scr->rx_expected : MAX_RXTHR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) scr_reg->TXFIFOTH = MAX_TXTHR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) inten1 = RXTHRESHOLD | RXFIFULL | RXPERR | C2CFULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) /* send data until FIFO full or send over. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) while ((scr->tx_cnt < scr->tx_expected) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) !(scr_reg->FIFOCTRL & FC_TXFIFULL)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) scr_reg->FIFODATA = scr->tx_buf[scr->tx_cnt++];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) /* need enable tx interrupt to continue */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) if (scr->tx_cnt < scr->tx_expected)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) inten1 |= TXFIEMPTY | TXPERR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) scr_reg->INTEN1 = inten1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) static enum hal_scr_id_e g_curr_sur_id = HAL_SCR_ID0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) void _scr_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) enum hal_scr_id_e id = g_curr_sur_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) rk_scr_open(id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) void _scr_close(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) enum hal_scr_id_e id = g_curr_sur_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) rk_scr_close(id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) bool _scr_set_voltage(enum hal_scr_voltage_e level)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) enum hal_scr_id_e id = g_curr_sur_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) struct rk_scr *scr = to_opened_rk_scr(id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) if (scr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) rk_scr_set_scr_voltage(scr, level);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) void _scr_reset(unsigned char *rx_bytes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) enum hal_scr_id_e id = g_curr_sur_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) struct rk_scr *scr = to_opened_rk_scr(id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) if (scr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) rk_scr_reset(scr, rx_bytes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) void _scr_set_etu_duration(unsigned int F, unsigned int D)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) enum hal_scr_id_e id = g_curr_sur_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) struct rk_scr *scr = to_opened_rk_scr(id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) if (scr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) rk_scr_set_etu_duration(scr, F, D);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) void _scr_set_clock_stopmode(enum hal_scr_clock_stop_mode_e mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) enum hal_scr_id_e id = g_curr_sur_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) struct rk_scr *scr = to_opened_rk_scr(id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) if (scr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) rk_scr_set_clockstop_mode(scr, mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) void _scr_set_work_waitingtime(unsigned char wi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) enum hal_scr_id_e id = g_curr_sur_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) struct rk_scr *scr = to_opened_rk_scr(id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) if (scr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) rk_scr_set_work_waitingtime(scr, wi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) void _scr_clock_start(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) enum hal_scr_id_e id = g_curr_sur_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) struct rk_scr *scr = to_opened_rk_scr(id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) if (scr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) rk_scr_clock_start(scr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) void _scr_clock_stop(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) enum hal_scr_id_e id = g_curr_sur_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) struct rk_scr *scr = to_opened_rk_scr(id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) if (scr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) rk_scr_clock_stop(scr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) bool _scr_tx_byte(unsigned int n_tx_byte,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) const unsigned char *p_tx_byte)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) enum hal_scr_id_e id = g_curr_sur_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) ret = rk_scr_write(id, n_tx_byte, p_tx_byte);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) bool _scr_rx_byte(unsigned int n_rx_byte, unsigned char *p_rx_byte)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) enum hal_scr_id_e id = g_curr_sur_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) ret = rk_scr_read(id, n_rx_byte, p_rx_byte);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) bool _scr_tx_byte_rx_byte(unsigned int n_tx_byte,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) unsigned char *p_tx_byte,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) unsigned int n_rx_byte,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) unsigned char *p_rx_byte)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) enum hal_scr_id_e id = g_curr_sur_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) ret = rk_scr_transfer(id, n_tx_byte, p_tx_byte, n_rx_byte, p_rx_byte);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) unsigned int _scr_get_num_rx_bytes(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) enum hal_scr_id_e id = g_curr_sur_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) struct rk_scr *scr = to_opened_rk_scr(id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) if (scr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) return scr->rx_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) unsigned int _scr_get_num_tx_bytes(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) enum hal_scr_id_e id = g_curr_sur_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) struct rk_scr *scr = to_opened_rk_scr(id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) if (scr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) return scr->tx_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) void _scr_powerdown(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) enum hal_scr_id_e id = g_curr_sur_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) struct rk_scr *scr = to_opened_rk_scr(id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) if (scr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) rk_scr_powerdown(scr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) void _scr_irq_set_handler(hal_scr_irq_handler_t handler)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) enum hal_scr_id_e id = g_curr_sur_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) struct rk_scr *scr = to_rk_scr(id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) if (scr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) scr->user_handler = handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) void _scr_irq_set_mask(struct hal_scr_irq_status_t mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) enum hal_scr_id_e id = g_curr_sur_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) struct rk_scr *scr = to_rk_scr(id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) if (scr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) scr->user_mask = mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) struct hal_scr_irq_status_t _scr_irq_get_mask(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) enum hal_scr_id_e id = g_curr_sur_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) struct rk_scr *scr = to_rk_scr(id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) struct hal_scr_irq_status_t user_mask = {0};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) if (scr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) return scr->user_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) return user_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) enum hal_scr_detect_status_e _scr_irq_get_detect_status(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) enum hal_scr_id_e id = g_curr_sur_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) struct rk_scr *scr = to_rk_scr(id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) if (scr && (scr->hw->reg_base->SCPADS & SCPRESENT)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) DAL_LOGV("\n scr_check_card_insert: yes.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) return SMC_DRV_INT_CARDIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) DAL_LOGV("\n scr_check_card_insert: no.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) return SMC_DRV_INT_CARDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) unsigned char _scr_rx_done(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) enum hal_scr_id_e id = g_curr_sur_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) struct rk_scr *scr = to_rk_scr(id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) if (scr->hw->reg_base->INTSTAT1 & RXDONE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) void scr_set_etu_duration_struct(int f_and_d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) switch (f_and_d) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) case HAL_SCR_ETU_F_372_AND_D_1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) _scr_set_etu_duration(372, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) case HAL_SCR_ETU_F_512_AND_D_8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) _scr_set_etu_duration(512, 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) case HAL_SCR_ETU_F_512_AND_D_4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) _scr_set_etu_duration(512, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) int scr_check_card_insert(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) int card_detect = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) card_detect = _scr_irq_get_detect_status();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) if (card_detect)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) return SMC_DRV_INT_CARDIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) return SMC_DRV_INT_CARDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) static void scr_activate_card(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) _scr_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) _scr_set_voltage(HAL_SCR_VOLTAGE_CLASS_B);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) static void scr_deactivate_card(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) _scr_close();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) static void scr_isr_callback(enum hal_scr_irq_cause_e cause)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) complete(&rk_scr->is_done);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) ssize_t scr_write(unsigned char *buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) unsigned int write_cnt, unsigned int *to_read_cnt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) unsigned time_out = SMC_DEFAULT_TIMEOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) unsigned long udelay = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) mutex_lock(&rk_scr->scr_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) if (scr_check_card_insert() == SMC_DRV_INT_CARDOUT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) mutex_unlock(&rk_scr->scr_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) return SMC_ERROR_CARD_NOT_INSERT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) udelay = msecs_to_jiffies(time_out) + jiffies;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) init_completion(&rk_scr->is_done);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) rk_scr->recv_data_count = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) rk_scr->recv_data_offset = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) _scr_clock_start();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) _scr_tx_byte(write_cnt, buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) if (*to_read_cnt != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) /* Set registers, ready to receive.*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) _scr_rx_byte(*to_read_cnt, rk_scr->recv_buffer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) ret = wait_for_completion_timeout(&rk_scr->is_done,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) msecs_to_jiffies(time_out));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) rk_scr->recv_data_count = _scr_get_num_rx_bytes();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) if (ret == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) _scr_clock_stop();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) mutex_unlock(&rk_scr->scr_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) return TIMEOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) _scr_clock_stop();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) mutex_unlock(&rk_scr->scr_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) return SUCCESSFUL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) ssize_t scr_read(unsigned char *buf, unsigned int to_read_cnt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) unsigned int *have_read_cnt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) unsigned data_len = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) unsigned data_remain = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) unsigned data_available = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) unsigned data_offset = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) unsigned time_out_ms = SMC_DEFAULT_TIMEOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) unsigned data_count = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) unsigned char data_remain_flag = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) unsigned long udelay = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) if (!rk_scr->recv_buffer)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) return SMC_ERROR_RX_ERR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) mutex_lock(&rk_scr->scr_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) if (scr_check_card_insert() == SMC_DRV_INT_CARDOUT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) mutex_unlock(&rk_scr->scr_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) return SMC_ERROR_CARD_NOT_INSERT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) udelay = msecs_to_jiffies(time_out_ms) + jiffies;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) data_remain = to_read_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) data_count = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) _scr_clock_start();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) if (data_remain != 0xffffff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) data_remain_flag = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) while (time_before(jiffies, udelay)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) data_available = rk_scr->recv_data_count
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) - rk_scr->recv_data_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) if (data_available) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) if (data_remain_flag)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) data_len = (data_available > data_remain)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) ? (data_remain) : (data_available);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) data_len = data_available;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) data_offset = rk_scr->recv_data_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) memcpy(&buf[data_count],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) &rk_scr->recv_buffer[data_offset],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) data_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) data_count += data_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) rk_scr->recv_data_offset += data_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) if (data_remain_flag)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) data_remain -= data_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) if (data_remain_flag && (data_remain == 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) msleep(50);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) _scr_clock_stop();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) *have_read_cnt = data_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) mutex_unlock(&rk_scr->scr_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) return SUCCESSFUL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) int scr_open(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) mutex_lock(&rk_scr->scr_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) _scr_irq_set_handler(scr_isr_callback);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) if (!rk_scr->recv_buffer) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) rk_scr->recv_buffer = kmalloc(SMC_RECEIVE_BUF_LEN, GFP_DMA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) if (!rk_scr->recv_buffer)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) return NO_MEMORY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) memset(rk_scr->recv_buffer, 0, SMC_RECEIVE_BUF_LEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) init_completion(&rk_scr->is_done);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) rk_scr->recv_data_count = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) rk_scr->recv_data_offset = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) scr_activate_card();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) mutex_unlock(&rk_scr->scr_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) return SUCCESSFUL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) int scr_close(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) mutex_lock(&rk_scr->scr_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) scr_deactivate_card();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) kfree(rk_scr->recv_buffer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) rk_scr->recv_buffer = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) mutex_unlock(&rk_scr->scr_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) return SUCCESSFUL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) int scr_reset(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) unsigned long timeout_ms = SMC_DEFAULT_TIMEOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) int i = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) DAL_LOGV("-----------------scr_reset------------------\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) mutex_lock(&rk_scr->scr_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) if (scr_check_card_insert() == SMC_DRV_INT_CARDOUT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) mutex_unlock(&rk_scr->scr_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) return SMC_ERROR_CARD_NOT_INSERT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) init_completion(&rk_scr->is_done);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) rk_scr->recv_data_count = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) rk_scr->recv_data_offset = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) memset(rk_scr->atr_buffer, 0, SMC_ATR_MAX_LENGTH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) rk_scr->atr_length = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) _scr_clock_start();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) _scr_reset(rk_scr->recv_buffer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) ret = wait_for_completion_timeout(&rk_scr->is_done,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) msecs_to_jiffies(timeout_ms));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) rk_scr->recv_data_count = _scr_get_num_rx_bytes();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) _scr_clock_stop();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) if ((rk_scr->recv_data_count <= SMC_ATR_MAX_LENGTH) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) (rk_scr->recv_data_count > 0)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) memcpy(rk_scr->atr_buffer, rk_scr->recv_buffer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) rk_scr->recv_data_count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) rk_scr->atr_length = rk_scr->recv_data_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) DAL_LOGV("ATR error: rk_scr->recv_data_count = %d.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) rk_scr->recv_data_count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) mutex_unlock(&rk_scr->scr_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) return SMC_ERROR_ATR_ERR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) DAL_LOGV("\n--------ATR start-----------\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) DAL_LOGV("rk_scr->atr_length = %d\n", rk_scr->atr_length);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) for (i = 0; i < rk_scr->recv_data_count; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) DAL_LOGV("0x%2x\n", rk_scr->atr_buffer[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) DAL_LOGV("\n--------ATR end-----------\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) mutex_unlock(&rk_scr->scr_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) return SUCCESSFUL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) int scr_get_atr_data(unsigned char *atr_buf, unsigned char *atr_len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) if ((!atr_buf) || (!atr_len))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) return SMC_ERROR_BAD_PARAMETER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) mutex_lock(&rk_scr->scr_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) if ((rk_scr->atr_length < SMC_ATR_MIN_LENGTH) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) (rk_scr->atr_length > SMC_ATR_MAX_LENGTH)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) mutex_unlock(&rk_scr->scr_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) return SMC_ERROR_ATR_ERR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) memcpy(atr_buf, &rk_scr->atr_buffer[0], rk_scr->atr_length);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) *atr_len = rk_scr->atr_length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) mutex_unlock(&rk_scr->scr_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) return SUCCESSFUL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) void scr_set_etu_duration(unsigned int F, unsigned int D)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) mutex_lock(&rk_scr->scr_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) _scr_set_etu_duration(F, D);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) mutex_unlock(&rk_scr->scr_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) void scr_set_work_waitingtime(unsigned char wi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) mutex_lock(&rk_scr->scr_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) _scr_set_work_waitingtime(wi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) mutex_unlock(&rk_scr->scr_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) static int scr_sysfs_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) static ssize_t scr_sysfs_show(struct kobject *kobj,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) struct kobj_attribute *attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) scr_open();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) scr_reset();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) scr_close();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) return sprintf(buf, "%d\n", scr_sysfs_value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) static ssize_t scr_sysfs_store(struct kobject *kobj,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) struct kobj_attribute *attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) const char *buf, size_t count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) ret = sscanf(buf, "%du", &scr_sysfs_value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) if (ret != 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) static struct kobj_attribute scr_sysfs_attribute =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) __ATTR(scr_sysfs, 0664, scr_sysfs_show, scr_sysfs_store);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) struct attribute *rockchip_smartcard_attributes[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) &scr_sysfs_attribute.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) static const struct attribute_group rockchip_smartcard_group = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) .attrs = rockchip_smartcard_attributes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) /* #define CONFIG_SMARTCARD_MUX_SEL_T0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) /* #define CONFIG_SMARTCARD_MUX_SEL_T1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) #define RK_SCR_CLK_NAME "g_pclk_sim_card"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) static int rk_scr_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) struct rk_scr_device *rk_scr_dev = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) struct resource *res = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) struct device *dev = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) rk_scr_dev = devm_kzalloc(dev, sizeof(*rk_scr_dev), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) if (!rk_scr_dev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) dev_err(dev, "failed to allocate scr_device\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) rk_scr = rk_scr_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) mutex_init(&rk_scr->scr_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) rk_scr_dev->irq = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) if (rk_scr_dev->irq < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) dev_err(dev, "failed to get scr irq\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) return -ENOENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) ret = devm_request_irq(dev, rk_scr_dev->irq, rk_scr_irqhandler,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) 0, "rockchip-scr",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) (void *)&rk_scr->scr[g_curr_sur_id]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) dev_err(dev, "failed to attach scr irq\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) rk_scr_dev->clk_scr = devm_clk_get(dev, RK_SCR_CLK_NAME);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) if (IS_ERR(rk_scr_dev->clk_scr)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) dev_err(dev, "failed to get scr clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) return PTR_ERR(rk_scr_dev->clk_scr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) rk_scr_dev->regs = devm_ioremap_resource(dev, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) if (IS_ERR(rk_scr_dev->regs))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) return PTR_ERR(rk_scr_dev->regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) #ifdef CONFIG_SMARTCARD_MUX_SEL_T0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) writel_relaxed(((0x1 << 22) | (0x1 << 6)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) RK_GRF_VIRT + RK3288_GRF_SOC_CON2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) #ifdef CONFIG_SMARTCARD_MUX_SEL_T1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) pinctrl_select_state(dev->pins->p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) pinctrl_lookup_state(dev->pins->p, "sc_t1"));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) writel_relaxed(((0x1 << 22) | (0x0 << 6)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) (RK_GRF_VIRT + RK3288_GRF_SOC_CON2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) dev_set_drvdata(dev, rk_scr_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) ret = sysfs_create_group(&pdev->dev.kobj, &rockchip_smartcard_group);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) dev_err(&pdev->dev, "Create sysfs group failed (%d)\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) DAL_LOGV("rk_scr_pdev->name = %s\n", pdev->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) DAL_LOGV("rk_scr_dev->irq = 0x%x\n", rk_scr_dev->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) #ifdef CONFIG_PM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) static int rk_scr_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) struct rk_scr_device *rk_scr_dev = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) disable_irq(rk_scr_dev->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) clk_disable(rk_scr_dev->clk_scr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) static int rk_scr_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) struct rk_scr_device *rk_scr_dev = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) clk_enable(rk_scr_dev->clk_scr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) enable_irq(rk_scr_dev->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) #define rk_scr_suspend NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) #define rk_scr_resume NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) #ifdef CONFIG_OF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) static const struct of_device_id rockchip_scr_dt_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) { .compatible = "rockchip-scr",},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) MODULE_DEVICE_TABLE(of, rockchip_scr_dt_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) #endif /* CONFIG_OF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) static const struct dev_pm_ops scr_pm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) .suspend = rk_scr_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) .resume = rk_scr_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) static struct platform_driver rk_scr_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) .name = "rockchip-scr",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) .pm = &scr_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) .of_match_table = of_match_ptr(rockchip_scr_dt_match),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) .probe = rk_scr_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) module_platform_driver(rk_scr_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) MODULE_DESCRIPTION("rockchip Smart Card controller driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) MODULE_AUTHOR("<rockchip>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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