^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /* Copyright (c) 2013, The Linux Foundation. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2015, Sony Mobile Communications Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) struct qcom_coincell {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) u32 base_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define QCOM_COINCELL_REG_RSET 0x44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define QCOM_COINCELL_REG_VSET 0x45
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define QCOM_COINCELL_REG_ENABLE 0x46
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define QCOM_COINCELL_ENABLE BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) static const int qcom_rset_map[] = { 2100, 1700, 1200, 800 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) static const int qcom_vset_map[] = { 2500, 3200, 3100, 3000 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) /* NOTE: for pm8921 and others, voltage of 2500 is 16 (10000b), not 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) /* if enable==0, rset and vset are ignored */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) static int qcom_coincell_chgr_config(struct qcom_coincell *chgr, int rset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) int vset, bool enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) int i, j, rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) /* if disabling, just do that and skip other operations */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) if (!enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) return regmap_write(chgr->regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) chgr->base_addr + QCOM_COINCELL_REG_ENABLE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) /* find index for current-limiting resistor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) for (i = 0; i < ARRAY_SIZE(qcom_rset_map); i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) if (rset == qcom_rset_map[i])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) if (i >= ARRAY_SIZE(qcom_rset_map)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) dev_err(chgr->dev, "invalid rset-ohms value %d\n", rset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) /* find index for charge voltage */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) for (j = 0; j < ARRAY_SIZE(qcom_vset_map); j++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) if (vset == qcom_vset_map[j])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) if (j >= ARRAY_SIZE(qcom_vset_map)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) dev_err(chgr->dev, "invalid vset-millivolts value %d\n", vset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) rc = regmap_write(chgr->regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) chgr->base_addr + QCOM_COINCELL_REG_RSET, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) if (rc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) * This is mainly to flag a bad base_addr (reg) from dts.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) * Other failures writing to the registers should be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) * extremely rare, or indicative of problems that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) * should be reported elsewhere (eg. spmi failure).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) dev_err(chgr->dev, "could not write to RSET register\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) rc = regmap_write(chgr->regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) chgr->base_addr + QCOM_COINCELL_REG_VSET, j);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) /* set 'enable' register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) return regmap_write(chgr->regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) chgr->base_addr + QCOM_COINCELL_REG_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) QCOM_COINCELL_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) static int qcom_coincell_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) struct device_node *node = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) struct qcom_coincell chgr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) u32 rset = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) u32 vset = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) bool enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) chgr.dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) chgr.regmap = dev_get_regmap(pdev->dev.parent, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) if (!chgr.regmap) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) dev_err(chgr.dev, "Unable to get regmap\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) rc = of_property_read_u32(node, "reg", &chgr.base_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) enable = !of_property_read_bool(node, "qcom,charger-disable");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) if (enable) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) rc = of_property_read_u32(node, "qcom,rset-ohms", &rset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) if (rc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) dev_err(chgr.dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) "can't find 'qcom,rset-ohms' in DT block");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) rc = of_property_read_u32(node, "qcom,vset-millivolts", &vset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) if (rc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) dev_err(chgr.dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) "can't find 'qcom,vset-millivolts' in DT block");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) return qcom_coincell_chgr_config(&chgr, rset, vset, enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) static const struct of_device_id qcom_coincell_match_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) { .compatible = "qcom,pm8941-coincell", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) MODULE_DEVICE_TABLE(of, qcom_coincell_match_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) static struct platform_driver qcom_coincell_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) .name = "qcom-spmi-coincell",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) .of_match_table = qcom_coincell_match_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) .probe = qcom_coincell_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) module_platform_driver(qcom_coincell_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) MODULE_DESCRIPTION("Qualcomm PMIC coincell charger driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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