^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) 2011 LAPIS Semiconductor Co., Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/fs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/uaccess.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/string.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/mutex.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/if_ether.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/ctype.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/dmi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define PHUB_STATUS 0x00 /* Status Register offset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define PHUB_CONTROL 0x04 /* Control Register offset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define PHUB_TIMEOUT 0x05 /* Time out value for Status Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define PCH_PHUB_ROM_WRITE_ENABLE 0x01 /* Enabling for writing ROM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define PCH_PHUB_ROM_WRITE_DISABLE 0x00 /* Disabling for writing ROM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define PCH_PHUB_MAC_START_ADDR_EG20T 0x14 /* MAC data area start address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) offset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define PCH_PHUB_MAC_START_ADDR_ML7223 0x20C /* MAC data area start address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) offset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define PCH_PHUB_ROM_START_ADDR_EG20T 0x80 /* ROM data area start address offset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) (Intel EG20T PCH)*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define PCH_PHUB_ROM_START_ADDR_ML7213 0x400 /* ROM data area start address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) offset(LAPIS Semicon ML7213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define PCH_PHUB_ROM_START_ADDR_ML7223 0x400 /* ROM data area start address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) offset(LAPIS Semicon ML7223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) /* MAX number of INT_REDUCE_CONTROL registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define MAX_NUM_INT_REDUCE_CONTROL_REG 128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define PCI_DEVICE_ID_PCH1_PHUB 0x8801
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define PCH_MINOR_NOS 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define CLKCFG_CAN_50MHZ 0x12000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define CLKCFG_CANCLK_MASK 0xFF000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define CLKCFG_UART_MASK 0xFFFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) /* CM-iTC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define CLKCFG_UART_48MHZ (1 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define CLKCFG_UART_25MHZ (2 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define CLKCFG_BAUDDIV (2 << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define CLKCFG_PLL2VCO (8 << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define CLKCFG_UARTCLKSEL (1 << 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) /* Macros for ML7213 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define PCI_DEVICE_ID_ROHM_ML7213_PHUB 0x801A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) /* Macros for ML7223 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define PCI_DEVICE_ID_ROHM_ML7223_mPHUB 0x8012 /* for Bus-m */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define PCI_DEVICE_ID_ROHM_ML7223_nPHUB 0x8002 /* for Bus-n */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) /* Macros for ML7831 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define PCI_DEVICE_ID_ROHM_ML7831_PHUB 0x8801
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) /* SROM ACCESS Macro */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define PCH_WORD_ADDR_MASK (~((1 << 2) - 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) /* Registers address offset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define PCH_PHUB_ID_REG 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define PCH_PHUB_QUEUE_PRI_VAL_REG 0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define PCH_PHUB_RC_QUEUE_MAXSIZE_REG 0x0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define PCH_PHUB_BRI_QUEUE_MAXSIZE_REG 0x000C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define PCH_PHUB_COMP_RESP_TIMEOUT_REG 0x0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define PCH_PHUB_BUS_SLAVE_CONTROL_REG 0x0014
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define PCH_PHUB_DEADLOCK_AVOID_TYPE_REG 0x0018
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define PCH_PHUB_INTPIN_REG_WPERMIT_REG0 0x0020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define PCH_PHUB_INTPIN_REG_WPERMIT_REG1 0x0024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define PCH_PHUB_INTPIN_REG_WPERMIT_REG2 0x0028
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define PCH_PHUB_INTPIN_REG_WPERMIT_REG3 0x002C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define PCH_PHUB_INT_REDUCE_CONTROL_REG_BASE 0x0040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define CLKCFG_REG_OFFSET 0x500
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define FUNCSEL_REG_OFFSET 0x508
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define PCH_PHUB_OROM_SIZE 15360
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) * struct pch_phub_reg - PHUB register structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) * @phub_id_reg: PHUB_ID register val
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) * @q_pri_val_reg: QUEUE_PRI_VAL register val
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) * @rc_q_maxsize_reg: RC_QUEUE_MAXSIZE register val
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) * @bri_q_maxsize_reg: BRI_QUEUE_MAXSIZE register val
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) * @comp_resp_timeout_reg: COMP_RESP_TIMEOUT register val
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) * @bus_slave_control_reg: BUS_SLAVE_CONTROL_REG register val
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) * @deadlock_avoid_type_reg: DEADLOCK_AVOID_TYPE register val
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) * @intpin_reg_wpermit_reg0: INTPIN_REG_WPERMIT register 0 val
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) * @intpin_reg_wpermit_reg1: INTPIN_REG_WPERMIT register 1 val
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) * @intpin_reg_wpermit_reg2: INTPIN_REG_WPERMIT register 2 val
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) * @intpin_reg_wpermit_reg3: INTPIN_REG_WPERMIT register 3 val
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) * @int_reduce_control_reg: INT_REDUCE_CONTROL registers val
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) * @clkcfg_reg: CLK CFG register val
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) * @funcsel_reg: Function select register value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) * @pch_phub_base_address: Register base address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) * @pch_phub_extrom_base_address: external rom base address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) * @pch_mac_start_address: MAC address area start address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) * @pch_opt_rom_start_address: Option ROM start address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) * @ioh_type: Save IOH type
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) * @pdev: pointer to pci device struct
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) struct pch_phub_reg {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) u32 phub_id_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) u32 q_pri_val_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) u32 rc_q_maxsize_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) u32 bri_q_maxsize_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) u32 comp_resp_timeout_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) u32 bus_slave_control_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) u32 deadlock_avoid_type_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) u32 intpin_reg_wpermit_reg0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) u32 intpin_reg_wpermit_reg1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) u32 intpin_reg_wpermit_reg2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) u32 intpin_reg_wpermit_reg3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) u32 int_reduce_control_reg[MAX_NUM_INT_REDUCE_CONTROL_REG];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) u32 clkcfg_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) u32 funcsel_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) void __iomem *pch_phub_base_address;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) void __iomem *pch_phub_extrom_base_address;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) u32 pch_mac_start_address;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) u32 pch_opt_rom_start_address;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) int ioh_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) struct pci_dev *pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) /* SROM SPEC for MAC address assignment offset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) static const int pch_phub_mac_offset[ETH_ALEN] = {0x3, 0x2, 0x1, 0x0, 0xb, 0xa};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) static DEFINE_MUTEX(pch_phub_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) * pch_phub_read_modify_write_reg() - Reading modifying and writing register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) * @chip: Pointer to the PHUB register structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) * @reg_addr_offset: Register offset address value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) * @data: Writing value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) * @mask: Mask value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) static void pch_phub_read_modify_write_reg(struct pch_phub_reg *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) unsigned int reg_addr_offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) unsigned int data, unsigned int mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) void __iomem *reg_addr = chip->pch_phub_base_address + reg_addr_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) iowrite32(((ioread32(reg_addr) & ~mask)) | data, reg_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) /* pch_phub_save_reg_conf - saves register configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) static void __maybe_unused pch_phub_save_reg_conf(struct pci_dev *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) struct pch_phub_reg *chip = pci_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) void __iomem *p = chip->pch_phub_base_address;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) chip->phub_id_reg = ioread32(p + PCH_PHUB_ID_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) chip->q_pri_val_reg = ioread32(p + PCH_PHUB_QUEUE_PRI_VAL_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) chip->rc_q_maxsize_reg = ioread32(p + PCH_PHUB_RC_QUEUE_MAXSIZE_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) chip->bri_q_maxsize_reg = ioread32(p + PCH_PHUB_BRI_QUEUE_MAXSIZE_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) chip->comp_resp_timeout_reg =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) ioread32(p + PCH_PHUB_COMP_RESP_TIMEOUT_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) chip->bus_slave_control_reg =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) ioread32(p + PCH_PHUB_BUS_SLAVE_CONTROL_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) chip->deadlock_avoid_type_reg =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) ioread32(p + PCH_PHUB_DEADLOCK_AVOID_TYPE_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) chip->intpin_reg_wpermit_reg0 =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) ioread32(p + PCH_PHUB_INTPIN_REG_WPERMIT_REG0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) chip->intpin_reg_wpermit_reg1 =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) ioread32(p + PCH_PHUB_INTPIN_REG_WPERMIT_REG1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) chip->intpin_reg_wpermit_reg2 =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) ioread32(p + PCH_PHUB_INTPIN_REG_WPERMIT_REG2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) chip->intpin_reg_wpermit_reg3 =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) ioread32(p + PCH_PHUB_INTPIN_REG_WPERMIT_REG3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) dev_dbg(&pdev->dev, "%s : "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) "chip->phub_id_reg=%x, "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) "chip->q_pri_val_reg=%x, "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) "chip->rc_q_maxsize_reg=%x, "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) "chip->bri_q_maxsize_reg=%x, "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) "chip->comp_resp_timeout_reg=%x, "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) "chip->bus_slave_control_reg=%x, "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) "chip->deadlock_avoid_type_reg=%x, "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) "chip->intpin_reg_wpermit_reg0=%x, "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) "chip->intpin_reg_wpermit_reg1=%x, "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) "chip->intpin_reg_wpermit_reg2=%x, "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) "chip->intpin_reg_wpermit_reg3=%x\n", __func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) chip->phub_id_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) chip->q_pri_val_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) chip->rc_q_maxsize_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) chip->bri_q_maxsize_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) chip->comp_resp_timeout_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) chip->bus_slave_control_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) chip->deadlock_avoid_type_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) chip->intpin_reg_wpermit_reg0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) chip->intpin_reg_wpermit_reg1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) chip->intpin_reg_wpermit_reg2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) chip->intpin_reg_wpermit_reg3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) for (i = 0; i < MAX_NUM_INT_REDUCE_CONTROL_REG; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) chip->int_reduce_control_reg[i] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) ioread32(p + PCH_PHUB_INT_REDUCE_CONTROL_REG_BASE + 4 * i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) dev_dbg(&pdev->dev, "%s : "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) "chip->int_reduce_control_reg[%d]=%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) __func__, i, chip->int_reduce_control_reg[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) chip->clkcfg_reg = ioread32(p + CLKCFG_REG_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) if ((chip->ioh_type == 2) || (chip->ioh_type == 4))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) chip->funcsel_reg = ioread32(p + FUNCSEL_REG_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) /* pch_phub_restore_reg_conf - restore register configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) static void __maybe_unused pch_phub_restore_reg_conf(struct pci_dev *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) struct pch_phub_reg *chip = pci_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) void __iomem *p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) p = chip->pch_phub_base_address;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) iowrite32(chip->phub_id_reg, p + PCH_PHUB_ID_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) iowrite32(chip->q_pri_val_reg, p + PCH_PHUB_QUEUE_PRI_VAL_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) iowrite32(chip->rc_q_maxsize_reg, p + PCH_PHUB_RC_QUEUE_MAXSIZE_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) iowrite32(chip->bri_q_maxsize_reg, p + PCH_PHUB_BRI_QUEUE_MAXSIZE_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) iowrite32(chip->comp_resp_timeout_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) p + PCH_PHUB_COMP_RESP_TIMEOUT_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) iowrite32(chip->bus_slave_control_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) p + PCH_PHUB_BUS_SLAVE_CONTROL_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) iowrite32(chip->deadlock_avoid_type_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) p + PCH_PHUB_DEADLOCK_AVOID_TYPE_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) iowrite32(chip->intpin_reg_wpermit_reg0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) p + PCH_PHUB_INTPIN_REG_WPERMIT_REG0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) iowrite32(chip->intpin_reg_wpermit_reg1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) p + PCH_PHUB_INTPIN_REG_WPERMIT_REG1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) iowrite32(chip->intpin_reg_wpermit_reg2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) p + PCH_PHUB_INTPIN_REG_WPERMIT_REG2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) iowrite32(chip->intpin_reg_wpermit_reg3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) p + PCH_PHUB_INTPIN_REG_WPERMIT_REG3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) dev_dbg(&pdev->dev, "%s : "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) "chip->phub_id_reg=%x, "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) "chip->q_pri_val_reg=%x, "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) "chip->rc_q_maxsize_reg=%x, "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) "chip->bri_q_maxsize_reg=%x, "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) "chip->comp_resp_timeout_reg=%x, "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) "chip->bus_slave_control_reg=%x, "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) "chip->deadlock_avoid_type_reg=%x, "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) "chip->intpin_reg_wpermit_reg0=%x, "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) "chip->intpin_reg_wpermit_reg1=%x, "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) "chip->intpin_reg_wpermit_reg2=%x, "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) "chip->intpin_reg_wpermit_reg3=%x\n", __func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) chip->phub_id_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) chip->q_pri_val_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) chip->rc_q_maxsize_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) chip->bri_q_maxsize_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) chip->comp_resp_timeout_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) chip->bus_slave_control_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) chip->deadlock_avoid_type_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) chip->intpin_reg_wpermit_reg0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) chip->intpin_reg_wpermit_reg1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) chip->intpin_reg_wpermit_reg2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) chip->intpin_reg_wpermit_reg3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) for (i = 0; i < MAX_NUM_INT_REDUCE_CONTROL_REG; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) iowrite32(chip->int_reduce_control_reg[i],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) p + PCH_PHUB_INT_REDUCE_CONTROL_REG_BASE + 4 * i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) dev_dbg(&pdev->dev, "%s : "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) "chip->int_reduce_control_reg[%d]=%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) __func__, i, chip->int_reduce_control_reg[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) iowrite32(chip->clkcfg_reg, p + CLKCFG_REG_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) if ((chip->ioh_type == 2) || (chip->ioh_type == 4))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) iowrite32(chip->funcsel_reg, p + FUNCSEL_REG_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) * pch_phub_read_serial_rom() - Reading Serial ROM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) * @chip: Pointer to the PHUB register structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) * @offset_address: Serial ROM offset address to read.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) * @data: Read buffer for specified Serial ROM value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) static void pch_phub_read_serial_rom(struct pch_phub_reg *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) unsigned int offset_address, u8 *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) void __iomem *mem_addr = chip->pch_phub_extrom_base_address +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) offset_address;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) *data = ioread8(mem_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) * pch_phub_write_serial_rom() - Writing Serial ROM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) * @chip: Pointer to the PHUB register structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) * @offset_address: Serial ROM offset address.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) * @data: Serial ROM value to write.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) static int pch_phub_write_serial_rom(struct pch_phub_reg *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) unsigned int offset_address, u8 data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) void __iomem *mem_addr = chip->pch_phub_extrom_base_address +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) (offset_address & PCH_WORD_ADDR_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) unsigned int word_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) unsigned int pos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) unsigned int mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) pos = (offset_address % 4) * 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) mask = ~(0xFF << pos);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) iowrite32(PCH_PHUB_ROM_WRITE_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) chip->pch_phub_extrom_base_address + PHUB_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) word_data = ioread32(mem_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) iowrite32((word_data & mask) | (u32)data << pos, mem_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) i = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) while (ioread8(chip->pch_phub_extrom_base_address +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) PHUB_STATUS) != 0x00) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) msleep(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) if (i == PHUB_TIMEOUT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) i++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) iowrite32(PCH_PHUB_ROM_WRITE_DISABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) chip->pch_phub_extrom_base_address + PHUB_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) * pch_phub_read_serial_rom_val() - Read Serial ROM value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) * @chip: Pointer to the PHUB register structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) * @offset_address: Serial ROM address offset value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) * @data: Serial ROM value to read.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) static void pch_phub_read_serial_rom_val(struct pch_phub_reg *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) unsigned int offset_address, u8 *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) unsigned int mem_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) mem_addr = chip->pch_mac_start_address +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) pch_phub_mac_offset[offset_address];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) pch_phub_read_serial_rom(chip, mem_addr, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) * pch_phub_write_serial_rom_val() - writing Serial ROM value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) * @chip: Pointer to the PHUB register structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) * @offset_address: Serial ROM address offset value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) * @data: Serial ROM value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) static int pch_phub_write_serial_rom_val(struct pch_phub_reg *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) unsigned int offset_address, u8 data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) int retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) unsigned int mem_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) mem_addr = chip->pch_mac_start_address +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) pch_phub_mac_offset[offset_address];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) retval = pch_phub_write_serial_rom(chip, mem_addr, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) return retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) /* pch_phub_gbe_serial_rom_conf - makes Serial ROM header format configuration
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) * for Gigabit Ethernet MAC address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) static int pch_phub_gbe_serial_rom_conf(struct pch_phub_reg *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) int retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) retval = pch_phub_write_serial_rom(chip, 0x0b, 0xbc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) retval |= pch_phub_write_serial_rom(chip, 0x0a, 0x10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) retval |= pch_phub_write_serial_rom(chip, 0x09, 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) retval |= pch_phub_write_serial_rom(chip, 0x08, 0x02);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) retval |= pch_phub_write_serial_rom(chip, 0x0f, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) retval |= pch_phub_write_serial_rom(chip, 0x0e, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) retval |= pch_phub_write_serial_rom(chip, 0x0d, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) retval |= pch_phub_write_serial_rom(chip, 0x0c, 0x80);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) retval |= pch_phub_write_serial_rom(chip, 0x13, 0xbc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) retval |= pch_phub_write_serial_rom(chip, 0x12, 0x10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) retval |= pch_phub_write_serial_rom(chip, 0x11, 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) retval |= pch_phub_write_serial_rom(chip, 0x10, 0x18);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) retval |= pch_phub_write_serial_rom(chip, 0x1b, 0xbc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) retval |= pch_phub_write_serial_rom(chip, 0x1a, 0x10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) retval |= pch_phub_write_serial_rom(chip, 0x19, 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) retval |= pch_phub_write_serial_rom(chip, 0x18, 0x19);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) retval |= pch_phub_write_serial_rom(chip, 0x23, 0xbc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) retval |= pch_phub_write_serial_rom(chip, 0x22, 0x10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) retval |= pch_phub_write_serial_rom(chip, 0x21, 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) retval |= pch_phub_write_serial_rom(chip, 0x20, 0x3a);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) retval |= pch_phub_write_serial_rom(chip, 0x27, 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) retval |= pch_phub_write_serial_rom(chip, 0x26, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) retval |= pch_phub_write_serial_rom(chip, 0x25, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) retval |= pch_phub_write_serial_rom(chip, 0x24, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) return retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) /* pch_phub_gbe_serial_rom_conf_mp - makes SerialROM header format configuration
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) * for Gigabit Ethernet MAC address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) static int pch_phub_gbe_serial_rom_conf_mp(struct pch_phub_reg *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) int retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) u32 offset_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) offset_addr = 0x200;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) retval = pch_phub_write_serial_rom(chip, 0x03 + offset_addr, 0xbc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) retval |= pch_phub_write_serial_rom(chip, 0x02 + offset_addr, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) retval |= pch_phub_write_serial_rom(chip, 0x01 + offset_addr, 0x40);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) retval |= pch_phub_write_serial_rom(chip, 0x00 + offset_addr, 0x02);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) retval |= pch_phub_write_serial_rom(chip, 0x07 + offset_addr, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) retval |= pch_phub_write_serial_rom(chip, 0x06 + offset_addr, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) retval |= pch_phub_write_serial_rom(chip, 0x05 + offset_addr, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) retval |= pch_phub_write_serial_rom(chip, 0x04 + offset_addr, 0x80);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) retval |= pch_phub_write_serial_rom(chip, 0x0b + offset_addr, 0xbc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) retval |= pch_phub_write_serial_rom(chip, 0x0a + offset_addr, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) retval |= pch_phub_write_serial_rom(chip, 0x09 + offset_addr, 0x40);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) retval |= pch_phub_write_serial_rom(chip, 0x08 + offset_addr, 0x18);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) retval |= pch_phub_write_serial_rom(chip, 0x13 + offset_addr, 0xbc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) retval |= pch_phub_write_serial_rom(chip, 0x12 + offset_addr, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) retval |= pch_phub_write_serial_rom(chip, 0x11 + offset_addr, 0x40);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) retval |= pch_phub_write_serial_rom(chip, 0x10 + offset_addr, 0x19);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) retval |= pch_phub_write_serial_rom(chip, 0x1b + offset_addr, 0xbc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) retval |= pch_phub_write_serial_rom(chip, 0x1a + offset_addr, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) retval |= pch_phub_write_serial_rom(chip, 0x19 + offset_addr, 0x40);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) retval |= pch_phub_write_serial_rom(chip, 0x18 + offset_addr, 0x3a);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) retval |= pch_phub_write_serial_rom(chip, 0x1f + offset_addr, 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) retval |= pch_phub_write_serial_rom(chip, 0x1e + offset_addr, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) retval |= pch_phub_write_serial_rom(chip, 0x1d + offset_addr, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) retval |= pch_phub_write_serial_rom(chip, 0x1c + offset_addr, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) return retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) * pch_phub_read_gbe_mac_addr() - Read Gigabit Ethernet MAC address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) * @chip: Pointer to the PHUB register structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) * @data: Buffer of the Gigabit Ethernet MAC address value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) static void pch_phub_read_gbe_mac_addr(struct pch_phub_reg *chip, u8 *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) for (i = 0; i < ETH_ALEN; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) pch_phub_read_serial_rom_val(chip, i, &data[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) * pch_phub_write_gbe_mac_addr() - Write MAC address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) * @chip: Pointer to the PHUB register structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) * @data: Gigabit Ethernet MAC address value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) static int pch_phub_write_gbe_mac_addr(struct pch_phub_reg *chip, u8 *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) int retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) if ((chip->ioh_type == 1) || (chip->ioh_type == 5)) /* EG20T or ML7831*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) retval = pch_phub_gbe_serial_rom_conf(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) else /* ML7223 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) retval = pch_phub_gbe_serial_rom_conf_mp(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) if (retval)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) return retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) for (i = 0; i < ETH_ALEN; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) retval = pch_phub_write_serial_rom_val(chip, i, data[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) if (retval)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) return retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) return retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) static ssize_t pch_phub_bin_read(struct file *filp, struct kobject *kobj,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) struct bin_attribute *attr, char *buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) loff_t off, size_t count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) unsigned int rom_signature;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) unsigned char rom_length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) unsigned int tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) unsigned int addr_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) unsigned int orom_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) ssize_t rom_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) struct pch_phub_reg *chip = dev_get_drvdata(kobj_to_dev(kobj));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) ret = mutex_lock_interruptible(&pch_phub_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) err = -ERESTARTSYS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) goto return_err_nomutex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) /* Get Rom signature */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) chip->pch_phub_extrom_base_address = pci_map_rom(chip->pdev, &rom_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) if (!chip->pch_phub_extrom_base_address) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) err = -ENODATA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) goto exrom_map_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) pch_phub_read_serial_rom(chip, chip->pch_opt_rom_start_address,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) (unsigned char *)&rom_signature);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) rom_signature &= 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) pch_phub_read_serial_rom(chip, chip->pch_opt_rom_start_address + 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) (unsigned char *)&tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) rom_signature |= (tmp & 0xff) << 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) if (rom_signature == 0xAA55) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) pch_phub_read_serial_rom(chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) chip->pch_opt_rom_start_address + 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) &rom_length);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) orom_size = rom_length * 512;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) if (orom_size < off) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) addr_offset = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) goto return_ok;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) if (orom_size < count) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) addr_offset = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) goto return_ok;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) for (addr_offset = 0; addr_offset < count; addr_offset++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) pch_phub_read_serial_rom(chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) chip->pch_opt_rom_start_address + addr_offset + off,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) &buf[addr_offset]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) err = -ENODATA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) goto return_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) return_ok:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) pci_unmap_rom(chip->pdev, chip->pch_phub_extrom_base_address);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) mutex_unlock(&pch_phub_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) return addr_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) return_err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) pci_unmap_rom(chip->pdev, chip->pch_phub_extrom_base_address);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) exrom_map_err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) mutex_unlock(&pch_phub_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) return_err_nomutex:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) static ssize_t pch_phub_bin_write(struct file *filp, struct kobject *kobj,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) struct bin_attribute *attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) char *buf, loff_t off, size_t count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) unsigned int addr_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) ssize_t rom_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) struct pch_phub_reg *chip = dev_get_drvdata(kobj_to_dev(kobj));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) ret = mutex_lock_interruptible(&pch_phub_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) return -ERESTARTSYS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) if (off > PCH_PHUB_OROM_SIZE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) addr_offset = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) goto return_ok;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) if (count > PCH_PHUB_OROM_SIZE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) addr_offset = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) goto return_ok;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) chip->pch_phub_extrom_base_address = pci_map_rom(chip->pdev, &rom_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) if (!chip->pch_phub_extrom_base_address) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) err = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) goto exrom_map_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) for (addr_offset = 0; addr_offset < count; addr_offset++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) if (PCH_PHUB_OROM_SIZE < off + addr_offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) goto return_ok;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) ret = pch_phub_write_serial_rom(chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) chip->pch_opt_rom_start_address + addr_offset + off,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) buf[addr_offset]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) err = ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) goto return_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) return_ok:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) pci_unmap_rom(chip->pdev, chip->pch_phub_extrom_base_address);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) mutex_unlock(&pch_phub_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) return addr_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) return_err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) pci_unmap_rom(chip->pdev, chip->pch_phub_extrom_base_address);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) exrom_map_err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) mutex_unlock(&pch_phub_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) static ssize_t show_pch_mac(struct device *dev, struct device_attribute *attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) u8 mac[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) struct pch_phub_reg *chip = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) ssize_t rom_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) chip->pch_phub_extrom_base_address = pci_map_rom(chip->pdev, &rom_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) if (!chip->pch_phub_extrom_base_address)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) pch_phub_read_gbe_mac_addr(chip, mac);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) pci_unmap_rom(chip->pdev, chip->pch_phub_extrom_base_address);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) return sprintf(buf, "%pM\n", mac);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) static ssize_t store_pch_mac(struct device *dev, struct device_attribute *attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) const char *buf, size_t count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) u8 mac[ETH_ALEN];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) ssize_t rom_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) struct pch_phub_reg *chip = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) if (!mac_pton(buf, mac))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) chip->pch_phub_extrom_base_address = pci_map_rom(chip->pdev, &rom_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) if (!chip->pch_phub_extrom_base_address)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) ret = pch_phub_write_gbe_mac_addr(chip, mac);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) pci_unmap_rom(chip->pdev, chip->pch_phub_extrom_base_address);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) return count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) static DEVICE_ATTR(pch_mac, S_IRUGO | S_IWUSR, show_pch_mac, store_pch_mac);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) static const struct bin_attribute pch_bin_attr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) .attr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) .name = "pch_firmware",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) .mode = S_IRUGO | S_IWUSR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) .size = PCH_PHUB_OROM_SIZE + 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) .read = pch_phub_bin_read,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) .write = pch_phub_bin_write,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) static int pch_phub_probe(struct pci_dev *pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) const struct pci_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) struct pch_phub_reg *chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) chip = kzalloc(sizeof(struct pch_phub_reg), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) if (chip == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) ret = pci_enable_device(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) dev_err(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) "%s : pci_enable_device FAILED(ret=%d)", __func__, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) goto err_pci_enable_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) dev_dbg(&pdev->dev, "%s : pci_enable_device returns %d\n", __func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) ret = pci_request_regions(pdev, KBUILD_MODNAME);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) dev_err(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) "%s : pci_request_regions FAILED(ret=%d)", __func__, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) goto err_req_regions;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) dev_dbg(&pdev->dev, "%s : "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) "pci_request_regions returns %d\n", __func__, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) chip->pch_phub_base_address = pci_iomap(pdev, 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) if (chip->pch_phub_base_address == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) dev_err(&pdev->dev, "%s : pci_iomap FAILED", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) goto err_pci_iomap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) dev_dbg(&pdev->dev, "%s : pci_iomap SUCCESS and value "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) "in pch_phub_base_address variable is %p\n", __func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) chip->pch_phub_base_address);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) chip->pdev = pdev; /* Save pci device struct */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) if (id->driver_data == 1) { /* EG20T PCH */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) const char *board_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) unsigned int prefetch = 0x000affaa;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) if (pdev->dev.of_node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) of_property_read_u32(pdev->dev.of_node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) "intel,eg20t-prefetch",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) &prefetch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) ret = sysfs_create_file(&pdev->dev.kobj,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) &dev_attr_pch_mac.attr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) goto err_sysfs_create;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) ret = sysfs_create_bin_file(&pdev->dev.kobj, &pch_bin_attr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) goto exit_bin_attr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) pch_phub_read_modify_write_reg(chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) (unsigned int)CLKCFG_REG_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) CLKCFG_CAN_50MHZ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) CLKCFG_CANCLK_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) /* quirk for CM-iTC board */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) board_name = dmi_get_system_info(DMI_BOARD_NAME);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) if (board_name && strstr(board_name, "CM-iTC"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) pch_phub_read_modify_write_reg(chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) (unsigned int)CLKCFG_REG_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) CLKCFG_UART_48MHZ | CLKCFG_BAUDDIV |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) CLKCFG_PLL2VCO | CLKCFG_UARTCLKSEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) CLKCFG_UART_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) /* set the prefech value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) iowrite32(prefetch, chip->pch_phub_base_address + 0x14);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) /* set the interrupt delay value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) iowrite32(0x25, chip->pch_phub_base_address + 0x44);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) chip->pch_opt_rom_start_address = PCH_PHUB_ROM_START_ADDR_EG20T;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) chip->pch_mac_start_address = PCH_PHUB_MAC_START_ADDR_EG20T;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) /* quirk for MIPS Boston platform */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) if (pdev->dev.of_node) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) if (of_machine_is_compatible("img,boston")) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) pch_phub_read_modify_write_reg(chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) (unsigned int)CLKCFG_REG_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) CLKCFG_UART_25MHZ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) CLKCFG_UART_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) } else if (id->driver_data == 2) { /* ML7213 IOH */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) ret = sysfs_create_bin_file(&pdev->dev.kobj, &pch_bin_attr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) goto err_sysfs_create;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) /* set the prefech value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) * Device2(USB OHCI #1/ USB EHCI #1/ USB Device):a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) * Device4(SDIO #0,1,2):f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) * Device6(SATA 2):f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) * Device8(USB OHCI #0/ USB EHCI #0):a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) iowrite32(0x000affa0, chip->pch_phub_base_address + 0x14);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) chip->pch_opt_rom_start_address =\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) PCH_PHUB_ROM_START_ADDR_ML7213;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) } else if (id->driver_data == 3) { /* ML7223 IOH Bus-m*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) /* set the prefech value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) * Device8(GbE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) iowrite32(0x000a0000, chip->pch_phub_base_address + 0x14);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) /* set the interrupt delay value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) iowrite32(0x25, chip->pch_phub_base_address + 0x140);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) chip->pch_opt_rom_start_address =\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) PCH_PHUB_ROM_START_ADDR_ML7223;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) chip->pch_mac_start_address = PCH_PHUB_MAC_START_ADDR_ML7223;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) } else if (id->driver_data == 4) { /* ML7223 IOH Bus-n*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) ret = sysfs_create_file(&pdev->dev.kobj,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) &dev_attr_pch_mac.attr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) goto err_sysfs_create;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) ret = sysfs_create_bin_file(&pdev->dev.kobj, &pch_bin_attr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) goto exit_bin_attr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) /* set the prefech value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) * Device2(USB OHCI #0,1,2,3/ USB EHCI #0):a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) * Device4(SDIO #0,1):f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) * Device6(SATA 2):f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) iowrite32(0x0000ffa0, chip->pch_phub_base_address + 0x14);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) chip->pch_opt_rom_start_address =\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) PCH_PHUB_ROM_START_ADDR_ML7223;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) chip->pch_mac_start_address = PCH_PHUB_MAC_START_ADDR_ML7223;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) } else if (id->driver_data == 5) { /* ML7831 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) ret = sysfs_create_file(&pdev->dev.kobj,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) &dev_attr_pch_mac.attr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) goto err_sysfs_create;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) ret = sysfs_create_bin_file(&pdev->dev.kobj, &pch_bin_attr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) goto exit_bin_attr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) /* set the prefech value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) iowrite32(0x000affaa, chip->pch_phub_base_address + 0x14);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) /* set the interrupt delay value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) iowrite32(0x25, chip->pch_phub_base_address + 0x44);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) chip->pch_opt_rom_start_address = PCH_PHUB_ROM_START_ADDR_EG20T;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) chip->pch_mac_start_address = PCH_PHUB_MAC_START_ADDR_EG20T;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) chip->ioh_type = id->driver_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) pci_set_drvdata(pdev, chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) exit_bin_attr:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) sysfs_remove_file(&pdev->dev.kobj, &dev_attr_pch_mac.attr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) err_sysfs_create:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) pci_iounmap(pdev, chip->pch_phub_base_address);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) err_pci_iomap:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) pci_release_regions(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) err_req_regions:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) pci_disable_device(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) err_pci_enable_dev:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) kfree(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) dev_err(&pdev->dev, "%s returns %d\n", __func__, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) static void pch_phub_remove(struct pci_dev *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) struct pch_phub_reg *chip = pci_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) sysfs_remove_file(&pdev->dev.kobj, &dev_attr_pch_mac.attr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) sysfs_remove_bin_file(&pdev->dev.kobj, &pch_bin_attr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) pci_iounmap(pdev, chip->pch_phub_base_address);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) pci_release_regions(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) pci_disable_device(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) kfree(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) static int __maybe_unused pch_phub_suspend(struct device *dev_d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) device_wakeup_disable(dev_d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) static int __maybe_unused pch_phub_resume(struct device *dev_d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) device_wakeup_disable(dev_d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) static const struct pci_device_id pch_phub_pcidev_id[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_PCH1_PHUB), 1, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) { PCI_VDEVICE(ROHM, PCI_DEVICE_ID_ROHM_ML7213_PHUB), 2, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) { PCI_VDEVICE(ROHM, PCI_DEVICE_ID_ROHM_ML7223_mPHUB), 3, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) { PCI_VDEVICE(ROHM, PCI_DEVICE_ID_ROHM_ML7223_nPHUB), 4, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) { PCI_VDEVICE(ROHM, PCI_DEVICE_ID_ROHM_ML7831_PHUB), 5, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) MODULE_DEVICE_TABLE(pci, pch_phub_pcidev_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) static SIMPLE_DEV_PM_OPS(pch_phub_pm_ops, pch_phub_suspend, pch_phub_resume);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) static struct pci_driver pch_phub_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) .name = "pch_phub",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) .id_table = pch_phub_pcidev_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) .probe = pch_phub_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) .remove = pch_phub_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) .driver.pm = &pch_phub_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) module_pci_driver(pch_phub_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) MODULE_DESCRIPTION("Intel EG20T PCH/LAPIS Semiconductor IOH(ML7213/ML7223) PHUB");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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