^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) // Copyright 2019 IBM Corp.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) #include <linux/sched/mm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) #include "trace.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) #include "ocxl_internal.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) int ocxl_global_mmio_read32(struct ocxl_afu *afu, size_t offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) enum ocxl_endian endian, u32 *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) if (offset > afu->config.global_mmio_size - 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #ifdef __BIG_ENDIAN__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) if (endian == OCXL_HOST_ENDIAN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) endian = OCXL_BIG_ENDIAN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) switch (endian) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) case OCXL_BIG_ENDIAN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) *val = readl_be((char *)afu->global_mmio_ptr + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) *val = readl((char *)afu->global_mmio_ptr + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) EXPORT_SYMBOL_GPL(ocxl_global_mmio_read32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) int ocxl_global_mmio_read64(struct ocxl_afu *afu, size_t offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) enum ocxl_endian endian, u64 *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) if (offset > afu->config.global_mmio_size - 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #ifdef __BIG_ENDIAN__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) if (endian == OCXL_HOST_ENDIAN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) endian = OCXL_BIG_ENDIAN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) switch (endian) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) case OCXL_BIG_ENDIAN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) *val = readq_be((char *)afu->global_mmio_ptr + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) *val = readq((char *)afu->global_mmio_ptr + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) EXPORT_SYMBOL_GPL(ocxl_global_mmio_read64);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) int ocxl_global_mmio_write32(struct ocxl_afu *afu, size_t offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) enum ocxl_endian endian, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) if (offset > afu->config.global_mmio_size - 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #ifdef __BIG_ENDIAN__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) if (endian == OCXL_HOST_ENDIAN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) endian = OCXL_BIG_ENDIAN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) switch (endian) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) case OCXL_BIG_ENDIAN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) writel_be(val, (char *)afu->global_mmio_ptr + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) writel(val, (char *)afu->global_mmio_ptr + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) EXPORT_SYMBOL_GPL(ocxl_global_mmio_write32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) int ocxl_global_mmio_write64(struct ocxl_afu *afu, size_t offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) enum ocxl_endian endian, u64 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) if (offset > afu->config.global_mmio_size - 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #ifdef __BIG_ENDIAN__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) if (endian == OCXL_HOST_ENDIAN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) endian = OCXL_BIG_ENDIAN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) switch (endian) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) case OCXL_BIG_ENDIAN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) writeq_be(val, (char *)afu->global_mmio_ptr + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) writeq(val, (char *)afu->global_mmio_ptr + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) EXPORT_SYMBOL_GPL(ocxl_global_mmio_write64);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) int ocxl_global_mmio_set32(struct ocxl_afu *afu, size_t offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) enum ocxl_endian endian, u32 mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) u32 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) if (offset > afu->config.global_mmio_size - 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #ifdef __BIG_ENDIAN__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) if (endian == OCXL_HOST_ENDIAN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) endian = OCXL_BIG_ENDIAN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) switch (endian) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) case OCXL_BIG_ENDIAN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) tmp = readl_be((char *)afu->global_mmio_ptr + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) tmp |= mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) writel_be(tmp, (char *)afu->global_mmio_ptr + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) tmp = readl((char *)afu->global_mmio_ptr + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) tmp |= mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) writel(tmp, (char *)afu->global_mmio_ptr + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) EXPORT_SYMBOL_GPL(ocxl_global_mmio_set32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) int ocxl_global_mmio_set64(struct ocxl_afu *afu, size_t offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) enum ocxl_endian endian, u64 mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) u64 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) if (offset > afu->config.global_mmio_size - 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #ifdef __BIG_ENDIAN__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) if (endian == OCXL_HOST_ENDIAN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) endian = OCXL_BIG_ENDIAN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) switch (endian) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) case OCXL_BIG_ENDIAN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) tmp = readq_be((char *)afu->global_mmio_ptr + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) tmp |= mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) writeq_be(tmp, (char *)afu->global_mmio_ptr + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) tmp = readq((char *)afu->global_mmio_ptr + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) tmp |= mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) writeq(tmp, (char *)afu->global_mmio_ptr + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) EXPORT_SYMBOL_GPL(ocxl_global_mmio_set64);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) int ocxl_global_mmio_clear32(struct ocxl_afu *afu, size_t offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) enum ocxl_endian endian, u32 mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) u32 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) if (offset > afu->config.global_mmio_size - 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #ifdef __BIG_ENDIAN__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) if (endian == OCXL_HOST_ENDIAN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) endian = OCXL_BIG_ENDIAN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) switch (endian) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) case OCXL_BIG_ENDIAN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) tmp = readl_be((char *)afu->global_mmio_ptr + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) tmp &= ~mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) writel_be(tmp, (char *)afu->global_mmio_ptr + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) tmp = readl((char *)afu->global_mmio_ptr + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) tmp &= ~mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) writel(tmp, (char *)afu->global_mmio_ptr + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) EXPORT_SYMBOL_GPL(ocxl_global_mmio_clear32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) int ocxl_global_mmio_clear64(struct ocxl_afu *afu, size_t offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) enum ocxl_endian endian, u64 mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) u64 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) if (offset > afu->config.global_mmio_size - 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #ifdef __BIG_ENDIAN__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) if (endian == OCXL_HOST_ENDIAN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) endian = OCXL_BIG_ENDIAN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) switch (endian) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) case OCXL_BIG_ENDIAN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) tmp = readq_be((char *)afu->global_mmio_ptr + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) tmp &= ~mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) writeq_be(tmp, (char *)afu->global_mmio_ptr + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) tmp = readq((char *)afu->global_mmio_ptr + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) tmp &= ~mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) writeq(tmp, (char *)afu->global_mmio_ptr + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) writeq(tmp, (char *)afu->global_mmio_ptr + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) EXPORT_SYMBOL_GPL(ocxl_global_mmio_clear64);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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