^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) // Copyright 2017 IBM Corp.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) #include <asm/pnv-ocxl.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) #include <misc/ocxl-config.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include "ocxl_internal.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #define EXTRACT_BIT(val, bit) (!!(val & BIT(bit)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #define EXTRACT_BITS(val, s, e) ((val & GENMASK(e, s)) >> s)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define OCXL_DVSEC_AFU_IDX_MASK GENMASK(5, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define OCXL_DVSEC_ACTAG_MASK GENMASK(11, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define OCXL_DVSEC_PASID_MASK GENMASK(19, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define OCXL_DVSEC_PASID_LOG_MASK GENMASK(4, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define OCXL_DVSEC_TEMPL_VERSION 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define OCXL_DVSEC_TEMPL_NAME 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define OCXL_DVSEC_TEMPL_AFU_VERSION 0x1C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define OCXL_DVSEC_TEMPL_MMIO_GLOBAL 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define OCXL_DVSEC_TEMPL_MMIO_GLOBAL_SZ 0x28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define OCXL_DVSEC_TEMPL_MMIO_PP 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define OCXL_DVSEC_TEMPL_MMIO_PP_SZ 0x38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define OCXL_DVSEC_TEMPL_ALL_MEM_SZ 0x3C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define OCXL_DVSEC_TEMPL_LPC_MEM_START 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define OCXL_DVSEC_TEMPL_WWID 0x48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define OCXL_DVSEC_TEMPL_LPC_MEM_SZ 0x58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define OCXL_MAX_AFU_PER_FUNCTION 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define OCXL_TEMPL_LEN_1_0 0x58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define OCXL_TEMPL_LEN_1_1 0x60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define OCXL_TEMPL_NAME_LEN 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define OCXL_CFG_TIMEOUT 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) static int find_dvsec(struct pci_dev *dev, int dvsec_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) int vsec = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) u16 vendor, id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) while ((vsec = pci_find_next_ext_capability(dev, vsec,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) OCXL_EXT_CAP_ID_DVSEC))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) pci_read_config_word(dev, vsec + OCXL_DVSEC_VENDOR_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) &vendor);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) pci_read_config_word(dev, vsec + OCXL_DVSEC_ID_OFFSET, &id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) if (vendor == PCI_VENDOR_ID_IBM && id == dvsec_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) return vsec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) static int find_dvsec_afu_ctrl(struct pci_dev *dev, u8 afu_idx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) int vsec = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) u16 vendor, id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) u8 idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) while ((vsec = pci_find_next_ext_capability(dev, vsec,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) OCXL_EXT_CAP_ID_DVSEC))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) pci_read_config_word(dev, vsec + OCXL_DVSEC_VENDOR_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) &vendor);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) pci_read_config_word(dev, vsec + OCXL_DVSEC_ID_OFFSET, &id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) if (vendor == PCI_VENDOR_ID_IBM &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) id == OCXL_DVSEC_AFU_CTRL_ID) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) pci_read_config_byte(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) vsec + OCXL_DVSEC_AFU_CTRL_AFU_IDX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) &idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) if (idx == afu_idx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) return vsec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) * get_function_0() - Find a related PCI device (function 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) * @device: PCI device to match
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) * Returns a pointer to the related device, or null if not found
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) static struct pci_dev *get_function_0(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) unsigned int devfn = PCI_DEVFN(PCI_SLOT(dev->devfn), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) return pci_get_domain_bus_and_slot(pci_domain_nr(dev->bus),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) dev->bus->number, devfn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) static void read_pasid(struct pci_dev *dev, struct ocxl_fn_config *fn)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) u16 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) int pos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_PASID);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) if (!pos) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) * PASID capability is not mandatory, but there
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) * shouldn't be any AFU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) dev_dbg(&dev->dev, "Function doesn't require any PASID\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) fn->max_pasid_log = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) pci_read_config_word(dev, pos + PCI_PASID_CAP, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) fn->max_pasid_log = EXTRACT_BITS(val, 8, 12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) dev_dbg(&dev->dev, "PASID capability:\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) dev_dbg(&dev->dev, " Max PASID log = %d\n", fn->max_pasid_log);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) static int read_dvsec_tl(struct pci_dev *dev, struct ocxl_fn_config *fn)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) int pos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) pos = find_dvsec(dev, OCXL_DVSEC_TL_ID);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) if (!pos && PCI_FUNC(dev->devfn) == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) dev_err(&dev->dev, "Can't find TL DVSEC\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) if (pos && PCI_FUNC(dev->devfn) != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) dev_err(&dev->dev, "TL DVSEC is only allowed on function 0\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) fn->dvsec_tl_pos = pos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) static int read_dvsec_function(struct pci_dev *dev, struct ocxl_fn_config *fn)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) int pos, afu_present;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) pos = find_dvsec(dev, OCXL_DVSEC_FUNC_ID);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) if (!pos) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) dev_err(&dev->dev, "Can't find function DVSEC\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) fn->dvsec_function_pos = pos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) pci_read_config_dword(dev, pos + OCXL_DVSEC_FUNC_OFF_INDEX, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) afu_present = EXTRACT_BIT(val, 31);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) if (!afu_present) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) fn->max_afu_index = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) dev_dbg(&dev->dev, "Function doesn't define any AFU\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) fn->max_afu_index = EXTRACT_BITS(val, 24, 29);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) dev_dbg(&dev->dev, "Function DVSEC:\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) dev_dbg(&dev->dev, " Max AFU index = %d\n", fn->max_afu_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) static int read_dvsec_afu_info(struct pci_dev *dev, struct ocxl_fn_config *fn)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) int pos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) if (fn->max_afu_index < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) fn->dvsec_afu_info_pos = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) pos = find_dvsec(dev, OCXL_DVSEC_AFU_INFO_ID);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) if (!pos) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) dev_err(&dev->dev, "Can't find AFU information DVSEC\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) fn->dvsec_afu_info_pos = pos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) static int read_dvsec_vendor(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) int pos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) u32 cfg, tlx, dlx, reset_reload;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) * vendor specific DVSEC, for IBM images only. Some older
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) * images may not have it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) * It's only used on function 0 to specify the version of some
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) * logic blocks and to give access to special registers to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) * enable host-based flashing.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) if (PCI_FUNC(dev->devfn) != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) pos = find_dvsec(dev, OCXL_DVSEC_VENDOR_ID);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) if (!pos)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) pci_read_config_dword(dev, pos + OCXL_DVSEC_VENDOR_CFG_VERS, &cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) pci_read_config_dword(dev, pos + OCXL_DVSEC_VENDOR_TLX_VERS, &tlx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) pci_read_config_dword(dev, pos + OCXL_DVSEC_VENDOR_DLX_VERS, &dlx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) pci_read_config_dword(dev, pos + OCXL_DVSEC_VENDOR_RESET_RELOAD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) &reset_reload);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) dev_dbg(&dev->dev, "Vendor specific DVSEC:\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) dev_dbg(&dev->dev, " CFG version = 0x%x\n", cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) dev_dbg(&dev->dev, " TLX version = 0x%x\n", tlx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) dev_dbg(&dev->dev, " DLX version = 0x%x\n", dlx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) dev_dbg(&dev->dev, " ResetReload = 0x%x\n", reset_reload);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) static int get_dvsec_vendor0(struct pci_dev *dev, struct pci_dev **dev0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) int *out_pos)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) int pos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) if (PCI_FUNC(dev->devfn) != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) dev = get_function_0(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) if (!dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) pos = find_dvsec(dev, OCXL_DVSEC_VENDOR_ID);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) if (!pos)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) *dev0 = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) *out_pos = pos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) int ocxl_config_get_reset_reload(struct pci_dev *dev, int *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) struct pci_dev *dev0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) u32 reset_reload;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) int pos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) if (get_dvsec_vendor0(dev, &dev0, &pos))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) pci_read_config_dword(dev0, pos + OCXL_DVSEC_VENDOR_RESET_RELOAD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) &reset_reload);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) *val = !!(reset_reload & BIT(0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) int ocxl_config_set_reset_reload(struct pci_dev *dev, int val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) struct pci_dev *dev0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) u32 reset_reload;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) int pos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) if (get_dvsec_vendor0(dev, &dev0, &pos))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) pci_read_config_dword(dev0, pos + OCXL_DVSEC_VENDOR_RESET_RELOAD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) &reset_reload);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) if (val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) reset_reload |= BIT(0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) reset_reload &= ~BIT(0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) pci_write_config_dword(dev0, pos + OCXL_DVSEC_VENDOR_RESET_RELOAD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) reset_reload);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) static int validate_function(struct pci_dev *dev, struct ocxl_fn_config *fn)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) if (fn->max_pasid_log == -1 && fn->max_afu_index >= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) dev_err(&dev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) "AFUs are defined but no PASIDs are requested\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) if (fn->max_afu_index > OCXL_MAX_AFU_PER_FUNCTION) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) dev_err(&dev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) "Max AFU index out of architectural limit (%d vs %d)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) fn->max_afu_index, OCXL_MAX_AFU_PER_FUNCTION);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) int ocxl_config_read_function(struct pci_dev *dev, struct ocxl_fn_config *fn)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) read_pasid(dev, fn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) rc = read_dvsec_tl(dev, fn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) if (rc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) dev_err(&dev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) "Invalid Transaction Layer DVSEC configuration: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) rc = read_dvsec_function(dev, fn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) if (rc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) dev_err(&dev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) "Invalid Function DVSEC configuration: %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) rc = read_dvsec_afu_info(dev, fn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) if (rc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) dev_err(&dev->dev, "Invalid AFU configuration: %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) rc = read_dvsec_vendor(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) if (rc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) dev_err(&dev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) "Invalid vendor specific DVSEC configuration: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) rc = validate_function(dev, fn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) EXPORT_SYMBOL_GPL(ocxl_config_read_function);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) static int read_afu_info(struct pci_dev *dev, struct ocxl_fn_config *fn,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) int offset, u32 *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) unsigned long timeout = jiffies + (HZ * OCXL_CFG_TIMEOUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) int pos = fn->dvsec_afu_info_pos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) /* Protect 'data valid' bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) if (EXTRACT_BIT(offset, 31)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) dev_err(&dev->dev, "Invalid offset in AFU info DVSEC\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) pci_write_config_dword(dev, pos + OCXL_DVSEC_AFU_INFO_OFF, offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) pci_read_config_dword(dev, pos + OCXL_DVSEC_AFU_INFO_OFF, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) while (!EXTRACT_BIT(val, 31)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) if (time_after_eq(jiffies, timeout)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) dev_err(&dev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) "Timeout while reading AFU info DVSEC (offset=%d)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) cpu_relax();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) pci_read_config_dword(dev, pos + OCXL_DVSEC_AFU_INFO_OFF, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) pci_read_config_dword(dev, pos + OCXL_DVSEC_AFU_INFO_DATA, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) * read_template_version() - Read the template version from the AFU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) * @dev: the device for the AFU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) * @fn: the AFU offsets
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) * @len: outputs the template length
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) * @version: outputs the major<<8,minor version
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) * Returns 0 on success, negative on failure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) static int read_template_version(struct pci_dev *dev, struct ocxl_fn_config *fn,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) u16 *len, u16 *version)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) u32 val32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) u8 major, minor;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) rc = read_afu_info(dev, fn, OCXL_DVSEC_TEMPL_VERSION, &val32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) *len = EXTRACT_BITS(val32, 16, 31);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) major = EXTRACT_BITS(val32, 8, 15);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) minor = EXTRACT_BITS(val32, 0, 7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) *version = (major << 8) + minor;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) int ocxl_config_check_afu_index(struct pci_dev *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) struct ocxl_fn_config *fn, int afu_idx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) u16 templ_version;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) u16 len, expected_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) pci_write_config_byte(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) fn->dvsec_afu_info_pos + OCXL_DVSEC_AFU_INFO_AFU_IDX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) afu_idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) rc = read_template_version(dev, fn, &len, &templ_version);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) /* AFU index map can have holes, in which case we read all 0's */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) if (!templ_version && !len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) dev_dbg(&dev->dev, "AFU descriptor template version %d.%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) templ_version >> 8, templ_version & 0xFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) switch (templ_version) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) case 0x0005: // v0.5 was used prior to the spec approval
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) case 0x0100:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) expected_len = OCXL_TEMPL_LEN_1_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) case 0x0101:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) expected_len = OCXL_TEMPL_LEN_1_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) dev_warn(&dev->dev, "Unknown AFU template version %#x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) templ_version);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) expected_len = len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) if (len != expected_len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) dev_warn(&dev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) "Unexpected template length %#x in AFU information, expected %#x for version %#x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) len, expected_len, templ_version);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) static int read_afu_name(struct pci_dev *dev, struct ocxl_fn_config *fn,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) struct ocxl_afu_config *afu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) int i, rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) u32 val, *ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) BUILD_BUG_ON(OCXL_AFU_NAME_SZ < OCXL_TEMPL_NAME_LEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) for (i = 0; i < OCXL_TEMPL_NAME_LEN; i += 4) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) rc = read_afu_info(dev, fn, OCXL_DVSEC_TEMPL_NAME + i, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) ptr = (u32 *) &afu->name[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) *ptr = le32_to_cpu((__force __le32) val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) afu->name[OCXL_AFU_NAME_SZ - 1] = '\0'; /* play safe */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) static int read_afu_mmio(struct pci_dev *dev, struct ocxl_fn_config *fn,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) struct ocxl_afu_config *afu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) * Global MMIO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) rc = read_afu_info(dev, fn, OCXL_DVSEC_TEMPL_MMIO_GLOBAL, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) afu->global_mmio_bar = EXTRACT_BITS(val, 0, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) afu->global_mmio_offset = EXTRACT_BITS(val, 16, 31) << 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) rc = read_afu_info(dev, fn, OCXL_DVSEC_TEMPL_MMIO_GLOBAL + 4, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) afu->global_mmio_offset += (u64) val << 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) rc = read_afu_info(dev, fn, OCXL_DVSEC_TEMPL_MMIO_GLOBAL_SZ, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) afu->global_mmio_size = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) * Per-process MMIO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) rc = read_afu_info(dev, fn, OCXL_DVSEC_TEMPL_MMIO_PP, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) afu->pp_mmio_bar = EXTRACT_BITS(val, 0, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) afu->pp_mmio_offset = EXTRACT_BITS(val, 16, 31) << 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) rc = read_afu_info(dev, fn, OCXL_DVSEC_TEMPL_MMIO_PP + 4, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) afu->pp_mmio_offset += (u64) val << 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) rc = read_afu_info(dev, fn, OCXL_DVSEC_TEMPL_MMIO_PP_SZ, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) afu->pp_mmio_stride = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) static int read_afu_control(struct pci_dev *dev, struct ocxl_afu_config *afu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) int pos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) u8 val8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) u16 val16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) pos = find_dvsec_afu_ctrl(dev, afu->idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) if (!pos) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) dev_err(&dev->dev, "Can't find AFU control DVSEC for AFU %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) afu->idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) afu->dvsec_afu_control_pos = pos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) pci_read_config_byte(dev, pos + OCXL_DVSEC_AFU_CTRL_PASID_SUP, &val8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) afu->pasid_supported_log = EXTRACT_BITS(val8, 0, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) pci_read_config_word(dev, pos + OCXL_DVSEC_AFU_CTRL_ACTAG_SUP, &val16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) afu->actag_supported = EXTRACT_BITS(val16, 0, 11);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) static bool char_allowed(int c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) * Permitted Characters : Alphanumeric, hyphen, underscore, comma
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) if ((c >= 0x30 && c <= 0x39) /* digits */ ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) (c >= 0x41 && c <= 0x5A) /* upper case */ ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) (c >= 0x61 && c <= 0x7A) /* lower case */ ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) c == 0 /* NULL */ ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) c == 0x2D /* - */ ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) c == 0x5F /* _ */ ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) c == 0x2C /* , */)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) static int validate_afu(struct pci_dev *dev, struct ocxl_afu_config *afu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) if (!afu->name[0]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) dev_err(&dev->dev, "Empty AFU name\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) for (i = 0; i < OCXL_TEMPL_NAME_LEN; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) if (!char_allowed(afu->name[i])) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) dev_err(&dev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) "Invalid character in AFU name\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) if (afu->global_mmio_bar != 0 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) afu->global_mmio_bar != 2 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) afu->global_mmio_bar != 4) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) dev_err(&dev->dev, "Invalid global MMIO bar number\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) if (afu->pp_mmio_bar != 0 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) afu->pp_mmio_bar != 2 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) afu->pp_mmio_bar != 4) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) dev_err(&dev->dev, "Invalid per-process MMIO bar number\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) * read_afu_lpc_memory_info() - Populate AFU metadata regarding LPC memory
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) * @dev: the device for the AFU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) * @fn: the AFU offsets
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) * @afu: the AFU struct to populate the LPC metadata into
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) * Returns 0 on success, negative on failure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) static int read_afu_lpc_memory_info(struct pci_dev *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) struct ocxl_fn_config *fn,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) struct ocxl_afu_config *afu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) u32 val32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) u16 templ_version;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) u16 templ_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) u64 total_mem_size = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) u64 lpc_mem_size = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) afu->lpc_mem_offset = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) afu->lpc_mem_size = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) afu->special_purpose_mem_offset = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) afu->special_purpose_mem_size = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) * For AFUs following template v1.0, the LPC memory covers the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) * total memory. Its size is a power of 2.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) * For AFUs with template >= v1.01, the total memory size is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) * still a power of 2, but it is split in 2 parts:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) * - the LPC memory, whose size can now be anything
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) * - the remainder memory is a special purpose memory, whose
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) * definition is AFU-dependent. It is not accessible through
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) * the usual commands for LPC memory
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) rc = read_afu_info(dev, fn, OCXL_DVSEC_TEMPL_ALL_MEM_SZ, &val32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) val32 = EXTRACT_BITS(val32, 0, 7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) if (!val32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) return 0; /* No LPC memory */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) * The configuration space spec allows for a memory size of up
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) * to 2^255 bytes.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) * Current generation hardware uses 56-bit physical addresses,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) * but we won't be able to get near close to that, as we won't
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) * have a hole big enough in the memory map. Let it pass in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) * the driver for now. We'll get an error from the firmware
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) * when trying to configure something too big.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) total_mem_size = 1ull << val32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) rc = read_afu_info(dev, fn, OCXL_DVSEC_TEMPL_LPC_MEM_START, &val32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) afu->lpc_mem_offset = val32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) rc = read_afu_info(dev, fn, OCXL_DVSEC_TEMPL_LPC_MEM_START + 4, &val32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) afu->lpc_mem_offset |= (u64) val32 << 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) rc = read_template_version(dev, fn, &templ_len, &templ_version);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) if (templ_version >= 0x0101) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) rc = read_afu_info(dev, fn,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) OCXL_DVSEC_TEMPL_LPC_MEM_SZ, &val32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) lpc_mem_size = val32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) rc = read_afu_info(dev, fn,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) OCXL_DVSEC_TEMPL_LPC_MEM_SZ + 4, &val32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) lpc_mem_size |= (u64) val32 << 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) lpc_mem_size = total_mem_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) afu->lpc_mem_size = lpc_mem_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) if (lpc_mem_size < total_mem_size) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) afu->special_purpose_mem_offset =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) afu->lpc_mem_offset + lpc_mem_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) afu->special_purpose_mem_size =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) total_mem_size - lpc_mem_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) int ocxl_config_read_afu(struct pci_dev *dev, struct ocxl_fn_config *fn,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) struct ocxl_afu_config *afu, u8 afu_idx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) u32 val32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) * First, we need to write the AFU idx for the AFU we want to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) * access.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) WARN_ON((afu_idx & OCXL_DVSEC_AFU_IDX_MASK) != afu_idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) afu->idx = afu_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) pci_write_config_byte(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) fn->dvsec_afu_info_pos + OCXL_DVSEC_AFU_INFO_AFU_IDX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) afu->idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) rc = read_afu_name(dev, fn, afu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) rc = read_afu_info(dev, fn, OCXL_DVSEC_TEMPL_AFU_VERSION, &val32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) afu->version_major = EXTRACT_BITS(val32, 24, 31);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) afu->version_minor = EXTRACT_BITS(val32, 16, 23);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) afu->afuc_type = EXTRACT_BITS(val32, 14, 15);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) afu->afum_type = EXTRACT_BITS(val32, 12, 13);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) afu->profile = EXTRACT_BITS(val32, 0, 7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) rc = read_afu_mmio(dev, fn, afu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) rc = read_afu_lpc_memory_info(dev, fn, afu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) rc = read_afu_control(dev, afu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) dev_dbg(&dev->dev, "AFU configuration:\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) dev_dbg(&dev->dev, " name = %s\n", afu->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) dev_dbg(&dev->dev, " version = %d.%d\n", afu->version_major,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) afu->version_minor);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) dev_dbg(&dev->dev, " global mmio bar = %hhu\n", afu->global_mmio_bar);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) dev_dbg(&dev->dev, " global mmio offset = %#llx\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) afu->global_mmio_offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) dev_dbg(&dev->dev, " global mmio size = %#x\n", afu->global_mmio_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) dev_dbg(&dev->dev, " pp mmio bar = %hhu\n", afu->pp_mmio_bar);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) dev_dbg(&dev->dev, " pp mmio offset = %#llx\n", afu->pp_mmio_offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) dev_dbg(&dev->dev, " pp mmio stride = %#x\n", afu->pp_mmio_stride);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) dev_dbg(&dev->dev, " lpc_mem offset = %#llx\n", afu->lpc_mem_offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) dev_dbg(&dev->dev, " lpc_mem size = %#llx\n", afu->lpc_mem_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) dev_dbg(&dev->dev, " special purpose mem offset = %#llx\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) afu->special_purpose_mem_offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) dev_dbg(&dev->dev, " special purpose mem size = %#llx\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) afu->special_purpose_mem_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) dev_dbg(&dev->dev, " pasid supported (log) = %u\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) afu->pasid_supported_log);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) dev_dbg(&dev->dev, " actag supported = %u\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) afu->actag_supported);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) rc = validate_afu(dev, afu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) EXPORT_SYMBOL_GPL(ocxl_config_read_afu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) int ocxl_config_get_actag_info(struct pci_dev *dev, u16 *base, u16 *enabled,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) u16 *supported)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) * This is really a simple wrapper for the kernel API, to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) * avoid an external driver using ocxl as a library to call
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) * platform-dependent code
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) rc = pnv_ocxl_get_actag(dev, base, enabled, supported);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) if (rc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) dev_err(&dev->dev, "Can't get actag for device: %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) EXPORT_SYMBOL_GPL(ocxl_config_get_actag_info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) void ocxl_config_set_afu_actag(struct pci_dev *dev, int pos, int actag_base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) int actag_count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) u16 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) val = actag_count & OCXL_DVSEC_ACTAG_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) pci_write_config_byte(dev, pos + OCXL_DVSEC_AFU_CTRL_ACTAG_EN, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) val = actag_base & OCXL_DVSEC_ACTAG_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) pci_write_config_dword(dev, pos + OCXL_DVSEC_AFU_CTRL_ACTAG_BASE, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) EXPORT_SYMBOL_GPL(ocxl_config_set_afu_actag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) int ocxl_config_get_pasid_info(struct pci_dev *dev, int *count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) return pnv_ocxl_get_pasid_count(dev, count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) void ocxl_config_set_afu_pasid(struct pci_dev *dev, int pos, int pasid_base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) u32 pasid_count_log)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) u8 val8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) u32 val32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) val8 = pasid_count_log & OCXL_DVSEC_PASID_LOG_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) pci_write_config_byte(dev, pos + OCXL_DVSEC_AFU_CTRL_PASID_EN, val8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) pci_read_config_dword(dev, pos + OCXL_DVSEC_AFU_CTRL_PASID_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) &val32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) val32 &= ~OCXL_DVSEC_PASID_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) val32 |= pasid_base & OCXL_DVSEC_PASID_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) pci_write_config_dword(dev, pos + OCXL_DVSEC_AFU_CTRL_PASID_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) val32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) EXPORT_SYMBOL_GPL(ocxl_config_set_afu_pasid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) void ocxl_config_set_afu_state(struct pci_dev *dev, int pos, int enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) pci_read_config_byte(dev, pos + OCXL_DVSEC_AFU_CTRL_ENABLE, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) if (enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) val |= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) val &= 0xFE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) pci_write_config_byte(dev, pos + OCXL_DVSEC_AFU_CTRL_ENABLE, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) EXPORT_SYMBOL_GPL(ocxl_config_set_afu_state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) int ocxl_config_set_TL(struct pci_dev *dev, int tl_dvsec)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) __be32 *be32ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) u8 timers;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) int i, rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) long recv_cap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) char *recv_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) * Skip on function != 0, as the TL can only be defined on 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) if (PCI_FUNC(dev->devfn) != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) recv_rate = kzalloc(PNV_OCXL_TL_RATE_BUF_SIZE, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) if (!recv_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) * The spec defines 64 templates for messages in the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) * Transaction Layer (TL).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) * The host and device each support a subset, so we need to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) * configure the transmitters on each side to send only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) * templates the receiver understands, at a rate the receiver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) * can process. Per the spec, template 0 must be supported by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) * everybody. That's the template which has been used by the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) * host and device so far.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) * The sending rate limit must be set before the template is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) * enabled.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) * Device -> host
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) rc = pnv_ocxl_get_tl_cap(dev, &recv_cap, recv_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) PNV_OCXL_TL_RATE_BUF_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) for (i = 0; i < PNV_OCXL_TL_RATE_BUF_SIZE; i += 4) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) be32ptr = (__be32 *) &recv_rate[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) pci_write_config_dword(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) tl_dvsec + OCXL_DVSEC_TL_SEND_RATE + i,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) be32_to_cpu(*be32ptr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) val = recv_cap >> 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) pci_write_config_dword(dev, tl_dvsec + OCXL_DVSEC_TL_SEND_CAP, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) val = recv_cap & GENMASK(31, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) pci_write_config_dword(dev, tl_dvsec + OCXL_DVSEC_TL_SEND_CAP + 4, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) * Host -> device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) for (i = 0; i < PNV_OCXL_TL_RATE_BUF_SIZE; i += 4) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) pci_read_config_dword(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) tl_dvsec + OCXL_DVSEC_TL_RECV_RATE + i,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) be32ptr = (__be32 *) &recv_rate[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) *be32ptr = cpu_to_be32(val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) pci_read_config_dword(dev, tl_dvsec + OCXL_DVSEC_TL_RECV_CAP, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) recv_cap = (long) val << 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) pci_read_config_dword(dev, tl_dvsec + OCXL_DVSEC_TL_RECV_CAP + 4, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) recv_cap |= val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) rc = pnv_ocxl_set_tl_conf(dev, recv_cap, __pa(recv_rate),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) PNV_OCXL_TL_RATE_BUF_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) * Opencapi commands needing to be retried are classified per
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) * the TL in 2 groups: short and long commands.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) * The short back off timer it not used for now. It will be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) * for opencapi 4.0.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) * The long back off timer is typically used when an AFU hits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) * a page fault but the NPU is already processing one. So the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) * AFU needs to wait before it can resubmit. Having a value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) * too low doesn't break anything, but can generate extra
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) * traffic on the link.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) * We set it to 1.6 us for now. It's shorter than, but in the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) * same order of magnitude as the time spent to process a page
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) * fault.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) timers = 0x2 << 4; /* long timer = 1.6 us */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) pci_write_config_byte(dev, tl_dvsec + OCXL_DVSEC_TL_BACKOFF_TIMERS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) timers);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) rc = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) kfree(recv_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) EXPORT_SYMBOL_GPL(ocxl_config_set_TL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) int ocxl_config_terminate_pasid(struct pci_dev *dev, int afu_control, int pasid)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) unsigned long timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) pci_read_config_dword(dev, afu_control + OCXL_DVSEC_AFU_CTRL_TERM_PASID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) if (EXTRACT_BIT(val, 20)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) dev_err(&dev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) "Can't terminate PASID %#x, previous termination didn't complete\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) pasid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) val &= ~OCXL_DVSEC_PASID_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) val |= pasid & OCXL_DVSEC_PASID_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) val |= BIT(20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) pci_write_config_dword(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) afu_control + OCXL_DVSEC_AFU_CTRL_TERM_PASID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) timeout = jiffies + (HZ * OCXL_CFG_TIMEOUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) pci_read_config_dword(dev, afu_control + OCXL_DVSEC_AFU_CTRL_TERM_PASID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) while (EXTRACT_BIT(val, 20)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) if (time_after_eq(jiffies, timeout)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) dev_err(&dev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) "Timeout while waiting for AFU to terminate PASID %#x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) pasid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) cpu_relax();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) pci_read_config_dword(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) afu_control + OCXL_DVSEC_AFU_CTRL_TERM_PASID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) EXPORT_SYMBOL_GPL(ocxl_config_terminate_pasid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) void ocxl_config_set_actag(struct pci_dev *dev, int func_dvsec, u32 tag_first,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) u32 tag_count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) val = (tag_first & OCXL_DVSEC_ACTAG_MASK) << 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) val |= tag_count & OCXL_DVSEC_ACTAG_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) pci_write_config_dword(dev, func_dvsec + OCXL_DVSEC_FUNC_OFF_ACTAG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) EXPORT_SYMBOL_GPL(ocxl_config_set_actag);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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