Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * Copyright (c) 2013-2016, Intel Corporation. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  * Intel Management Engine Interface (Intel MEI) Linux driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) #ifndef _MEI_HW_TXE_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) #define _MEI_HW_TXE_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/irqreturn.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include "hw.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include "hw-txe-regs.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define MEI_TXI_RPM_TIMEOUT    500 /* ms */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) /* Flatten Hierarchy interrupt cause */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define TXE_INTR_READINESS_BIT  0 /* HISR_INT_0_STS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define TXE_INTR_READINESS      HISR_INT_0_STS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define TXE_INTR_ALIVENESS_BIT  1 /* HISR_INT_1_STS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define TXE_INTR_ALIVENESS      HISR_INT_1_STS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define TXE_INTR_OUT_DB_BIT     2 /* HISR_INT_2_STS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define TXE_INTR_OUT_DB         HISR_INT_2_STS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define TXE_INTR_IN_READY_BIT   8 /* beyond HISR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define TXE_INTR_IN_READY       BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)  * struct mei_txe_hw - txe hardware specifics
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)  * @mem_addr:            SeC and BRIDGE bars
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)  * @aliveness:           aliveness (power gating) state of the hardware
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)  * @readiness:           readiness state of the hardware
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)  * @slots:               number of empty slots
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)  * @wait_aliveness_resp: aliveness wait queue
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)  * @intr_cause:          translated interrupt cause
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) struct mei_txe_hw {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 	void __iomem * const *mem_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 	u32 aliveness;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 	u32 readiness;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 	u32 slots;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 	wait_queue_head_t wait_aliveness_resp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) 	unsigned long intr_cause;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define to_txe_hw(dev) (struct mei_txe_hw *)((dev)->hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) static inline struct mei_device *hw_txe_to_mei(struct mei_txe_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) 	return container_of((void *)hw, struct mei_device, hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) struct mei_device *mei_txe_dev_init(struct pci_dev *pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) irqreturn_t mei_txe_irq_quick_handler(int irq, void *dev_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) irqreturn_t mei_txe_irq_thread_handler(int irq, void *dev_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) int mei_txe_aliveness_set_sync(struct mei_device *dev, u32 req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) int mei_txe_setup_satt2(struct mei_device *dev, phys_addr_t addr, u32 range);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #endif /* _MEI_HW_TXE_H_ */