^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2013-2014, Intel Corporation. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Intel Management Engine Interface (Intel MEI) Linux driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #ifndef _MEI_HW_TXE_REGS_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #define _MEI_HW_TXE_REGS_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include "hw.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define SEC_ALIVENESS_TIMER_TIMEOUT (5 * MSEC_PER_SEC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define SEC_ALIVENESS_WAIT_TIMEOUT (1 * MSEC_PER_SEC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define SEC_RESET_WAIT_TIMEOUT (1 * MSEC_PER_SEC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define SEC_READY_WAIT_TIMEOUT (5 * MSEC_PER_SEC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define START_MESSAGE_RESPONSE_WAIT_TIMEOUT (5 * MSEC_PER_SEC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define RESET_CANCEL_WAIT_TIMEOUT (1 * MSEC_PER_SEC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) SEC_BAR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) BRIDGE_BAR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) NUM_OF_MEM_BARS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) /* SeC FW Status Register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) * FW uses this register in order to report its status to host.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) * This register resides in PCI-E config space.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define PCI_CFG_TXE_FW_STS0 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) # define PCI_CFG_TXE_FW_STS0_WRK_ST_MSK 0x0000000F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) # define PCI_CFG_TXE_FW_STS0_OP_ST_MSK 0x000001C0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) # define PCI_CFG_TXE_FW_STS0_FW_INIT_CMPLT 0x00000200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) # define PCI_CFG_TXE_FW_STS0_ERR_CODE_MSK 0x0000F000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) # define PCI_CFG_TXE_FW_STS0_OP_MODE_MSK 0x000F0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) # define PCI_CFG_TXE_FW_STS0_RST_CNT_MSK 0x00F00000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define PCI_CFG_TXE_FW_STS1 0x48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define IPC_BASE_ADDR 0x80400 /* SeC IPC Base Address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) /* IPC Input Doorbell Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define SEC_IPC_INPUT_DOORBELL_REG (0x0000 + IPC_BASE_ADDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) /* IPC Input Status Register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) * This register indicates whether or not processing of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) * the most recent command has been completed by the SEC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) * New commands and payloads should not be written by the Host
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) * until this indicates that the previous command has been processed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define SEC_IPC_INPUT_STATUS_REG (0x0008 + IPC_BASE_ADDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) # define SEC_IPC_INPUT_STATUS_RDY BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) /* IPC Host Interrupt Status Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define SEC_IPC_HOST_INT_STATUS_REG (0x0010 + IPC_BASE_ADDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define SEC_IPC_HOST_INT_STATUS_OUT_DB BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define SEC_IPC_HOST_INT_STATUS_IN_RDY BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define SEC_IPC_HOST_INT_STATUS_HDCP_M0_RCVD BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define SEC_IPC_HOST_INT_STATUS_ILL_MEM_ACCESS BIT(17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define SEC_IPC_HOST_INT_STATUS_AES_HKEY_ERR BIT(18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define SEC_IPC_HOST_INT_STATUS_DES_HKEY_ERR BIT(19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define SEC_IPC_HOST_INT_STATUS_TMRMTB_OVERFLOW BIT(21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) /* Convenient mask for pending interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define SEC_IPC_HOST_INT_STATUS_PENDING \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) (SEC_IPC_HOST_INT_STATUS_OUT_DB| \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) SEC_IPC_HOST_INT_STATUS_IN_RDY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) /* IPC Host Interrupt Mask Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define SEC_IPC_HOST_INT_MASK_REG (0x0014 + IPC_BASE_ADDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) # define SEC_IPC_HOST_INT_MASK_OUT_DB BIT(0) /* Output Doorbell Int Mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) # define SEC_IPC_HOST_INT_MASK_IN_RDY BIT(1) /* Input Ready Int Mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) /* IPC Input Payload RAM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define SEC_IPC_INPUT_PAYLOAD_REG (0x0100 + IPC_BASE_ADDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) /* IPC Shared Payload RAM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define IPC_SHARED_PAYLOAD_REG (0x0200 + IPC_BASE_ADDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) /* SeC Address Translation Table Entry 2 - Ctrl
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) * This register resides also in SeC's PCI-E Memory space.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define SATT2_CTRL_REG 0x1040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) # define SATT2_CTRL_VALID_MSK BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) # define SATT2_CTRL_BR_BASE_ADDR_REG_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) # define SATT2_CTRL_BRIDGE_HOST_EN_MSK BIT(12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) /* SATT Table Entry 2 SAP Base Address Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define SATT2_SAP_BA_REG 0x1044
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) /* SATT Table Entry 2 SAP Size Register. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define SATT2_SAP_SIZE_REG 0x1048
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) /* SATT Table Entry 2 SAP Bridge Address - LSB Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define SATT2_BRG_BA_LSB_REG 0x104C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) /* Host High-level Interrupt Status Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define HHISR_REG 0x2020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) /* Host High-level Interrupt Enable Register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) * Resides in PCI memory space. This is the top hierarchy for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) * interrupts from SeC to host, aggregating both interrupts that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) * arrive through HICR registers as well as interrupts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) * that arrive via IPC.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define HHIER_REG 0x2024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define IPC_HHIER_SEC BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define IPC_HHIER_BRIDGE BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define IPC_HHIER_MSK (IPC_HHIER_SEC | IPC_HHIER_BRIDGE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) /* Host High-level Interrupt Mask Register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) * Resides in PCI memory space.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) * This is the top hierarchy for masking interrupts from SeC to host.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define HHIMR_REG 0x2028
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define IPC_HHIMR_SEC BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define IPC_HHIMR_BRIDGE BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) /* Host High-level IRQ Status Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define HHIRQSR_REG 0x202C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) /* Host Interrupt Cause Register 0 - SeC IPC Readiness
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) * This register is both an ICR to Host from PCI Memory Space
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) * and it is also exposed in the SeC memory space.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) * This register is used by SeC's IPC driver in order
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) * to synchronize with host about IPC interface state.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define HICR_SEC_IPC_READINESS_REG 0x2040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define HICR_SEC_IPC_READINESS_HOST_RDY BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define HICR_SEC_IPC_READINESS_SEC_RDY BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define HICR_SEC_IPC_READINESS_SYS_RDY \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) (HICR_SEC_IPC_READINESS_HOST_RDY | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) HICR_SEC_IPC_READINESS_SEC_RDY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define HICR_SEC_IPC_READINESS_RDY_CLR BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) /* Host Interrupt Cause Register 1 - Aliveness Response */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) /* This register is both an ICR to Host from PCI Memory Space
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) * and it is also exposed in the SeC memory space.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) * The register may be used by SeC to ACK a host request for aliveness.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define HICR_HOST_ALIVENESS_RESP_REG 0x2044
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define HICR_HOST_ALIVENESS_RESP_ACK BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) /* Host Interrupt Cause Register 2 - SeC IPC Output Doorbell */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define HICR_SEC_IPC_OUTPUT_DOORBELL_REG 0x2048
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) /* Host Interrupt Status Register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) * Resides in PCI memory space.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) * This is the main register involved in generating interrupts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) * from SeC to host via HICRs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) * The interrupt generation rules are as follows:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) * An interrupt will be generated whenever for any i,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) * there is a transition from a state where at least one of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) * the following conditions did not hold, to a state where
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) * ALL the following conditions hold:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) * A) HISR.INT[i]_STS == 1.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) * B) HIER.INT[i]_EN == 1.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define HISR_REG 0x2060
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define HISR_INT_0_STS BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define HISR_INT_1_STS BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define HISR_INT_2_STS BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define HISR_INT_3_STS BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define HISR_INT_4_STS BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define HISR_INT_5_STS BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define HISR_INT_6_STS BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define HISR_INT_7_STS BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define HISR_INT_STS_MSK \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) (HISR_INT_0_STS | HISR_INT_1_STS | HISR_INT_2_STS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) /* Host Interrupt Enable Register. Resides in PCI memory space. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define HIER_REG 0x2064
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define HIER_INT_0_EN BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define HIER_INT_1_EN BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define HIER_INT_2_EN BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define HIER_INT_3_EN BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define HIER_INT_4_EN BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define HIER_INT_5_EN BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define HIER_INT_6_EN BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define HIER_INT_7_EN BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define HIER_INT_EN_MSK \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) (HIER_INT_0_EN | HIER_INT_1_EN | HIER_INT_2_EN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) /* SEC Memory Space IPC output payload.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) * This register is part of the output payload which SEC provides to host.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define BRIDGE_IPC_OUTPUT_PAYLOAD_REG 0x20C0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) /* SeC Interrupt Cause Register - Host Aliveness Request
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) * This register is both an ICR to SeC and it is also exposed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) * in the host-visible PCI memory space.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) * The register is used by host to request SeC aliveness.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define SICR_HOST_ALIVENESS_REQ_REG 0x214C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define SICR_HOST_ALIVENESS_REQ_REQUESTED BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) /* SeC Interrupt Cause Register - Host IPC Readiness
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) * This register is both an ICR to SeC and it is also exposed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) * in the host-visible PCI memory space.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) * This register is used by the host's SeC driver uses in order
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) * to synchronize with SeC about IPC interface state.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define SICR_HOST_IPC_READINESS_REQ_REG 0x2150
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #define SICR_HOST_IPC_READINESS_HOST_RDY BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #define SICR_HOST_IPC_READINESS_SEC_RDY BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #define SICR_HOST_IPC_READINESS_SYS_RDY \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) (SICR_HOST_IPC_READINESS_HOST_RDY | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) SICR_HOST_IPC_READINESS_SEC_RDY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #define SICR_HOST_IPC_READINESS_RDY_CLR BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) /* SeC Interrupt Cause Register - SeC IPC Output Status
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) * This register indicates whether or not processing of the most recent
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) * command has been completed by the Host.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) * New commands and payloads should not be written by SeC until this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) * register indicates that the previous command has been processed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #define SICR_SEC_IPC_OUTPUT_STATUS_REG 0x2154
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) # define SEC_IPC_OUTPUT_STATUS_RDY BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) /* MEI IPC Message payload size 64 bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) #define PAYLOAD_SIZE 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) /* MAX size for SATT range 32MB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) #define SATT_RANGE_MAX (32 << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) #endif /* _MEI_HW_TXE_REGS_H_ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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