^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2012-2020, Intel Corporation. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Intel Management Engine Interface (Intel MEI) Linux driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #ifndef _MEI_INTERFACE_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #define _MEI_INTERFACE_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/irqreturn.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/mei.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include "mei_dev.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include "client.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * mei_cfg - mei device configuration
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * @fw_status: FW status
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) * @quirk_probe: device exclusion quirk
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * @kind: MEI head kind
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) * @dma_size: device DMA buffers size
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) * @fw_ver_supported: is fw version retrievable from FW
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * @hw_trc_supported: does the hw support trc register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) struct mei_cfg {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) const struct mei_fw_status fw_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) bool (*quirk_probe)(const struct pci_dev *pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) const char *kind;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) size_t dma_size[DMA_DSCR_NUM];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) u32 fw_ver_supported:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) u32 hw_trc_supported:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define MEI_PCI_DEVICE(dev, cfg) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) .vendor = PCI_VENDOR_ID_INTEL, .device = (dev), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) .driver_data = (kernel_ulong_t)(cfg),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define MEI_ME_RPM_TIMEOUT 500 /* ms */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) * struct mei_me_hw - me hw specific data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) * @cfg: per device generation config and ops
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) * @mem_addr: io memory address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) * @irq: irq number
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) * @pg_state: power gating state
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) * @d0i3_supported: di03 support
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) * @hbuf_depth: depth of hardware host/write buffer in slots
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) * @read_fws: read FW status register handler
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) struct mei_me_hw {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) const struct mei_cfg *cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) void __iomem *mem_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) enum mei_pg_state pg_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) bool d0i3_supported;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) u8 hbuf_depth;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) int (*read_fws)(const struct mei_device *dev, int where, u32 *val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define to_me_hw(dev) (struct mei_me_hw *)((dev)->hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) * enum mei_cfg_idx - indices to platform specific configurations.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) * Note: has to be synchronized with mei_cfg_list[]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) * @MEI_ME_UNDEF_CFG: Lower sentinel.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) * @MEI_ME_ICH_CFG: I/O Controller Hub legacy devices.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) * @MEI_ME_ICH10_CFG: I/O Controller Hub platforms Gen10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) * @MEI_ME_PCH6_CFG: Platform Controller Hub platforms (Gen6).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) * @MEI_ME_PCH7_CFG: Platform Controller Hub platforms (Gen7).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) * @MEI_ME_PCH_CPT_PBG_CFG:Platform Controller Hub workstations
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) * with quirk for Node Manager exclusion.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) * @MEI_ME_PCH8_CFG: Platform Controller Hub Gen8 and newer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) * client platforms.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) * @MEI_ME_PCH8_ITOUCH_CFG:Platform Controller Hub Gen8 and newer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) * client platforms (iTouch).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) * @MEI_ME_PCH8_SPS_4_CFG: Platform Controller Hub Gen8 and newer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) * servers platforms with quirk for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) * SPS firmware exclusion.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) * @MEI_ME_PCH12_CFG: Platform Controller Hub Gen12 and newer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) * @MEI_ME_PCH12_SPS_4_CFG:Platform Controller Hub Gen12 up to 4.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) * servers platforms with quirk for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) * SPS firmware exclusion.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) * @MEI_ME_PCH12_SPS_CFG: Platform Controller Hub Gen12 5.0 and newer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) * servers platforms with quirk for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) * SPS firmware exclusion.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) * @MEI_ME_PCH15_CFG: Platform Controller Hub Gen15 and newer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) * @MEI_ME_PCH15_SPS_CFG: Platform Controller Hub Gen15 and newer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) * servers platforms with quirk for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) * SPS firmware exclusion.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) * @MEI_ME_NUM_CFG: Upper Sentinel.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) enum mei_cfg_idx {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) MEI_ME_UNDEF_CFG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) MEI_ME_ICH_CFG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) MEI_ME_ICH10_CFG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) MEI_ME_PCH6_CFG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) MEI_ME_PCH7_CFG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) MEI_ME_PCH_CPT_PBG_CFG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) MEI_ME_PCH8_CFG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) MEI_ME_PCH8_ITOUCH_CFG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) MEI_ME_PCH8_SPS_4_CFG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) MEI_ME_PCH12_CFG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) MEI_ME_PCH12_SPS_4_CFG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) MEI_ME_PCH12_SPS_CFG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) MEI_ME_PCH12_SPS_ITOUCH_CFG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) MEI_ME_PCH15_CFG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) MEI_ME_PCH15_SPS_CFG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) MEI_ME_NUM_CFG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) const struct mei_cfg *mei_me_get_cfg(kernel_ulong_t idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) struct mei_device *mei_me_dev_init(struct device *parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) const struct mei_cfg *cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) int mei_me_pg_enter_sync(struct mei_device *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) int mei_me_pg_exit_sync(struct mei_device *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) irqreturn_t mei_me_irq_quick_handler(int irq, void *dev_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) irqreturn_t mei_me_irq_thread_handler(int irq, void *dev_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #endif /* _MEI_INTERFACE_H_ */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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