Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Copyright(c) 2016-2018 Intel Corporation. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5) #include <linux/dma-mapping.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) #include <linux/mei.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #include "mei_dev.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11)  * mei_dmam_dscr_alloc() - allocate a managed coherent buffer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12)  *     for the dma descriptor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13)  * @dev: mei_device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14)  * @dscr: dma descriptor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16)  * Return:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17)  * * 0       - on success or zero allocation request
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18)  * * -EINVAL - if size is not power of 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19)  * * -ENOMEM - of allocation has failed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) static int mei_dmam_dscr_alloc(struct mei_device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) 			       struct mei_dma_dscr *dscr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) 	if (!dscr->size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 	if (WARN_ON(!is_power_of_2(dscr->size)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 	if (dscr->vaddr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 	dscr->vaddr = dmam_alloc_coherent(dev->dev, dscr->size, &dscr->daddr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 					  GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 	if (!dscr->vaddr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42)  * mei_dmam_dscr_free() - free a managed coherent buffer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43)  *     from the dma descriptor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44)  * @dev: mei_device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45)  * @dscr: dma descriptor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) static void mei_dmam_dscr_free(struct mei_device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 			       struct mei_dma_dscr *dscr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 	if (!dscr->vaddr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 	dmam_free_coherent(dev->dev, dscr->size, dscr->vaddr, dscr->daddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 	dscr->vaddr = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58)  * mei_dmam_ring_free() - free dma ring buffers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59)  * @dev: mei device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) void mei_dmam_ring_free(struct mei_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 	int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	for (i = 0; i < DMA_DSCR_NUM; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 		mei_dmam_dscr_free(dev, &dev->dr_dscr[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70)  * mei_dmam_ring_alloc() - allocate dma ring buffers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71)  * @dev: mei device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73)  * Return: -ENOMEM on allocation failure 0 otherwise
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) int mei_dmam_ring_alloc(struct mei_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	for (i = 0; i < DMA_DSCR_NUM; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 		if (mei_dmam_dscr_alloc(dev, &dev->dr_dscr[i]))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 			goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	mei_dmam_ring_free(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91)  * mei_dma_ring_is_allocated() - check if dma ring is allocated
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92)  * @dev: mei device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94)  * Return: true if dma ring is allocated
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) bool mei_dma_ring_is_allocated(struct mei_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	return !!dev->dr_dscr[DMA_DSCR_HOST].vaddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) static inline
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) struct hbm_dma_ring_ctrl *mei_dma_ring_ctrl(struct mei_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	return (struct hbm_dma_ring_ctrl *)dev->dr_dscr[DMA_DSCR_CTRL].vaddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)  * mei_dma_ring_reset() - reset the dma control block
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)  * @dev: mei device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) void mei_dma_ring_reset(struct mei_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	struct hbm_dma_ring_ctrl *ctrl = mei_dma_ring_ctrl(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	if (!ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	memset(ctrl, 0, sizeof(*ctrl));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)  * mei_dma_copy_from() - copy from dma ring into buffer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)  * @dev: mei device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)  * @buf: data buffer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)  * @offset: offset in slots.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)  * @n: number of slots to copy.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) static size_t mei_dma_copy_from(struct mei_device *dev, unsigned char *buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 				u32 offset, u32 n)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	unsigned char *dbuf = dev->dr_dscr[DMA_DSCR_DEVICE].vaddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	size_t b_offset = offset << 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	size_t b_n = n << 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	memcpy(buf, dbuf + b_offset, b_n);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	return b_n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)  * mei_dma_copy_to() - copy to a buffer to the dma ring
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)  * @dev: mei device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)  * @buf: data buffer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)  * @offset: offset in slots.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)  * @n: number of slots to copy.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) static size_t mei_dma_copy_to(struct mei_device *dev, unsigned char *buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 			      u32 offset, u32 n)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	unsigned char *hbuf = dev->dr_dscr[DMA_DSCR_HOST].vaddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	size_t b_offset = offset << 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	size_t b_n = n << 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	memcpy(hbuf + b_offset, buf, b_n);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	return b_n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)  * mei_dma_ring_read() - read data from the ring
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)  * @dev: mei device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)  * @buf: buffer to read into: may be NULL in case of droping the data.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)  * @len: length to read.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) void mei_dma_ring_read(struct mei_device *dev, unsigned char *buf, u32 len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	struct hbm_dma_ring_ctrl *ctrl = mei_dma_ring_ctrl(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	u32 dbuf_depth;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	u32 rd_idx, rem, slots;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	if (WARN_ON(!ctrl))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	dev_dbg(dev->dev, "reading from dma %u bytes\n", len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	if (!len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	dbuf_depth = dev->dr_dscr[DMA_DSCR_DEVICE].size >> 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	rd_idx = READ_ONCE(ctrl->dbuf_rd_idx) & (dbuf_depth - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	slots = mei_data2slots(len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	/* if buf is NULL we drop the packet by advancing the pointer.*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	if (!buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 		goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	if (rd_idx + slots > dbuf_depth) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 		buf += mei_dma_copy_from(dev, buf, rd_idx, dbuf_depth - rd_idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 		rem = slots - (dbuf_depth - rd_idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 		rd_idx = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 		rem = slots;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	mei_dma_copy_from(dev, buf, rd_idx, rem);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	WRITE_ONCE(ctrl->dbuf_rd_idx, ctrl->dbuf_rd_idx + slots);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) static inline u32 mei_dma_ring_hbuf_depth(struct mei_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	return dev->dr_dscr[DMA_DSCR_HOST].size >> 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)  * mei_dma_ring_empty_slots() - calaculate number of empty slots in dma ring
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)  * @dev: mei_device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)  * Return: number of empty slots
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) u32 mei_dma_ring_empty_slots(struct mei_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 	struct hbm_dma_ring_ctrl *ctrl = mei_dma_ring_ctrl(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	u32 wr_idx, rd_idx, hbuf_depth, empty;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 	if (!mei_dma_ring_is_allocated(dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	if (WARN_ON(!ctrl))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 	/* easier to work in slots */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 	hbuf_depth = mei_dma_ring_hbuf_depth(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 	rd_idx = READ_ONCE(ctrl->hbuf_rd_idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 	wr_idx = READ_ONCE(ctrl->hbuf_wr_idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	if (rd_idx > wr_idx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 		empty = rd_idx - wr_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 		empty = hbuf_depth - (wr_idx - rd_idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 	return empty;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)  * mei_dma_ring_write - write data to dma ring host buffer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)  * @dev: mei_device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)  * @buf: data will be written
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)  * @len: data length
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) void mei_dma_ring_write(struct mei_device *dev, unsigned char *buf, u32 len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 	struct hbm_dma_ring_ctrl *ctrl = mei_dma_ring_ctrl(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 	u32 hbuf_depth;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 	u32 wr_idx, rem, slots;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 	if (WARN_ON(!ctrl))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 	dev_dbg(dev->dev, "writing to dma %u bytes\n", len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 	hbuf_depth = mei_dma_ring_hbuf_depth(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 	wr_idx = READ_ONCE(ctrl->hbuf_wr_idx) & (hbuf_depth - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 	slots = mei_data2slots(len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 	if (wr_idx + slots > hbuf_depth) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 		buf += mei_dma_copy_to(dev, buf, wr_idx, hbuf_depth - wr_idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 		rem = slots - (hbuf_depth - wr_idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 		wr_idx = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 		rem = slots;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 	mei_dma_copy_to(dev, buf, wr_idx, rem);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 	WRITE_ONCE(ctrl->hbuf_wr_idx, ctrl->hbuf_wr_idx + slots);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) }