Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /* SPDX-License-Identifier: GPL-2.0-or-later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  *  lis3lv02d.h - ST LIS3LV02DL accelerometer driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  *  Copyright (C) 2007-2008 Yan Burman
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  *  Copyright (C) 2008-2009 Eric Piel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/input.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/regulator/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/miscdevice.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14)  * This driver tries to support the "digital" accelerometer chips from
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15)  * STMicroelectronics such as LIS3LV02DL, LIS302DL, LIS3L02DQ, LIS331DL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16)  * LIS331DLH, LIS35DE, or LIS202DL. They are very similar in terms of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17)  * programming, with almost the same registers. In addition to differing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18)  * on physical properties, they differ on the number of axes (2/3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19)  * precision (8/12 bits), and special features (freefall detection,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20)  * click...). Unfortunately, not all the differences can be probed via
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21)  * a register. They can be connected either via I²C or SPI.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #include <linux/lis3lv02d.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) enum lis3_reg {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 	WHO_AM_I	= 0x0F,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 	OFFSET_X	= 0x16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 	OFFSET_Y	= 0x17,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 	OFFSET_Z	= 0x18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 	GAIN_X		= 0x19,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 	GAIN_Y		= 0x1A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 	GAIN_Z		= 0x1B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 	CTRL_REG1	= 0x20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 	CTRL_REG2	= 0x21,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 	CTRL_REG3	= 0x22,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 	CTRL_REG4	= 0x23,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 	HP_FILTER_RESET	= 0x23,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 	STATUS_REG	= 0x27,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 	OUTX_L		= 0x28,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 	OUTX_H		= 0x29,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 	OUTX		= 0x29,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 	OUTY_L		= 0x2A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 	OUTY_H		= 0x2B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 	OUTY		= 0x2B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 	OUTZ_L		= 0x2C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 	OUTZ_H		= 0x2D,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 	OUTZ		= 0x2D,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) enum lis302d_reg {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 	FF_WU_CFG_1	= 0x30,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 	FF_WU_SRC_1	= 0x31,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 	FF_WU_THS_1	= 0x32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 	FF_WU_DURATION_1 = 0x33,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 	FF_WU_CFG_2	= 0x34,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 	FF_WU_SRC_2	= 0x35,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 	FF_WU_THS_2	= 0x36,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	FF_WU_DURATION_2 = 0x37,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 	CLICK_CFG	= 0x38,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 	CLICK_SRC	= 0x39,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	CLICK_THSY_X	= 0x3B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 	CLICK_THSZ	= 0x3C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	CLICK_TIMELIMIT	= 0x3D,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	CLICK_LATENCY	= 0x3E,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 	CLICK_WINDOW	= 0x3F,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) enum lis3lv02d_reg {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	FF_WU_CFG	= 0x30,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	FF_WU_SRC	= 0x31,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	FF_WU_ACK	= 0x32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	FF_WU_THS_L	= 0x34,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	FF_WU_THS_H	= 0x35,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	FF_WU_DURATION	= 0x36,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	DD_CFG		= 0x38,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	DD_SRC		= 0x39,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	DD_ACK		= 0x3A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	DD_THSI_L	= 0x3C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	DD_THSI_H	= 0x3D,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	DD_THSE_L	= 0x3E,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	DD_THSE_H	= 0x3F,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) enum lis3_who_am_i {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	WAI_3DLH	= 0x32,	/* 16 bits: LIS331DLH */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	WAI_3DC		= 0x33,	/* 8 bits: LIS3DC, HP3DC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	WAI_12B		= 0x3A, /* 12 bits: LIS3LV02D[LQ]... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	WAI_8B		= 0x3B, /* 8 bits: LIS[23]02D[LQ]... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	WAI_6B		= 0x52, /* 6 bits: LIS331DLF - not supported */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) enum lis3_type {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	LIS3LV02D,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	LIS3DC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	HP3DC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	LIS2302D,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	LIS331DLF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	LIS331DLH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) enum lis3lv02d_ctrl1_12b {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	CTRL1_Xen	= 0x01,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	CTRL1_Yen	= 0x02,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	CTRL1_Zen	= 0x04,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	CTRL1_ST	= 0x08,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	CTRL1_DF0	= 0x10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	CTRL1_DF1	= 0x20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	CTRL1_PD0	= 0x40,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	CTRL1_PD1	= 0x80,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) /* Delta to ctrl1_12b version */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) enum lis3lv02d_ctrl1_8b {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	CTRL1_STM	= 0x08,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	CTRL1_STP	= 0x10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	CTRL1_FS	= 0x20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	CTRL1_PD	= 0x40,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	CTRL1_DR	= 0x80,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) enum lis3lv02d_ctrl1_3dc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	CTRL1_ODR0	= 0x10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	CTRL1_ODR1	= 0x20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	CTRL1_ODR2	= 0x40,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	CTRL1_ODR3	= 0x80,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) enum lis331dlh_ctrl1 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	CTRL1_DR0	= 0x08,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	CTRL1_DR1	= 0x10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	CTRL1_PM0	= 0x20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	CTRL1_PM1	= 0x40,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	CTRL1_PM2	= 0x80,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) enum lis331dlh_ctrl2 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	CTRL2_HPEN1	= 0x04,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	CTRL2_HPEN2	= 0x08,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	CTRL2_FDS_3DLH	= 0x10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	CTRL2_BOOT_3DLH	= 0x80,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) enum lis331dlh_ctrl4 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	CTRL4_STSIGN	= 0x08,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	CTRL4_BLE	= 0x40,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	CTRL4_BDU	= 0x80,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) enum lis3lv02d_ctrl2 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	CTRL2_DAS	= 0x01,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	CTRL2_SIM	= 0x02,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	CTRL2_DRDY	= 0x04,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	CTRL2_IEN	= 0x08,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	CTRL2_BOOT	= 0x10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	CTRL2_BLE	= 0x20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	CTRL2_BDU	= 0x40, /* Block Data Update */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	CTRL2_FS	= 0x80, /* Full Scale selection */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) enum lis3lv02d_ctrl4_3dc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	CTRL4_SIM	= 0x01,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	CTRL4_ST0	= 0x02,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	CTRL4_ST1	= 0x04,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	CTRL4_FS0	= 0x10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	CTRL4_FS1	= 0x20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) enum lis302d_ctrl2 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	HP_FF_WU2	= 0x08,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	HP_FF_WU1	= 0x04,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	CTRL2_BOOT_8B   = 0x40,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) enum lis3lv02d_ctrl3 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	CTRL3_CFS0	= 0x01,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	CTRL3_CFS1	= 0x02,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	CTRL3_FDS	= 0x10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	CTRL3_HPFF	= 0x20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	CTRL3_HPDD	= 0x40,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	CTRL3_ECK	= 0x80,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) enum lis3lv02d_status_reg {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	STATUS_XDA	= 0x01,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	STATUS_YDA	= 0x02,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	STATUS_ZDA	= 0x04,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	STATUS_XYZDA	= 0x08,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	STATUS_XOR	= 0x10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	STATUS_YOR	= 0x20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	STATUS_ZOR	= 0x40,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	STATUS_XYZOR	= 0x80,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) enum lis3lv02d_ff_wu_cfg {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	FF_WU_CFG_XLIE	= 0x01,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	FF_WU_CFG_XHIE	= 0x02,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	FF_WU_CFG_YLIE	= 0x04,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	FF_WU_CFG_YHIE	= 0x08,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	FF_WU_CFG_ZLIE	= 0x10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	FF_WU_CFG_ZHIE	= 0x20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	FF_WU_CFG_LIR	= 0x40,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 	FF_WU_CFG_AOI	= 0x80,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) enum lis3lv02d_ff_wu_src {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	FF_WU_SRC_XL	= 0x01,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 	FF_WU_SRC_XH	= 0x02,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	FF_WU_SRC_YL	= 0x04,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	FF_WU_SRC_YH	= 0x08,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	FF_WU_SRC_ZL	= 0x10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	FF_WU_SRC_ZH	= 0x20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	FF_WU_SRC_IA	= 0x40,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) enum lis3lv02d_dd_cfg {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 	DD_CFG_XLIE	= 0x01,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 	DD_CFG_XHIE	= 0x02,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	DD_CFG_YLIE	= 0x04,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	DD_CFG_YHIE	= 0x08,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	DD_CFG_ZLIE	= 0x10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 	DD_CFG_ZHIE	= 0x20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 	DD_CFG_LIR	= 0x40,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 	DD_CFG_IEND	= 0x80,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) enum lis3lv02d_dd_src {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 	DD_SRC_XL	= 0x01,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	DD_SRC_XH	= 0x02,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 	DD_SRC_YL	= 0x04,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 	DD_SRC_YH	= 0x08,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 	DD_SRC_ZL	= 0x10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 	DD_SRC_ZH	= 0x20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 	DD_SRC_IA	= 0x40,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) enum lis3lv02d_click_src_8b {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 	CLICK_SINGLE_X	= 0x01,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 	CLICK_DOUBLE_X	= 0x02,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 	CLICK_SINGLE_Y	= 0x04,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 	CLICK_DOUBLE_Y	= 0x08,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 	CLICK_SINGLE_Z	= 0x10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 	CLICK_DOUBLE_Z	= 0x20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 	CLICK_IA	= 0x40,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) enum lis3lv02d_reg_state {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 	LIS3_REG_OFF	= 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 	LIS3_REG_ON	= 0x01,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) union axis_conversion {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 	struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 		int x, y, z;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 	int as_array[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) struct lis3lv02d {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 	void			*bus_priv; /* used by the bus layer only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 	struct device		*pm_dev; /* for pm_runtime purposes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 	int (*init) (struct lis3lv02d *lis3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 	int (*write) (struct lis3lv02d *lis3, int reg, u8 val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 	int (*read) (struct lis3lv02d *lis3, int reg, u8 *ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 	int (*blkread) (struct lis3lv02d *lis3, int reg, int len, u8 *ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 	int (*reg_ctrl) (struct lis3lv02d *lis3, bool state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 	int                     *odrs;     /* Supported output data rates */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 	u8			*regs;	   /* Regs to store / restore */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 	int			regs_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 	u8                      *reg_cache;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 	bool			regs_stored;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 	bool			init_required;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 	u8                      odr_mask;  /* ODR bit mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 	u8			whoami;    /* indicates measurement precision */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 	s16 (*read_data) (struct lis3lv02d *lis3, int reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 	int			mdps_max_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 	int			pwron_delay;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 	int                     scale; /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 					* relationship between 1 LBS and mG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 					* (1/1000th of earth gravity)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 					*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 	struct input_dev	*idev;     /* input device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 	struct platform_device	*pdev;     /* platform device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 	struct regulator_bulk_data regulators[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 	atomic_t		count;     /* interrupt count after last read */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 	union axis_conversion	ac;        /* hw -> logical axis */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 	int			mapped_btns[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 	u32			irq;       /* IRQ number */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 	struct fasync_struct	*async_queue; /* queue for the misc device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 	wait_queue_head_t	misc_wait; /* Wait queue for the misc device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 	unsigned long		misc_opened; /* bit0: whether the device is open */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 	struct miscdevice	miscdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 	int                     data_ready_count[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 	atomic_t		wake_thread;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 	unsigned char           irq_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 	unsigned int		shift_adj;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 	struct lis3lv02d_platform_data *pdata;	/* for passing board config */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 	struct mutex		mutex;     /* Serialize poll and selftest */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) #ifdef CONFIG_OF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 	struct device_node	*of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) int lis3lv02d_init_device(struct lis3lv02d *lis3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) int lis3lv02d_joystick_enable(struct lis3lv02d *lis3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) void lis3lv02d_joystick_disable(struct lis3lv02d *lis3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) void lis3lv02d_poweroff(struct lis3lv02d *lis3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) int lis3lv02d_poweron(struct lis3lv02d *lis3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) int lis3lv02d_remove_fs(struct lis3lv02d *lis3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) int lis3lv02d_init_dt(struct lis3lv02d *lis3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) extern struct lis3lv02d lis3_dev;