^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) 2012 Stefan Roese <sr@denx.de>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/firmware.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/errno.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/spi/spi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <asm/unaligned.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define FIRMWARE_NAME "lattice-ecp3.bit"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * The JTAG ID's of the supported FPGA's. The ID is 32bit wide
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * reversed as noted in the manual.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define ID_ECP3_17 0xc2088080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define ID_ECP3_35 0xc2048080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) /* FPGA commands */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define FPGA_CMD_READ_ID 0x07 /* plus 24 bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define FPGA_CMD_READ_STATUS 0x09 /* plus 24 bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define FPGA_CMD_CLEAR 0x70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define FPGA_CMD_REFRESH 0x71
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define FPGA_CMD_WRITE_EN 0x4a /* plus 2 bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define FPGA_CMD_WRITE_DIS 0x4f /* plus 8 bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define FPGA_CMD_WRITE_INC 0x41 /* plus 0 bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) * The status register is 32bit revered, DONE is bit 17 from the TN1222.pdf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) * (LatticeECP3 Slave SPI Port User's Guide)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define FPGA_STATUS_DONE 0x00004000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define FPGA_STATUS_CLEARED 0x00010000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define FPGA_CLEAR_TIMEOUT 5000 /* max. 5000ms for FPGA clear */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define FPGA_CLEAR_MSLEEP 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define FPGA_CLEAR_LOOP_COUNT (FPGA_CLEAR_TIMEOUT / FPGA_CLEAR_MSLEEP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) struct fpga_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) struct completion fw_loaded;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) struct ecp3_dev {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) u32 jedec_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) static const struct ecp3_dev ecp3_dev[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) .jedec_id = ID_ECP3_17,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) .name = "Lattice ECP3-17",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) .jedec_id = ID_ECP3_35,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) .name = "Lattice ECP3-35",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) static void firmware_load(const struct firmware *fw, void *context)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) struct spi_device *spi = (struct spi_device *)context;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) struct fpga_data *data = spi_get_drvdata(spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) u8 *buffer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) u8 txbuf[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) u8 rxbuf[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) int rx_len = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) u32 jedec_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) u32 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) if (fw == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) dev_err(&spi->dev, "Cannot load firmware, aborting\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) if (fw->size == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) dev_err(&spi->dev, "Error: Firmware size is 0!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) /* Fill dummy data (24 stuffing bits for commands) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) txbuf[1] = 0x00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) txbuf[2] = 0x00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) txbuf[3] = 0x00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) /* Trying to speak with the FPGA via SPI... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) txbuf[0] = FPGA_CMD_READ_ID;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) spi_write_then_read(spi, txbuf, 8, rxbuf, rx_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) jedec_id = get_unaligned_be32(&rxbuf[4]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) dev_dbg(&spi->dev, "FPGA JTAG ID=%08x\n", jedec_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) for (i = 0; i < ARRAY_SIZE(ecp3_dev); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) if (jedec_id == ecp3_dev[i].jedec_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) if (i == ARRAY_SIZE(ecp3_dev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) dev_err(&spi->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) "Error: No supported FPGA detected (JEDEC_ID=%08x)!\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) jedec_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) dev_info(&spi->dev, "FPGA %s detected\n", ecp3_dev[i].name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) txbuf[0] = FPGA_CMD_READ_STATUS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) spi_write_then_read(spi, txbuf, 8, rxbuf, rx_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) status = get_unaligned_be32(&rxbuf[4]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) dev_dbg(&spi->dev, "FPGA Status=%08x\n", status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) buffer = kzalloc(fw->size + 8, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) if (!buffer) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) dev_err(&spi->dev, "Error: Can't allocate memory!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) * Insert WRITE_INC command into stream (one SPI frame)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) buffer[0] = FPGA_CMD_WRITE_INC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) buffer[1] = 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) buffer[2] = 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) buffer[3] = 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) memcpy(buffer + 4, fw->data, fw->size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) txbuf[0] = FPGA_CMD_REFRESH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) spi_write(spi, txbuf, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) txbuf[0] = FPGA_CMD_WRITE_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) spi_write(spi, txbuf, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) txbuf[0] = FPGA_CMD_CLEAR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) spi_write(spi, txbuf, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) * Wait for FPGA memory to become cleared
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) for (i = 0; i < FPGA_CLEAR_LOOP_COUNT; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) txbuf[0] = FPGA_CMD_READ_STATUS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) spi_write_then_read(spi, txbuf, 8, rxbuf, rx_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) status = get_unaligned_be32(&rxbuf[4]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) if (status == FPGA_STATUS_CLEARED)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) msleep(FPGA_CLEAR_MSLEEP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) if (i == FPGA_CLEAR_LOOP_COUNT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) dev_err(&spi->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) "Error: Timeout waiting for FPGA to clear (status=%08x)!\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) kfree(buffer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) dev_info(&spi->dev, "Configuring the FPGA...\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) spi_write(spi, buffer, fw->size + 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) txbuf[0] = FPGA_CMD_WRITE_DIS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) spi_write(spi, txbuf, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) txbuf[0] = FPGA_CMD_READ_STATUS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) spi_write_then_read(spi, txbuf, 8, rxbuf, rx_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) status = get_unaligned_be32(&rxbuf[4]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) dev_dbg(&spi->dev, "FPGA Status=%08x\n", status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) /* Check result */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) if (status & FPGA_STATUS_DONE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) dev_info(&spi->dev, "FPGA successfully configured!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) dev_info(&spi->dev, "FPGA not configured (DONE not set)\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) * Don't forget to release the firmware again
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) release_firmware(fw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) kfree(buffer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) complete(&data->fw_loaded);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) static int lattice_ecp3_probe(struct spi_device *spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) struct fpga_data *data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) data = devm_kzalloc(&spi->dev, sizeof(*data), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) if (!data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) dev_err(&spi->dev, "Memory allocation for fpga_data failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) spi_set_drvdata(spi, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) init_completion(&data->fw_loaded);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) err = request_firmware_nowait(THIS_MODULE, FW_ACTION_HOTPLUG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) FIRMWARE_NAME, &spi->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) GFP_KERNEL, spi, firmware_load);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) dev_err(&spi->dev, "Firmware loading failed with %d!\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) dev_info(&spi->dev, "FPGA bitstream configuration driver registered\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) static int lattice_ecp3_remove(struct spi_device *spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) struct fpga_data *data = spi_get_drvdata(spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) wait_for_completion(&data->fw_loaded);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) static const struct spi_device_id lattice_ecp3_id[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) { "ecp3-17", 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) { "ecp3-35", 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) MODULE_DEVICE_TABLE(spi, lattice_ecp3_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) static struct spi_driver lattice_ecp3_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) .name = "lattice-ecp3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) .probe = lattice_ecp3_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) .remove = lattice_ecp3_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) .id_table = lattice_ecp3_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) module_spi_driver(lattice_ecp3_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) MODULE_AUTHOR("Stefan Roese <sr@denx.de>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) MODULE_DESCRIPTION("Lattice ECP3 FPGA configuration via SPI");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) MODULE_FIRMWARE(FIRMWARE_NAME);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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