Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * linux/drivers/char/hpilo.h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Copyright (C) 2008 Hewlett-Packard Development Company, L.P.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  *	David Altobelli <david.altobelli@hp.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #ifndef __HPILO_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #define __HPILO_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #define ILO_NAME "hpilo"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) /* max number of open channel control blocks per device, hw limited to 32 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #define MAX_CCB	       24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) /* min number of open channel control blocks per device, hw limited to 32 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #define MIN_CCB		8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) /* max number of supported devices */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #define MAX_ILO_DEV	1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) /* max number of files */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #define MAX_OPEN	(MAX_CCB * MAX_ILO_DEV)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) /* total wait time in usec */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #define MAX_WAIT_TIME	10000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) /* per spin wait time in usec */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #define WAIT_TIME	10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) /* spin counter for open/close delay */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define MAX_WAIT	(MAX_WAIT_TIME / WAIT_TIME)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29)  * Per device, used to track global memory allocations.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) struct ilo_hwinfo {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 	/* mmio registers on device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 	char __iomem *mmio_vaddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 	/* doorbell registers on device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 	char __iomem *db_vaddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 	/* shared memory on device used for channel control blocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 	char __iomem *ram_vaddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 	/* files corresponding to this device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 	struct ccb_data *ccb_alloc[MAX_CCB];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 	struct pci_dev *ilo_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 	 * open_lock      serializes ccb_cnt during open and close
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 	 * [ irq disabled ]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 	 * -> alloc_lock  used when adding/removing/searching ccb_alloc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 	 *                which represents all ccbs open on the device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 	 * --> fifo_lock  controls access to fifo queues shared with hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 	 *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 	 * Locks must be taken in this order, but open_lock and alloc_lock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 	 * are optional, they do not need to be held in order to take a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 	 * lower level lock.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 	spinlock_t open_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 	spinlock_t alloc_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	spinlock_t fifo_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 	struct cdev cdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) /* offset from mmio_vaddr for enabling doorbell interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) #define DB_IRQ		0xB2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) /* offset from mmio_vaddr for outbound communications */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) #define DB_OUT		0xD4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) /* DB_OUT reset bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) #define DB_RESET	26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72)  * Channel control block. Used to manage hardware queues.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73)  * The format must match hw's version.  The hw ccb is 128 bytes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74)  * but the context area shouldn't be touched by the driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) #define ILOSW_CCB_SZ	64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) #define ILOHW_CCB_SZ 	128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) struct ccb {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 		char *send_fifobar;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 		u64 send_fifobar_pa;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	} ccb_u1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 		char *send_desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 		u64 send_desc_pa;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	} ccb_u2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	u64 send_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 		char *recv_fifobar;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 		u64 recv_fifobar_pa;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	} ccb_u3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 		char *recv_desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 		u64 recv_desc_pa;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	} ccb_u4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	u64 recv_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 		char __iomem *db_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 		u64 padding5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	} ccb_u5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	u64 channel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	/* unused context area (64 bytes) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) /* ccb queue parameters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define SENDQ		1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define RECVQ 		2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define NR_QENTRY    	4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define L2_QENTRY_SZ 	12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) /* ccb ctrl bitfields */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define CTRL_BITPOS_L2SZ             0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define CTRL_BITPOS_FIFOINDEXMASK    4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define CTRL_BITPOS_DESCLIMIT        18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define CTRL_BITPOS_A                30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define CTRL_BITPOS_G                31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) /* ccb doorbell macros */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define L2_DB_SIZE		14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define ONE_DB_SIZE		(1 << L2_DB_SIZE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)  * Per fd structure used to track the ccb allocated to that dev file.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) struct ccb_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	/* software version of ccb, using virtual addrs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	struct ccb  driver_ccb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	/* hardware version of ccb, using physical addrs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	struct ccb  ilo_ccb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	/* hardware ccb is written to this shared mapped device memory */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	struct ccb __iomem *mapped_ccb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	/* dma'able memory used for send/recv queues */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	void       *dma_va;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	dma_addr_t  dma_pa;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	size_t      dma_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	/* pointer to hardware device info */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	struct ilo_hwinfo *ilo_hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	/* queue for this ccb to wait for recv data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	wait_queue_head_t ccb_waitq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	/* usage count, to allow for shared ccb's */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	int	    ccb_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	/* open wanted exclusive access to this ccb */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	int	    ccb_excl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)  * FIFO queue structure, shared with hw.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define ILO_START_ALIGN	4096
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define ILO_CACHE_SZ 	 128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) struct fifo {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	u64 nrents;	/* user requested number of fifo entries */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	u64 imask;  /* mask to extract valid fifo index */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	u64 merge;	/*  O/C bits to merge in during enqueue operation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	u64 reset;	/* set to non-zero when the target device resets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	u8  pad_0[ILO_CACHE_SZ - (sizeof(u64) * 4)];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	u64 head;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	u8  pad_1[ILO_CACHE_SZ - (sizeof(u64))];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	u64 tail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	u8  pad_2[ILO_CACHE_SZ - (sizeof(u64))];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	u64 fifobar[];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) /* convert between struct fifo, and the fifobar, which is saved in the ccb */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define FIFOHANDLESIZE (sizeof(struct fifo))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define FIFOBARTOHANDLE(_fifo) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	((struct fifo *)(((char *)(_fifo)) - FIFOHANDLESIZE))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) /* the number of qwords to consume from the entry descriptor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define ENTRY_BITPOS_QWORDS      0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) /* descriptor index number (within a specified queue) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define ENTRY_BITPOS_DESCRIPTOR  10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) /* state bit, fifo entry consumed by consumer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define ENTRY_BITPOS_C           22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) /* state bit, fifo entry is occupied */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define ENTRY_BITPOS_O           23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define ENTRY_BITS_QWORDS        10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define ENTRY_BITS_DESCRIPTOR    12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define ENTRY_BITS_C             1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define ENTRY_BITS_O             1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define ENTRY_BITS_TOTAL	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	(ENTRY_BITS_C + ENTRY_BITS_O + \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	 ENTRY_BITS_QWORDS + ENTRY_BITS_DESCRIPTOR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) /* extract various entry fields */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define ENTRY_MASK ((1 << ENTRY_BITS_TOTAL) - 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define ENTRY_MASK_C (((1 << ENTRY_BITS_C) - 1) << ENTRY_BITPOS_C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define ENTRY_MASK_O (((1 << ENTRY_BITS_O) - 1) << ENTRY_BITPOS_O)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define ENTRY_MASK_QWORDS \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	(((1 << ENTRY_BITS_QWORDS) - 1) << ENTRY_BITPOS_QWORDS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define ENTRY_MASK_DESCRIPTOR \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	(((1 << ENTRY_BITS_DESCRIPTOR) - 1) << ENTRY_BITPOS_DESCRIPTOR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define ENTRY_MASK_NOSTATE (ENTRY_MASK >> (ENTRY_BITS_C + ENTRY_BITS_O))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #endif /* __HPILO_H */