Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /* SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Copyright 2016-2019 HabanaLabs, Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  * All Rights Reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #ifndef GOYAP_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #define GOYAP_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <uapi/misc/habanalabs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include "../common/habanalabs.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include "../include/common/hl_boot_if.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include "../include/goya/goya_packets.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include "../include/goya/goya.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include "../include/goya/goya_async_events.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include "../include/goya/goya_fw_if.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #define NUMBER_OF_CMPLT_QUEUES		5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #define NUMBER_OF_EXT_HW_QUEUES		5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #define NUMBER_OF_CPU_HW_QUEUES		1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #define NUMBER_OF_INT_HW_QUEUES		9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #define NUMBER_OF_HW_QUEUES		(NUMBER_OF_EXT_HW_QUEUES + \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) 					NUMBER_OF_CPU_HW_QUEUES + \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 					NUMBER_OF_INT_HW_QUEUES)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28)  * Number of MSIX interrupts IDS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29)  * Each completion queue has 1 ID
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30)  * The event queue has 1 ID
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define NUMBER_OF_INTERRUPTS		(NUMBER_OF_CMPLT_QUEUES + 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #if (NUMBER_OF_INTERRUPTS > GOYA_MSIX_ENTRIES)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #error "Number of MSIX interrupts must be smaller or equal to GOYA_MSIX_ENTRIES"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define QMAN_FENCE_TIMEOUT_USEC		10000		/* 10 ms */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #define QMAN_STOP_TIMEOUT_USEC		100000		/* 100 ms */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #define CORESIGHT_TIMEOUT_USEC		100000		/* 100 ms */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #define GOYA_CPU_TIMEOUT_USEC		15000000	/* 15s */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) #define TPC_ENABLED_MASK		0xFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) #define PLL_HIGH_DEFAULT		1575000000	/* 1.575 GHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) #define MAX_POWER_DEFAULT		200000		/* 200W */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) #define DRAM_PHYS_DEFAULT_SIZE		0x100000000ull	/* 4GB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) #define GOYA_DEFAULT_CARD_NAME		"HL1000"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) #define GOYA_MAX_PENDING_CS		64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) #if !IS_MAX_PENDING_CS_VALID(GOYA_MAX_PENDING_CS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) #error "GOYA_MAX_PENDING_CS must be power of 2 and greater than 1"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) /* DRAM Memory Map */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) #define CPU_FW_IMAGE_SIZE		0x10000000	/* 256MB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) #define MMU_PAGE_TABLES_SIZE		0x0FC00000	/* 252MB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) #define MMU_DRAM_DEFAULT_PAGE_SIZE	0x00200000	/* 2MB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) #define MMU_CACHE_MNG_SIZE		0x00001000	/* 4KB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) #define CPU_FW_IMAGE_ADDR		DRAM_PHYS_BASE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) #define MMU_PAGE_TABLES_ADDR		(CPU_FW_IMAGE_ADDR + CPU_FW_IMAGE_SIZE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) #define MMU_DRAM_DEFAULT_PAGE_ADDR	(MMU_PAGE_TABLES_ADDR + \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 						MMU_PAGE_TABLES_SIZE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) #define MMU_CACHE_MNG_ADDR		(MMU_DRAM_DEFAULT_PAGE_ADDR + \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 					MMU_DRAM_DEFAULT_PAGE_SIZE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) #define DRAM_DRIVER_END_ADDR		(MMU_CACHE_MNG_ADDR + \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 						MMU_CACHE_MNG_SIZE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) #define DRAM_BASE_ADDR_USER		0x20000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) #if (DRAM_DRIVER_END_ADDR > DRAM_BASE_ADDR_USER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) #error "Driver must reserve no more than 512MB"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85)  * SRAM Memory Map for Driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87)  * Driver occupies DRIVER_SRAM_SIZE bytes from the start of SRAM. It is used for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88)  * MME/TPC QMANs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) #define MME_QMAN_BASE_OFFSET	0x000000	/* Must be 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) #define MME_QMAN_LENGTH		64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) #define TPC_QMAN_LENGTH		64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) #define TPC0_QMAN_BASE_OFFSET	(MME_QMAN_BASE_OFFSET + \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 				(MME_QMAN_LENGTH * QMAN_PQ_ENTRY_SIZE))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) #define TPC1_QMAN_BASE_OFFSET	(TPC0_QMAN_BASE_OFFSET + \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 				(TPC_QMAN_LENGTH * QMAN_PQ_ENTRY_SIZE))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define TPC2_QMAN_BASE_OFFSET	(TPC1_QMAN_BASE_OFFSET + \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 				(TPC_QMAN_LENGTH * QMAN_PQ_ENTRY_SIZE))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define TPC3_QMAN_BASE_OFFSET	(TPC2_QMAN_BASE_OFFSET + \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 				(TPC_QMAN_LENGTH * QMAN_PQ_ENTRY_SIZE))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define TPC4_QMAN_BASE_OFFSET	(TPC3_QMAN_BASE_OFFSET + \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 				(TPC_QMAN_LENGTH * QMAN_PQ_ENTRY_SIZE))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define TPC5_QMAN_BASE_OFFSET	(TPC4_QMAN_BASE_OFFSET + \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 				(TPC_QMAN_LENGTH * QMAN_PQ_ENTRY_SIZE))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define TPC6_QMAN_BASE_OFFSET	(TPC5_QMAN_BASE_OFFSET + \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 				(TPC_QMAN_LENGTH * QMAN_PQ_ENTRY_SIZE))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define TPC7_QMAN_BASE_OFFSET	(TPC6_QMAN_BASE_OFFSET + \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 				(TPC_QMAN_LENGTH * QMAN_PQ_ENTRY_SIZE))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define SRAM_DRIVER_RES_OFFSET	(TPC7_QMAN_BASE_OFFSET + \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 				(TPC_QMAN_LENGTH * QMAN_PQ_ENTRY_SIZE))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #if (SRAM_DRIVER_RES_OFFSET >= GOYA_KMD_SRAM_RESERVED_SIZE_FROM_START)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #error "MME/TPC QMANs SRAM space exceeds limit"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define SRAM_USER_BASE_OFFSET	GOYA_KMD_SRAM_RESERVED_SIZE_FROM_START
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) /* Virtual address space */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define VA_HOST_SPACE_START	0x1000000000000ull	/* 256TB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define VA_HOST_SPACE_END	0x3FF8000000000ull	/* 1PB - 1TB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define VA_HOST_SPACE_SIZE	(VA_HOST_SPACE_END - \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 					VA_HOST_SPACE_START) /* 767TB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define VA_DDR_SPACE_START	0x800000000ull		/* 32GB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define VA_DDR_SPACE_END	0x2000000000ull		/* 128GB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define VA_DDR_SPACE_SIZE	(VA_DDR_SPACE_END - \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 					VA_DDR_SPACE_START)	/* 128GB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #if (HL_CPU_ACCESSIBLE_MEM_SIZE != SZ_2M)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #error "HL_CPU_ACCESSIBLE_MEM_SIZE must be exactly 2MB to enable MMU mapping"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define VA_CPU_ACCESSIBLE_MEM_ADDR	0x8000000000ull
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define DMA_MAX_TRANSFER_SIZE	U32_MAX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define HW_CAP_PLL		0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define HW_CAP_DDR_0		0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define HW_CAP_DDR_1		0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define HW_CAP_MME		0x00000008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define HW_CAP_CPU		0x00000010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define HW_CAP_DMA		0x00000020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define HW_CAP_MSIX		0x00000040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define HW_CAP_CPU_Q		0x00000080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define HW_CAP_MMU		0x00000100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define HW_CAP_TPC_MBIST	0x00000200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define HW_CAP_GOLDEN		0x00000400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define HW_CAP_TPC		0x00000800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) struct goya_device {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	/* TODO: remove hw_queues_lock after moving to scheduler code */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	spinlock_t	hw_queues_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	u64		mme_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	u64		tpc_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	u64		ic_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	u64		ddr_bar_cur_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	u32		events_stat[GOYA_ASYNC_EVENT_ID_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	u32		events_stat_aggregate[GOYA_ASYNC_EVENT_ID_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	u32		hw_cap_initialized;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	u8		device_cpu_mmu_mappings_done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) int goya_get_fixed_properties(struct hl_device *hdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) int goya_mmu_init(struct hl_device *hdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) void goya_init_dma_qmans(struct hl_device *hdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) void goya_init_mme_qmans(struct hl_device *hdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) void goya_init_tpc_qmans(struct hl_device *hdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) int goya_init_cpu_queues(struct hl_device *hdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) void goya_init_security(struct hl_device *hdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) int goya_late_init(struct hl_device *hdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) void goya_late_fini(struct hl_device *hdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) void goya_ring_doorbell(struct hl_device *hdev, u32 hw_queue_id, u32 pi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) void goya_pqe_write(struct hl_device *hdev, __le64 *pqe, struct hl_bd *bd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) void goya_update_eq_ci(struct hl_device *hdev, u32 val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) void goya_restore_phase_topology(struct hl_device *hdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) int goya_context_switch(struct hl_device *hdev, u32 asid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) int goya_debugfs_i2c_read(struct hl_device *hdev, u8 i2c_bus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 			u8 i2c_addr, u8 i2c_reg, u32 *val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) int goya_debugfs_i2c_write(struct hl_device *hdev, u8 i2c_bus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 			u8 i2c_addr, u8 i2c_reg, u32 val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) void goya_debugfs_led_set(struct hl_device *hdev, u8 led, u8 state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) int goya_test_queue(struct hl_device *hdev, u32 hw_queue_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) int goya_test_queues(struct hl_device *hdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) int goya_test_cpu_queue(struct hl_device *hdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) int goya_send_cpu_message(struct hl_device *hdev, u32 *msg, u16 len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 				u32 timeout, long *result);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) long goya_get_temperature(struct hl_device *hdev, int sensor_index, u32 attr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) long goya_get_voltage(struct hl_device *hdev, int sensor_index, u32 attr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) long goya_get_current(struct hl_device *hdev, int sensor_index, u32 attr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) long goya_get_fan_speed(struct hl_device *hdev, int sensor_index, u32 attr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) long goya_get_pwm_info(struct hl_device *hdev, int sensor_index, u32 attr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) void goya_set_pwm_info(struct hl_device *hdev, int sensor_index, u32 attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 			long value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) u64 goya_get_max_power(struct hl_device *hdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) void goya_set_max_power(struct hl_device *hdev, u64 value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) void goya_set_pll_profile(struct hl_device *hdev, enum hl_pll_frequency freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) void goya_add_device_attr(struct hl_device *hdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 			struct attribute_group *dev_attr_grp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) int goya_cpucp_info_get(struct hl_device *hdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) int goya_debug_coresight(struct hl_device *hdev, void *data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) void goya_halt_coresight(struct hl_device *hdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) int goya_suspend(struct hl_device *hdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) int goya_resume(struct hl_device *hdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) void goya_handle_eqe(struct hl_device *hdev, struct hl_eq_entry *eq_entry);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) void *goya_get_events_stat(struct hl_device *hdev, bool aggregate, u32 *size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) void goya_add_end_of_cb_packets(struct hl_device *hdev, void *kernel_address,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 				u32 len, u64 cq_addr, u32 cq_val, u32 msix_vec,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 				bool eb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) int goya_cs_parser(struct hl_device *hdev, struct hl_cs_parser *parser);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) void *goya_get_int_queue_base(struct hl_device *hdev, u32 queue_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 				dma_addr_t *dma_handle,	u16 *queue_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) u32 goya_get_dma_desc_list_size(struct hl_device *hdev, struct sg_table *sgt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) int goya_send_heartbeat(struct hl_device *hdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) void *goya_cpu_accessible_dma_pool_alloc(struct hl_device *hdev, size_t size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 					dma_addr_t *dma_handle);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) void goya_cpu_accessible_dma_pool_free(struct hl_device *hdev, size_t size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 					void *vaddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) void goya_mmu_remove_device_cpu_mappings(struct hl_device *hdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) int goya_get_clk_rate(struct hl_device *hdev, u32 *cur_clk, u32 *max_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) u32 goya_get_queue_id_for_cq(struct hl_device *hdev, u32 cq_idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) u64 goya_get_device_time(struct hl_device *hdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) #endif /* GOYAP_H_ */