^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright 2019-2020 HabanaLabs, Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * All Rights Reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #ifndef GAUDIP_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #define GAUDIP_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <uapi/misc/habanalabs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include "../common/habanalabs.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include "../include/common/hl_boot_if.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include "../include/gaudi/gaudi_packets.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include "../include/gaudi/gaudi.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include "../include/gaudi/gaudi_async_events.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define NUMBER_OF_EXT_HW_QUEUES 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define NUMBER_OF_CMPLT_QUEUES NUMBER_OF_EXT_HW_QUEUES
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define NUMBER_OF_CPU_HW_QUEUES 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define NUMBER_OF_INT_HW_QUEUES 100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define NUMBER_OF_HW_QUEUES (NUMBER_OF_EXT_HW_QUEUES + \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) NUMBER_OF_CPU_HW_QUEUES + \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) NUMBER_OF_INT_HW_QUEUES)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) * Number of MSI interrupts IDS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) * Each completion queue has 1 ID
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) * The event queue has 1 ID
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define NUMBER_OF_INTERRUPTS (NUMBER_OF_CMPLT_QUEUES + \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) NUMBER_OF_CPU_HW_QUEUES)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #if (NUMBER_OF_INTERRUPTS > GAUDI_MSI_ENTRIES)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #error "Number of MSI interrupts must be smaller or equal to GAUDI_MSI_ENTRIES"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define CORESIGHT_TIMEOUT_USEC 100000 /* 100 ms */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define GAUDI_MAX_CLK_FREQ 2200000000ull /* 2200 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define MAX_POWER_DEFAULT_PCI 200000 /* 200W */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define MAX_POWER_DEFAULT_PMC 350000 /* 350W */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define GAUDI_CPU_TIMEOUT_USEC 30000000 /* 30s */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define TPC_ENABLED_MASK 0xFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define GAUDI_HBM_SIZE_32GB 0x800000000ull
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define GAUDI_HBM_DEVICES 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define GAUDI_HBM_CHANNELS 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define GAUDI_HBM_CFG_BASE (mmHBM0_BASE - CFG_BASE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define GAUDI_HBM_CFG_OFFSET (mmHBM1_BASE - mmHBM0_BASE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define DMA_MAX_TRANSFER_SIZE U32_MAX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define GAUDI_DEFAULT_CARD_NAME "HL2000"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define GAUDI_MAX_PENDING_CS 1024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #if !IS_MAX_PENDING_CS_VALID(GAUDI_MAX_PENDING_CS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #error "GAUDI_MAX_PENDING_CS must be power of 2 and greater than 1"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define PCI_DMA_NUMBER_OF_CHNLS 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define HBM_DMA_NUMBER_OF_CHNLS 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define DMA_NUMBER_OF_CHNLS (PCI_DMA_NUMBER_OF_CHNLS + \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) HBM_DMA_NUMBER_OF_CHNLS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define MME_NUMBER_OF_SLAVE_ENGINES 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define MME_NUMBER_OF_ENGINES (MME_NUMBER_OF_MASTER_ENGINES + \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) MME_NUMBER_OF_SLAVE_ENGINES)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define MME_NUMBER_OF_QMANS (MME_NUMBER_OF_MASTER_ENGINES * \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) QMAN_STREAMS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define QMAN_STREAMS 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define DMA_QMAN_OFFSET (mmDMA1_QM_BASE - mmDMA0_QM_BASE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define TPC_QMAN_OFFSET (mmTPC1_QM_BASE - mmTPC0_QM_BASE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define MME_QMAN_OFFSET (mmMME1_QM_BASE - mmMME0_QM_BASE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define NIC_MACRO_QMAN_OFFSET (mmNIC1_QM0_BASE - mmNIC0_QM0_BASE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define TPC_CFG_OFFSET (mmTPC1_CFG_BASE - mmTPC0_CFG_BASE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define DMA_CORE_OFFSET (mmDMA1_CORE_BASE - mmDMA0_CORE_BASE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define QMAN_LDMA_SRC_OFFSET (mmDMA0_CORE_SRC_BASE_LO - mmDMA0_CORE_CFG_0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define QMAN_LDMA_DST_OFFSET (mmDMA0_CORE_DST_BASE_LO - mmDMA0_CORE_CFG_0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define QMAN_LDMA_SIZE_OFFSET (mmDMA0_CORE_DST_TSIZE_0 - mmDMA0_CORE_CFG_0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define QMAN_CPDMA_SRC_OFFSET (mmDMA0_QM_CQ_PTR_LO_4 - mmDMA0_CORE_CFG_0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define QMAN_CPDMA_DST_OFFSET (mmDMA0_CORE_DST_BASE_LO - mmDMA0_CORE_CFG_0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define QMAN_CPDMA_SIZE_OFFSET (mmDMA0_QM_CQ_TSIZE_4 - mmDMA0_CORE_CFG_0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define SIF_RTR_CTRL_OFFSET (mmSIF_RTR_CTRL_1_BASE - mmSIF_RTR_CTRL_0_BASE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define NIF_RTR_CTRL_OFFSET (mmNIF_RTR_CTRL_1_BASE - mmNIF_RTR_CTRL_0_BASE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define MME_ACC_OFFSET (mmMME1_ACC_BASE - mmMME0_ACC_BASE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define SRAM_BANK_OFFSET (mmSRAM_Y0_X1_RTR_BASE - mmSRAM_Y0_X0_RTR_BASE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define NUM_OF_SOB_IN_BLOCK \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) (((mmSYNC_MNGR_E_N_SYNC_MNGR_OBJS_SOB_OBJ_2047 - \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) mmSYNC_MNGR_E_N_SYNC_MNGR_OBJS_SOB_OBJ_0) + 4) >> 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define NUM_OF_MONITORS_IN_BLOCK \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) (((mmSYNC_MNGR_E_N_SYNC_MNGR_OBJS_MON_STATUS_511 - \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) mmSYNC_MNGR_E_N_SYNC_MNGR_OBJS_MON_STATUS_0) + 4) >> 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) /* DRAM Memory Map */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define CPU_FW_IMAGE_SIZE 0x10000000 /* 256MB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define MMU_PAGE_TABLES_SIZE 0x0BF00000 /* 191MB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define MMU_CACHE_MNG_SIZE 0x00100000 /* 1MB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define RESERVED 0x04000000 /* 64MB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define CPU_FW_IMAGE_ADDR DRAM_PHYS_BASE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define MMU_PAGE_TABLES_ADDR (CPU_FW_IMAGE_ADDR + CPU_FW_IMAGE_SIZE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define MMU_CACHE_MNG_ADDR (MMU_PAGE_TABLES_ADDR + MMU_PAGE_TABLES_SIZE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define DRAM_DRIVER_END_ADDR (MMU_CACHE_MNG_ADDR + MMU_CACHE_MNG_SIZE +\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) RESERVED)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define DRAM_BASE_ADDR_USER 0x20000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #if (DRAM_DRIVER_END_ADDR > DRAM_BASE_ADDR_USER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #error "Driver must reserve no more than 512MB"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) /* Internal QMANs PQ sizes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define MME_QMAN_LENGTH 1024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define MME_QMAN_SIZE_IN_BYTES (MME_QMAN_LENGTH * QMAN_PQ_ENTRY_SIZE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define HBM_DMA_QMAN_LENGTH 1024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define HBM_DMA_QMAN_SIZE_IN_BYTES \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) (HBM_DMA_QMAN_LENGTH * QMAN_PQ_ENTRY_SIZE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define TPC_QMAN_LENGTH 1024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define TPC_QMAN_SIZE_IN_BYTES (TPC_QMAN_LENGTH * QMAN_PQ_ENTRY_SIZE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define SRAM_USER_BASE_OFFSET GAUDI_DRIVER_SRAM_RESERVED_SIZE_FROM_START
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) /* Virtual address space */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define VA_HOST_SPACE_START 0x1000000000000ull /* 256TB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define VA_HOST_SPACE_END 0x3FF8000000000ull /* 1PB - 1TB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define VA_HOST_SPACE_SIZE (VA_HOST_SPACE_END - \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) VA_HOST_SPACE_START) /* 767TB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define HW_CAP_PLL BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define HW_CAP_HBM BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define HW_CAP_MMU BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define HW_CAP_MME BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define HW_CAP_CPU BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define HW_CAP_PCI_DMA BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define HW_CAP_MSI BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define HW_CAP_CPU_Q BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define HW_CAP_HBM_DMA BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define HW_CAP_CLK_GATE BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define HW_CAP_SRAM_SCRAMBLER BIT(10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define HW_CAP_HBM_SCRAMBLER BIT(11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define HW_CAP_TPC0 BIT(24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define HW_CAP_TPC1 BIT(25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define HW_CAP_TPC2 BIT(26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define HW_CAP_TPC3 BIT(27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define HW_CAP_TPC4 BIT(28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define HW_CAP_TPC5 BIT(29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define HW_CAP_TPC6 BIT(30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define HW_CAP_TPC7 BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define HW_CAP_TPC_MASK GENMASK(31, 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define HW_CAP_TPC_SHIFT 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define GAUDI_CPU_PCI_MSB_ADDR(addr) (((addr) & GENMASK_ULL(49, 39)) >> 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define GAUDI_PCI_TO_CPU_ADDR(addr) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) do { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) (addr) &= ~GENMASK_ULL(49, 39); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) (addr) |= BIT_ULL(39); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) } while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define GAUDI_CPU_TO_PCI_ADDR(addr, extension) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) do { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) (addr) &= ~GENMASK_ULL(49, 39); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) (addr) |= (u64) (extension) << 39; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) } while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) enum gaudi_dma_channels {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) GAUDI_PCI_DMA_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) GAUDI_PCI_DMA_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) GAUDI_PCI_DMA_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) GAUDI_HBM_DMA_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) GAUDI_HBM_DMA_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) GAUDI_HBM_DMA_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) GAUDI_HBM_DMA_4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) GAUDI_HBM_DMA_5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) GAUDI_DMA_MAX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) enum gaudi_tpc_mask {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) GAUDI_TPC_MASK_TPC0 = 0x01,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) GAUDI_TPC_MASK_TPC1 = 0x02,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) GAUDI_TPC_MASK_TPC2 = 0x04,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) GAUDI_TPC_MASK_TPC3 = 0x08,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) GAUDI_TPC_MASK_TPC4 = 0x10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) GAUDI_TPC_MASK_TPC5 = 0x20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) GAUDI_TPC_MASK_TPC6 = 0x40,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) GAUDI_TPC_MASK_TPC7 = 0x80,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) GAUDI_TPC_MASK_ALL = 0xFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) * struct gaudi_internal_qman_info - Internal QMAN information.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) * @pq_kernel_addr: Kernel address of the PQ memory area in the host.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) * @pq_dma_addr: DMA address of the PQ memory area in the host.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) * @pq_size: Size of allocated host memory for PQ.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) struct gaudi_internal_qman_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) void *pq_kernel_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) dma_addr_t pq_dma_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) size_t pq_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) * struct gaudi_device - ASIC specific manage structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) * @cpucp_info_get: get information on device from CPU-CP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) * @hw_queues_lock: protects the H/W queues from concurrent access.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) * @clk_gate_mutex: protects code areas that require clock gating to be disabled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) * temporarily
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) * @internal_qmans: Internal QMANs information. The array size is larger than
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) * the actual number of internal queues because they are not in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) * consecutive order.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) * @hbm_bar_cur_addr: current address of HBM PCI bar.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) * @max_freq_value: current max clk frequency.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) * @events: array that holds all event id's
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) * @events_stat: array that holds histogram of all received events.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) * @events_stat_aggregate: same as events_stat but doesn't get cleared on reset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) * @hw_cap_initialized: This field contains a bit per H/W engine. When that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) * engine is initialized, that bit is set by the driver to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) * signal we can use this engine in later code paths.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) * Each bit is cleared upon reset of its corresponding H/W
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) * engine.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) * @multi_msi_mode: whether we are working in multi MSI single MSI mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) * Multi MSI is possible only with IOMMU enabled.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) * @mmu_cache_inv_pi: PI for MMU cache invalidation flow. The H/W expects an
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) * 8-bit value so use u8.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) struct gaudi_device {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) int (*cpucp_info_get)(struct hl_device *hdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) /* TODO: remove hw_queues_lock after moving to scheduler code */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) spinlock_t hw_queues_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) struct mutex clk_gate_mutex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) struct gaudi_internal_qman_info internal_qmans[GAUDI_QUEUE_ID_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) u64 hbm_bar_cur_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) u64 max_freq_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) u32 events[GAUDI_EVENT_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) u32 events_stat[GAUDI_EVENT_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) u32 events_stat_aggregate[GAUDI_EVENT_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) u32 hw_cap_initialized;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) u8 multi_msi_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) u8 mmu_cache_inv_pi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) void gaudi_init_security(struct hl_device *hdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) void gaudi_add_device_attr(struct hl_device *hdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) struct attribute_group *dev_attr_grp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) void gaudi_set_pll_profile(struct hl_device *hdev, enum hl_pll_frequency freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) int gaudi_debug_coresight(struct hl_device *hdev, void *data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) void gaudi_halt_coresight(struct hl_device *hdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) int gaudi_get_clk_rate(struct hl_device *hdev, u32 *cur_clk, u32 *max_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) void gaudi_mmu_prepare_reg(struct hl_device *hdev, u64 reg, u32 asid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) #endif /* GAUDIP_H_ */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags