^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright 2016-2019 HabanaLabs, Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * All Rights Reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include "habanalabs.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include "../include/hw_ip/pci/pci_general.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define HL_PLDM_PCI_ELBI_TIMEOUT_MSEC (HL_PCI_ELBI_TIMEOUT_MSEC * 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define IATU_REGION_CTRL_REGION_EN_MASK BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define IATU_REGION_CTRL_MATCH_MODE_MASK BIT(30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define IATU_REGION_CTRL_NUM_MATCH_EN_MASK BIT(19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define IATU_REGION_CTRL_BAR_NUM_MASK GENMASK(10, 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) * hl_pci_bars_map() - Map PCI BARs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * @hdev: Pointer to hl_device structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) * @name: Array of BAR names.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) * @is_wc: Array with flag per BAR whether a write-combined mapping is needed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) * Request PCI regions and map them to kernel virtual addresses.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) * Return: 0 on success, non-zero for failure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) int hl_pci_bars_map(struct hl_device *hdev, const char * const name[3],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) bool is_wc[3])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) struct pci_dev *pdev = hdev->pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) int rc, i, bar;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) rc = pci_request_regions(pdev, HL_NAME);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) if (rc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) dev_err(hdev->dev, "Cannot obtain PCI resources\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) for (i = 0 ; i < 3 ; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) bar = i * 2; /* 64-bit BARs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) hdev->pcie_bar[bar] = is_wc[i] ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) pci_ioremap_wc_bar(pdev, bar) :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) pci_ioremap_bar(pdev, bar);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) if (!hdev->pcie_bar[bar]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) dev_err(hdev->dev, "pci_ioremap%s_bar failed for %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) is_wc[i] ? "_wc" : "", name[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) rc = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) for (i = 2 ; i >= 0 ; i--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) bar = i * 2; /* 64-bit BARs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) if (hdev->pcie_bar[bar])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) iounmap(hdev->pcie_bar[bar]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) pci_release_regions(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) * hl_pci_bars_unmap() - Unmap PCI BARS.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) * @hdev: Pointer to hl_device structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) * Release all PCI BARs and unmap their virtual addresses.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) static void hl_pci_bars_unmap(struct hl_device *hdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) struct pci_dev *pdev = hdev->pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) int i, bar;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) for (i = 2 ; i >= 0 ; i--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) bar = i * 2; /* 64-bit BARs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) iounmap(hdev->pcie_bar[bar]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) pci_release_regions(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) * hl_pci_elbi_write() - Write through the ELBI interface.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) * @hdev: Pointer to hl_device structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) * @addr: Address to write to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) * @data: Data to write
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) * Return: 0 on success, negative value for failure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) static int hl_pci_elbi_write(struct hl_device *hdev, u64 addr, u32 data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) struct pci_dev *pdev = hdev->pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) ktime_t timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) u64 msec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) if (hdev->pldm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) msec = HL_PLDM_PCI_ELBI_TIMEOUT_MSEC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) msec = HL_PCI_ELBI_TIMEOUT_MSEC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) /* Clear previous status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) pci_write_config_dword(pdev, mmPCI_CONFIG_ELBI_STS, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) pci_write_config_dword(pdev, mmPCI_CONFIG_ELBI_ADDR, (u32) addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) pci_write_config_dword(pdev, mmPCI_CONFIG_ELBI_DATA, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) pci_write_config_dword(pdev, mmPCI_CONFIG_ELBI_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) PCI_CONFIG_ELBI_CTRL_WRITE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) timeout = ktime_add_ms(ktime_get(), msec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) for (;;) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) pci_read_config_dword(pdev, mmPCI_CONFIG_ELBI_STS, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) if (val & PCI_CONFIG_ELBI_STS_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) if (ktime_compare(ktime_get(), timeout) > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) pci_read_config_dword(pdev, mmPCI_CONFIG_ELBI_STS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) usleep_range(300, 500);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) if ((val & PCI_CONFIG_ELBI_STS_MASK) == PCI_CONFIG_ELBI_STS_DONE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) if (val & PCI_CONFIG_ELBI_STS_ERR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) if (!(val & PCI_CONFIG_ELBI_STS_MASK)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) dev_err(hdev->dev, "ELBI write didn't finish in time\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) dev_err(hdev->dev, "ELBI write has undefined bits in status\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) * hl_pci_iatu_write() - iatu write routine.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) * @hdev: Pointer to hl_device structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) * @addr: Address to write to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) * @data: Data to write
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) * Return: 0 on success, negative value for failure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) int hl_pci_iatu_write(struct hl_device *hdev, u32 addr, u32 data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) struct asic_fixed_properties *prop = &hdev->asic_prop;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) u32 dbi_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) dbi_offset = addr & 0xFFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) /* Ignore result of writing to pcie_aux_dbi_reg_addr as it could fail
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) * in case the firmware security is enabled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) hl_pci_elbi_write(hdev, prop->pcie_aux_dbi_reg_addr, 0x00300000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) rc = hl_pci_elbi_write(hdev, prop->pcie_dbi_base_address + dbi_offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) * hl_pci_reset_link_through_bridge() - Reset PCI link.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) * @hdev: Pointer to hl_device structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) static void hl_pci_reset_link_through_bridge(struct hl_device *hdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) struct pci_dev *pdev = hdev->pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) struct pci_dev *parent_port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) u16 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) parent_port = pdev->bus->self;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) pci_read_config_word(parent_port, PCI_BRIDGE_CONTROL, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) val |= PCI_BRIDGE_CTL_BUS_RESET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) pci_write_config_word(parent_port, PCI_BRIDGE_CONTROL, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) ssleep(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) val &= ~(PCI_BRIDGE_CTL_BUS_RESET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) pci_write_config_word(parent_port, PCI_BRIDGE_CONTROL, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) ssleep(3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) * hl_pci_set_inbound_region() - Configure inbound region
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) * @hdev: Pointer to hl_device structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) * @region: Inbound region number.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) * @pci_region: Inbound region parameters.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) * Configure the iATU inbound region.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) * Return: 0 on success, negative value for failure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) int hl_pci_set_inbound_region(struct hl_device *hdev, u8 region,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) struct hl_inbound_pci_region *pci_region)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) struct asic_fixed_properties *prop = &hdev->asic_prop;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) u64 bar_phys_base, region_base, region_end_address;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) u32 offset, ctrl_reg_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) int rc = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) /* region offset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) offset = (0x200 * region) + 0x100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) if (pci_region->mode == PCI_ADDRESS_MATCH_MODE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) bar_phys_base = hdev->pcie_bar_phys[pci_region->bar];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) region_base = bar_phys_base + pci_region->offset_in_bar;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) region_end_address = region_base + pci_region->size - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) rc |= hl_pci_iatu_write(hdev, offset + 0x8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) lower_32_bits(region_base));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) rc |= hl_pci_iatu_write(hdev, offset + 0xC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) upper_32_bits(region_base));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) rc |= hl_pci_iatu_write(hdev, offset + 0x10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) lower_32_bits(region_end_address));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) /* Point to the specified address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) rc |= hl_pci_iatu_write(hdev, offset + 0x14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) lower_32_bits(pci_region->addr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) rc |= hl_pci_iatu_write(hdev, offset + 0x18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) upper_32_bits(pci_region->addr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) rc |= hl_pci_iatu_write(hdev, offset + 0x0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) /* Enable + bar/address match + match enable + bar number */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) ctrl_reg_val = FIELD_PREP(IATU_REGION_CTRL_REGION_EN_MASK, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) ctrl_reg_val |= FIELD_PREP(IATU_REGION_CTRL_MATCH_MODE_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) pci_region->mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) ctrl_reg_val |= FIELD_PREP(IATU_REGION_CTRL_NUM_MATCH_EN_MASK, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) if (pci_region->mode == PCI_BAR_MATCH_MODE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) ctrl_reg_val |= FIELD_PREP(IATU_REGION_CTRL_BAR_NUM_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) pci_region->bar);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) rc |= hl_pci_iatu_write(hdev, offset + 0x4, ctrl_reg_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) /* Return the DBI window to the default location
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) * Ignore result of writing to pcie_aux_dbi_reg_addr as it could fail
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) * in case the firmware security is enabled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) hl_pci_elbi_write(hdev, prop->pcie_aux_dbi_reg_addr, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) dev_err(hdev->dev, "failed to map bar %u to 0x%08llx\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) pci_region->bar, pci_region->addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) * hl_pci_set_outbound_region() - Configure outbound region 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) * @hdev: Pointer to hl_device structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) * @pci_region: Outbound region parameters.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) * Configure the iATU outbound region 0.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) * Return: 0 on success, negative value for failure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) int hl_pci_set_outbound_region(struct hl_device *hdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) struct hl_outbound_pci_region *pci_region)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) struct asic_fixed_properties *prop = &hdev->asic_prop;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) u64 outbound_region_end_address;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) int rc = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) /* Outbound Region 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) outbound_region_end_address =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) pci_region->addr + pci_region->size - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) rc |= hl_pci_iatu_write(hdev, 0x008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) lower_32_bits(pci_region->addr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) rc |= hl_pci_iatu_write(hdev, 0x00C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) upper_32_bits(pci_region->addr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) rc |= hl_pci_iatu_write(hdev, 0x010,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) lower_32_bits(outbound_region_end_address));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) rc |= hl_pci_iatu_write(hdev, 0x014, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) if ((hdev->power9_64bit_dma_enable) && (hdev->dma_mask == 64))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) rc |= hl_pci_iatu_write(hdev, 0x018, 0x08000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) rc |= hl_pci_iatu_write(hdev, 0x018, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) rc |= hl_pci_iatu_write(hdev, 0x020,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) upper_32_bits(outbound_region_end_address));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) /* Increase region size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) rc |= hl_pci_iatu_write(hdev, 0x000, 0x00002000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) /* Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) rc |= hl_pci_iatu_write(hdev, 0x004, 0x80000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) /* Return the DBI window to the default location
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) * Ignore result of writing to pcie_aux_dbi_reg_addr as it could fail
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) * in case the firmware security is enabled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) hl_pci_elbi_write(hdev, prop->pcie_aux_dbi_reg_addr, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) * hl_pci_set_dma_mask() - Set DMA masks for the device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) * @hdev: Pointer to hl_device structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) * This function sets the DMA masks (regular and consistent) for a specified
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) * value. If it doesn't succeed, it tries to set it to a fall-back value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) * Return: 0 on success, non-zero for failure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) static int hl_pci_set_dma_mask(struct hl_device *hdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) struct pci_dev *pdev = hdev->pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) /* set DMA mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(hdev->dma_mask));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) if (rc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) dev_err(hdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) "Failed to set pci dma mask to %d bits, error %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) hdev->dma_mask, rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(hdev->dma_mask));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) if (rc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) dev_err(hdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) "Failed to set pci consistent dma mask to %d bits, error %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) hdev->dma_mask, rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) * hl_pci_init() - PCI initialization code.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) * @hdev: Pointer to hl_device structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) * @cpu_boot_status_reg: status register of the device's CPU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) * @boot_err0_reg: boot error register of the device's CPU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) * @preboot_ver_timeout: how much to wait before bailing out on reading
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) * the preboot version
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) * Set DMA masks, initialize the PCI controller and map the PCI BARs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) * Return: 0 on success, non-zero for failure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) int hl_pci_init(struct hl_device *hdev, u32 cpu_boot_status_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) u32 boot_err0_reg, u32 preboot_ver_timeout)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) struct pci_dev *pdev = hdev->pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) if (hdev->reset_pcilink)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) hl_pci_reset_link_through_bridge(hdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) rc = pci_enable_device_mem(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) if (rc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) dev_err(hdev->dev, "can't enable PCI device\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) pci_set_master(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) rc = hdev->asic_funcs->pci_bars_map(hdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) if (rc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) dev_err(hdev->dev, "Failed to initialize PCI BARs\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) goto disable_device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) rc = hdev->asic_funcs->init_iatu(hdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) if (rc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) dev_err(hdev->dev, "Failed to initialize iATU\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) goto unmap_pci_bars;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) rc = hl_pci_set_dma_mask(hdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) goto unmap_pci_bars;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) /* Before continuing in the initialization, we need to read the preboot
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) * version to determine whether we run with a security-enabled firmware
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) * The check will be done in each ASIC's specific code
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) rc = hl_fw_read_preboot_ver(hdev, cpu_boot_status_reg, boot_err0_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) preboot_ver_timeout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) goto unmap_pci_bars;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) unmap_pci_bars:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) hl_pci_bars_unmap(hdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) disable_device:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) pci_clear_master(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) pci_disable_device(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) * hl_fw_fini() - PCI finalization code.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) * @hdev: Pointer to hl_device structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) * Unmap PCI bars and disable PCI device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) void hl_pci_fini(struct hl_device *hdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) hl_pci_bars_unmap(hdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) pci_clear_master(hdev->pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) pci_disable_device(hdev->pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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