^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright 2016-2019 HabanaLabs, Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * All Rights Reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #ifndef HABANALABSP_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #define HABANALABSP_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include "../include/common/cpucp_if.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include "../include/common/qman_if.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <uapi/misc/habanalabs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/cdev.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/iopoll.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/irqreturn.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/dma-direction.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/scatterlist.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/hashtable.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/bitfield.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define HL_NAME "habanalabs"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) /* Use upper bits of mmap offset to store habana driver specific information.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) * bits[63:62] - Encode mmap type
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) * bits[45:0] - mmap offset value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) * NOTE: struct vm_area_struct.vm_pgoff uses offset in pages. Hence, these
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) * defines are w.r.t to PAGE_SIZE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define HL_MMAP_TYPE_SHIFT (62 - PAGE_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define HL_MMAP_TYPE_MASK (0x3ull << HL_MMAP_TYPE_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define HL_MMAP_TYPE_CB (0x2ull << HL_MMAP_TYPE_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define HL_MMAP_OFFSET_VALUE_MASK (0x3FFFFFFFFFFFull >> PAGE_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define HL_MMAP_OFFSET_VALUE_GET(off) (off & HL_MMAP_OFFSET_VALUE_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define HL_PENDING_RESET_PER_SEC 30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define HL_HARD_RESET_MAX_TIMEOUT 120
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define HL_DEVICE_TIMEOUT_USEC 1000000 /* 1 s */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define HL_HEARTBEAT_PER_USEC 5000000 /* 5 s */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define HL_PLL_LOW_JOB_FREQ_USEC 5000000 /* 5 s */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define HL_CPUCP_INFO_TIMEOUT_USEC 10000000 /* 10s */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define HL_CPUCP_EEPROM_TIMEOUT_USEC 10000000 /* 10s */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define HL_PCI_ELBI_TIMEOUT_MSEC 10 /* 10ms */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define HL_SIM_MAX_TIMEOUT_US 10000000 /* 10s */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define HL_IDLE_BUSY_TS_ARR_SIZE 4096
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) /* Memory */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define MEM_HASH_TABLE_BITS 7 /* 1 << 7 buckets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) /* MMU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define MMU_HASH_TABLE_BITS 7 /* 1 << 7 buckets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) * HL_RSVD_SOBS 'sync stream' reserved sync objects per QMAN stream
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) * HL_RSVD_MONS 'sync stream' reserved monitors per QMAN stream
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define HL_RSVD_SOBS 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define HL_RSVD_MONS 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define HL_RSVD_SOBS_IN_USE 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define HL_RSVD_MONS_IN_USE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define HL_MAX_SOB_VAL (1 << 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define IS_POWER_OF_2(n) (n != 0 && ((n & (n - 1)) == 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define IS_MAX_PENDING_CS_VALID(n) (IS_POWER_OF_2(n) && (n > 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define HL_PCI_NUM_BARS 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define HL_MAX_DCORES 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) * struct pgt_info - MMU hop page info.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) * @node: hash linked-list node for the pgts shadow hash of pgts.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) * @phys_addr: physical address of the pgt.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) * @shadow_addr: shadow hop in the host.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) * @ctx: pointer to the owner ctx.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) * @num_of_ptes: indicates how many ptes are used in the pgt.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) * The MMU page tables hierarchy is placed on the DRAM. When a new level (hop)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) * is needed during mapping, a new page is allocated and this structure holds
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) * its essential information. During unmapping, if no valid PTEs remained in the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) * page, it is freed with its pgt_info structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) struct pgt_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) struct hlist_node node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) u64 phys_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) u64 shadow_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) struct hl_ctx *ctx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) int num_of_ptes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) struct hl_device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) struct hl_fpriv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) * enum hl_pci_match_mode - pci match mode per region
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) * @PCI_ADDRESS_MATCH_MODE: address match mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) * @PCI_BAR_MATCH_MODE: bar match mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) enum hl_pci_match_mode {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) PCI_ADDRESS_MATCH_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) PCI_BAR_MATCH_MODE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) * enum hl_fw_component - F/W components to read version through registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) * @FW_COMP_UBOOT: u-boot.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) * @FW_COMP_PREBOOT: preboot.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) enum hl_fw_component {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) FW_COMP_UBOOT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) FW_COMP_PREBOOT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) * enum hl_queue_type - Supported QUEUE types.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) * @QUEUE_TYPE_NA: queue is not available.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) * @QUEUE_TYPE_EXT: external queue which is a DMA channel that may access the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) * host.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) * @QUEUE_TYPE_INT: internal queue that performs DMA inside the device's
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) * memories and/or operates the compute engines.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) * @QUEUE_TYPE_CPU: S/W queue for communication with the device's CPU.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) * @QUEUE_TYPE_HW: queue of DMA and compute engines jobs, for which completion
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) * notifications are sent by H/W.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) enum hl_queue_type {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) QUEUE_TYPE_NA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) QUEUE_TYPE_EXT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) QUEUE_TYPE_INT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) QUEUE_TYPE_CPU,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) QUEUE_TYPE_HW
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) enum hl_cs_type {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) CS_TYPE_DEFAULT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) CS_TYPE_SIGNAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) CS_TYPE_WAIT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) * struct hl_inbound_pci_region - inbound region descriptor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) * @mode: pci match mode for this region
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) * @addr: region target address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) * @size: region size in bytes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) * @offset_in_bar: offset within bar (address match mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) * @bar: bar id
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) struct hl_inbound_pci_region {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) enum hl_pci_match_mode mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) u64 addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) u64 size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) u64 offset_in_bar;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) u8 bar;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) * struct hl_outbound_pci_region - outbound region descriptor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) * @addr: region target address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) * @size: region size in bytes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) struct hl_outbound_pci_region {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) u64 addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) u64 size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) * struct hl_hw_sob - H/W SOB info.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) * @hdev: habanalabs device structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) * @kref: refcount of this SOB. The SOB will reset once the refcount is zero.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) * @sob_id: id of this SOB.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) * @q_idx: the H/W queue that uses this SOB.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) struct hl_hw_sob {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) struct hl_device *hdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) struct kref kref;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) u32 sob_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) u32 q_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) * struct hw_queue_properties - queue information.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) * @type: queue type.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) * @driver_only: true if only the driver is allowed to send a job to this queue,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) * false otherwise.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) * @requires_kernel_cb: true if a CB handle must be provided for jobs on this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) * queue, false otherwise (a CB address must be provided).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) * @supports_sync_stream: True if queue supports sync stream
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) struct hw_queue_properties {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) enum hl_queue_type type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) u8 driver_only;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) u8 requires_kernel_cb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) u8 supports_sync_stream;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) * enum vm_type_t - virtual memory mapping request information.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) * @VM_TYPE_USERPTR: mapping of user memory to device virtual address.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) * @VM_TYPE_PHYS_PACK: mapping of DRAM memory to device virtual address.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) enum vm_type_t {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) VM_TYPE_USERPTR = 0x1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) VM_TYPE_PHYS_PACK = 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) * enum hl_device_hw_state - H/W device state. use this to understand whether
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) * to do reset before hw_init or not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) * @HL_DEVICE_HW_STATE_CLEAN: H/W state is clean. i.e. after hard reset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) * @HL_DEVICE_HW_STATE_DIRTY: H/W state is dirty. i.e. we started to execute
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) * hw_init
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) enum hl_device_hw_state {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) HL_DEVICE_HW_STATE_CLEAN = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) HL_DEVICE_HW_STATE_DIRTY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) * struct hl_mmu_properties - ASIC specific MMU address translation properties.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) * @start_addr: virtual start address of the memory region.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) * @end_addr: virtual end address of the memory region.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) * @hop0_shift: shift of hop 0 mask.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) * @hop1_shift: shift of hop 1 mask.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) * @hop2_shift: shift of hop 2 mask.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) * @hop3_shift: shift of hop 3 mask.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) * @hop4_shift: shift of hop 4 mask.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) * @hop5_shift: shift of hop 5 mask.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) * @hop0_mask: mask to get the PTE address in hop 0.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) * @hop1_mask: mask to get the PTE address in hop 1.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) * @hop2_mask: mask to get the PTE address in hop 2.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) * @hop3_mask: mask to get the PTE address in hop 3.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) * @hop4_mask: mask to get the PTE address in hop 4.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) * @hop5_mask: mask to get the PTE address in hop 5.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) * @page_size: default page size used to allocate memory.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) * @num_hops: The amount of hops supported by the translation table.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) struct hl_mmu_properties {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) u64 start_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) u64 end_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) u64 hop0_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) u64 hop1_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) u64 hop2_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) u64 hop3_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) u64 hop4_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) u64 hop5_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) u64 hop0_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) u64 hop1_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) u64 hop2_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) u64 hop3_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) u64 hop4_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) u64 hop5_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) u32 page_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) u32 num_hops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) * struct asic_fixed_properties - ASIC specific immutable properties.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) * @hw_queues_props: H/W queues properties.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) * @cpucp_info: received various information from CPU-CP regarding the H/W, e.g.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) * available sensors.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) * @uboot_ver: F/W U-boot version.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) * @preboot_ver: F/W Preboot version.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) * @dmmu: DRAM MMU address translation properties.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) * @pmmu: PCI (host) MMU address translation properties.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) * @pmmu_huge: PCI (host) MMU address translation properties for memory
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) * allocated with huge pages.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) * @sram_base_address: SRAM physical start address.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) * @sram_end_address: SRAM physical end address.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) * @sram_user_base_address - SRAM physical start address for user access.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) * @dram_base_address: DRAM physical start address.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) * @dram_end_address: DRAM physical end address.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) * @dram_user_base_address: DRAM physical start address for user access.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) * @dram_size: DRAM total size.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) * @dram_pci_bar_size: size of PCI bar towards DRAM.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) * @max_power_default: max power of the device after reset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) * @dram_size_for_default_page_mapping: DRAM size needed to map to avoid page
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) * fault.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) * @pcie_dbi_base_address: Base address of the PCIE_DBI block.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) * @pcie_aux_dbi_reg_addr: Address of the PCIE_AUX DBI register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) * @mmu_pgt_addr: base physical address in DRAM of MMU page tables.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) * @mmu_dram_default_page_addr: DRAM default page physical address.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) * @cb_va_start_addr: virtual start address of command buffers which are mapped
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) * to the device's MMU.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) * @cb_va_end_addr: virtual end address of command buffers which are mapped to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) * the device's MMU.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) * @mmu_pgt_size: MMU page tables total size.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) * @mmu_pte_size: PTE size in MMU page tables.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) * @mmu_hop_table_size: MMU hop table size.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) * @mmu_hop0_tables_total_size: total size of MMU hop0 tables.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) * @dram_page_size: page size for MMU DRAM allocation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) * @cfg_size: configuration space size on SRAM.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) * @sram_size: total size of SRAM.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) * @max_asid: maximum number of open contexts (ASIDs).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) * @num_of_events: number of possible internal H/W IRQs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) * @psoc_pci_pll_nr: PCI PLL NR value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) * @psoc_pci_pll_nf: PCI PLL NF value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) * @psoc_pci_pll_od: PCI PLL OD value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) * @psoc_pci_pll_div_factor: PCI PLL DIV FACTOR 1 value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) * @psoc_timestamp_frequency: frequency of the psoc timestamp clock.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) * @high_pll: high PLL frequency used by the device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) * @cb_pool_cb_cnt: number of CBs in the CB pool.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) * @cb_pool_cb_size: size of each CB in the CB pool.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) * @max_pending_cs: maximum of concurrent pending command submissions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) * @max_queues: maximum amount of queues in the system
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) * @sync_stream_first_sob: first sync object available for sync stream use
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) * @sync_stream_first_mon: first monitor available for sync stream use
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) * @first_available_user_sob: first sob available for the user
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) * @first_available_user_mon: first monitor available for the user
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) * @tpc_enabled_mask: which TPCs are enabled.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) * @completion_queues_count: number of completion queues.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) * @fw_security_disabled: true if security measures are disabled in firmware,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) * false otherwise
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) struct asic_fixed_properties {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) struct hw_queue_properties *hw_queues_props;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) struct cpucp_info cpucp_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) char uboot_ver[VERSION_MAX_LEN];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) char preboot_ver[VERSION_MAX_LEN];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) struct hl_mmu_properties dmmu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) struct hl_mmu_properties pmmu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) struct hl_mmu_properties pmmu_huge;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) u64 sram_base_address;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) u64 sram_end_address;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) u64 sram_user_base_address;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) u64 dram_base_address;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) u64 dram_end_address;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) u64 dram_user_base_address;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) u64 dram_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) u64 dram_pci_bar_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) u64 max_power_default;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) u64 dram_size_for_default_page_mapping;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) u64 pcie_dbi_base_address;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) u64 pcie_aux_dbi_reg_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) u64 mmu_pgt_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) u64 mmu_dram_default_page_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) u64 cb_va_start_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) u64 cb_va_end_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) u32 mmu_pgt_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) u32 mmu_pte_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) u32 mmu_hop_table_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) u32 mmu_hop0_tables_total_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) u32 dram_page_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) u32 cfg_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) u32 sram_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) u32 max_asid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) u32 num_of_events;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) u32 psoc_pci_pll_nr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) u32 psoc_pci_pll_nf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) u32 psoc_pci_pll_od;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) u32 psoc_pci_pll_div_factor;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) u32 psoc_timestamp_frequency;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) u32 high_pll;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) u32 cb_pool_cb_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) u32 cb_pool_cb_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) u32 max_pending_cs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) u32 max_queues;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) u16 sync_stream_first_sob;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) u16 sync_stream_first_mon;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) u16 first_available_user_sob[HL_MAX_DCORES];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) u16 first_available_user_mon[HL_MAX_DCORES];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) u8 tpc_enabled_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) u8 completion_queues_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) u8 fw_security_disabled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) * struct hl_fence - software synchronization primitive
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) * @completion: fence is implemented using completion
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) * @refcount: refcount for this fence
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) * @error: mark this fence with error
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) struct hl_fence {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) struct completion completion;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) struct kref refcount;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) int error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) * struct hl_cs_compl - command submission completion object.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) * @base_fence: hl fence object.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) * @lock: spinlock to protect fence.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) * @hdev: habanalabs device structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) * @hw_sob: the H/W SOB used in this signal/wait CS.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) * @cs_seq: command submission sequence number.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) * @type: type of the CS - signal/wait.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) * @sob_val: the SOB value that is used in this signal/wait CS.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) struct hl_cs_compl {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) struct hl_fence base_fence;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) spinlock_t lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) struct hl_device *hdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) struct hl_hw_sob *hw_sob;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) u64 cs_seq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) enum hl_cs_type type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) u16 sob_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) * Command Buffers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) * struct hl_cb_mgr - describes a Command Buffer Manager.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) * @cb_lock: protects cb_handles.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) * @cb_handles: an idr to hold all command buffer handles.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) struct hl_cb_mgr {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) spinlock_t cb_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) struct idr cb_handles; /* protected by cb_lock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) * struct hl_cb - describes a Command Buffer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) * @refcount: reference counter for usage of the CB.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) * @hdev: pointer to device this CB belongs to.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) * @ctx: pointer to the CB owner's context.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) * @lock: spinlock to protect mmap/cs flows.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) * @debugfs_list: node in debugfs list of command buffers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) * @pool_list: node in pool list of command buffers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) * @va_block_list: list of virtual addresses blocks of the CB if it is mapped to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) * the device's MMU.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) * @id: the CB's ID.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) * @kernel_address: Holds the CB's kernel virtual address.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) * @bus_address: Holds the CB's DMA address.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) * @mmap_size: Holds the CB's size that was mmaped.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) * @size: holds the CB's size.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) * @cs_cnt: holds number of CS that this CB participates in.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) * @mmap: true if the CB is currently mmaped to user.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) * @is_pool: true if CB was acquired from the pool, false otherwise.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) * @is_internal: internaly allocated
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) * @is_mmu_mapped: true if the CB is mapped to the device's MMU.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) struct hl_cb {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) struct kref refcount;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) struct hl_device *hdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) struct hl_ctx *ctx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) spinlock_t lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) struct list_head debugfs_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) struct list_head pool_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) struct list_head va_block_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) u64 id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) void *kernel_address;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) dma_addr_t bus_address;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) u32 mmap_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) u32 size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) u32 cs_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) u8 mmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) u8 is_pool;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) u8 is_internal;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) u8 is_mmu_mapped;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) * QUEUES
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) struct hl_cs_job;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) /* Queue length of external and HW queues */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) #define HL_QUEUE_LENGTH 4096
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) #define HL_QUEUE_SIZE_IN_BYTES (HL_QUEUE_LENGTH * HL_BD_SIZE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) #if (HL_MAX_JOBS_PER_CS > HL_QUEUE_LENGTH)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) #error "HL_QUEUE_LENGTH must be greater than HL_MAX_JOBS_PER_CS"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) /* HL_CQ_LENGTH is in units of struct hl_cq_entry */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) #define HL_CQ_LENGTH HL_QUEUE_LENGTH
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) #define HL_CQ_SIZE_IN_BYTES (HL_CQ_LENGTH * HL_CQ_ENTRY_SIZE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) /* Must be power of 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) #define HL_EQ_LENGTH 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) #define HL_EQ_SIZE_IN_BYTES (HL_EQ_LENGTH * HL_EQ_ENTRY_SIZE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) /* Host <-> CPU-CP shared memory size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) #define HL_CPU_ACCESSIBLE_MEM_SIZE SZ_2M
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) * struct hl_hw_queue - describes a H/W transport queue.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) * @hw_sob: array of the used H/W SOBs by this H/W queue.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) * @shadow_queue: pointer to a shadow queue that holds pointers to jobs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) * @queue_type: type of queue.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) * @kernel_address: holds the queue's kernel virtual address.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) * @bus_address: holds the queue's DMA address.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) * @pi: holds the queue's pi value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) * @ci: holds the queue's ci value, AS CALCULATED BY THE DRIVER (not real ci).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) * @hw_queue_id: the id of the H/W queue.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) * @cq_id: the id for the corresponding CQ for this H/W queue.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) * @msi_vec: the IRQ number of the H/W queue.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) * @int_queue_len: length of internal queue (number of entries).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) * @next_sob_val: the next value to use for the currently used SOB.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) * @base_sob_id: the base SOB id of the SOBs used by this queue.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) * @base_mon_id: the base MON id of the MONs used by this queue.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) * @valid: is the queue valid (we have array of 32 queues, not all of them
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) * exist).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) * @curr_sob_offset: the id offset to the currently used SOB from the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) * HL_RSVD_SOBS that are being used by this queue.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) * @supports_sync_stream: True if queue supports sync stream
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) struct hl_hw_queue {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) struct hl_hw_sob hw_sob[HL_RSVD_SOBS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) struct hl_cs_job **shadow_queue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) enum hl_queue_type queue_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) void *kernel_address;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) dma_addr_t bus_address;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) u32 pi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) atomic_t ci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) u32 hw_queue_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) u32 cq_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) u32 msi_vec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) u16 int_queue_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) u16 next_sob_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) u16 base_sob_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) u16 base_mon_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) u8 valid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) u8 curr_sob_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) u8 supports_sync_stream;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) * struct hl_cq - describes a completion queue
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) * @hdev: pointer to the device structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) * @kernel_address: holds the queue's kernel virtual address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) * @bus_address: holds the queue's DMA address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) * @cq_idx: completion queue index in array
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) * @hw_queue_id: the id of the matching H/W queue
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) * @ci: ci inside the queue
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) * @pi: pi inside the queue
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) * @free_slots_cnt: counter of free slots in queue
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) struct hl_cq {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) struct hl_device *hdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) void *kernel_address;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) dma_addr_t bus_address;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) u32 cq_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) u32 hw_queue_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) u32 ci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) u32 pi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) atomic_t free_slots_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) * struct hl_eq - describes the event queue (single one per device)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) * @hdev: pointer to the device structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) * @kernel_address: holds the queue's kernel virtual address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) * @bus_address: holds the queue's DMA address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) * @ci: ci inside the queue
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) struct hl_eq {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) struct hl_device *hdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) void *kernel_address;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) dma_addr_t bus_address;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) u32 ci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) * ASICs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) * enum hl_asic_type - supported ASIC types.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) * @ASIC_INVALID: Invalid ASIC type.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) * @ASIC_GOYA: Goya device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) * @ASIC_GAUDI: Gaudi device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) enum hl_asic_type {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) ASIC_INVALID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) ASIC_GOYA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) ASIC_GAUDI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) struct hl_cs_parser;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) * enum hl_pm_mng_profile - power management profile.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) * @PM_AUTO: internal clock is set by the Linux driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) * @PM_MANUAL: internal clock is set by the user.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) * @PM_LAST: last power management type.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) enum hl_pm_mng_profile {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) PM_AUTO = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) PM_MANUAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) PM_LAST
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) * enum hl_pll_frequency - PLL frequency.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) * @PLL_HIGH: high frequency.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) * @PLL_LOW: low frequency.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) * @PLL_LAST: last frequency values that were configured by the user.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) enum hl_pll_frequency {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) PLL_HIGH = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) PLL_LOW,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) PLL_LAST
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) #define PLL_REF_CLK 50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) enum div_select_defs {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) DIV_SEL_REF_CLK = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) DIV_SEL_PLL_CLK = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) DIV_SEL_DIVIDED_REF = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) DIV_SEL_DIVIDED_PLL = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) * struct hl_asic_funcs - ASIC specific functions that are can be called from
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) * common code.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) * @early_init: sets up early driver state (pre sw_init), doesn't configure H/W.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) * @early_fini: tears down what was done in early_init.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) * @late_init: sets up late driver/hw state (post hw_init) - Optional.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) * @late_fini: tears down what was done in late_init (pre hw_fini) - Optional.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) * @sw_init: sets up driver state, does not configure H/W.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) * @sw_fini: tears down driver state, does not configure H/W.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) * @hw_init: sets up the H/W state.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) * @hw_fini: tears down the H/W state.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) * @halt_engines: halt engines, needed for reset sequence. This also disables
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) * interrupts from the device. Should be called before
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) * hw_fini and before CS rollback.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) * @suspend: handles IP specific H/W or SW changes for suspend.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) * @resume: handles IP specific H/W or SW changes for resume.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) * @cb_mmap: maps a CB.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) * @ring_doorbell: increment PI on a given QMAN.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) * @pqe_write: Write the PQ entry to the PQ. This is ASIC-specific
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) * function because the PQs are located in different memory areas
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) * per ASIC (SRAM, DRAM, Host memory) and therefore, the method of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) * writing the PQE must match the destination memory area
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) * properties.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) * @asic_dma_alloc_coherent: Allocate coherent DMA memory by calling
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) * dma_alloc_coherent(). This is ASIC function because
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) * its implementation is not trivial when the driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) * is loaded in simulation mode (not upstreamed).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) * @asic_dma_free_coherent: Free coherent DMA memory by calling
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) * dma_free_coherent(). This is ASIC function because
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) * its implementation is not trivial when the driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) * is loaded in simulation mode (not upstreamed).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) * @get_int_queue_base: get the internal queue base address.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) * @test_queues: run simple test on all queues for sanity check.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) * @asic_dma_pool_zalloc: small DMA allocation of coherent memory from DMA pool.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) * size of allocation is HL_DMA_POOL_BLK_SIZE.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) * @asic_dma_pool_free: free small DMA allocation from pool.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) * @cpu_accessible_dma_pool_alloc: allocate CPU PQ packet from DMA pool.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) * @cpu_accessible_dma_pool_free: free CPU PQ packet from DMA pool.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) * @hl_dma_unmap_sg: DMA unmap scatter-gather list.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) * @cs_parser: parse Command Submission.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) * @asic_dma_map_sg: DMA map scatter-gather list.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) * @get_dma_desc_list_size: get number of LIN_DMA packets required for CB.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) * @add_end_of_cb_packets: Add packets to the end of CB, if device requires it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) * @update_eq_ci: update event queue CI.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) * @context_switch: called upon ASID context switch.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) * @restore_phase_topology: clear all SOBs amd MONs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) * @debugfs_read32: debug interface for reading u32 from DRAM/SRAM.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) * @debugfs_write32: debug interface for writing u32 to DRAM/SRAM.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) * @add_device_attr: add ASIC specific device attributes.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) * @handle_eqe: handle event queue entry (IRQ) from CPU-CP.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) * @set_pll_profile: change PLL profile (manual/automatic).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) * @get_events_stat: retrieve event queue entries histogram.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) * @read_pte: read MMU page table entry from DRAM.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) * @write_pte: write MMU page table entry to DRAM.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) * @mmu_invalidate_cache: flush MMU STLB host/DRAM cache, either with soft
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) * (L1 only) or hard (L0 & L1) flush.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) * @mmu_invalidate_cache_range: flush specific MMU STLB cache lines with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) * ASID-VA-size mask.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) * @send_heartbeat: send is-alive packet to CPU-CP and verify response.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) * @set_clock_gating: enable/disable clock gating per engine according to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) * clock gating mask in hdev
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) * @disable_clock_gating: disable clock gating completely
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) * @debug_coresight: perform certain actions on Coresight for debugging.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) * @is_device_idle: return true if device is idle, false otherwise.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) * @soft_reset_late_init: perform certain actions needed after soft reset.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) * @hw_queues_lock: acquire H/W queues lock.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) * @hw_queues_unlock: release H/W queues lock.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) * @get_pci_id: retrieve PCI ID.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) * @get_eeprom_data: retrieve EEPROM data from F/W.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) * @send_cpu_message: send message to F/W. If the message is timedout, the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) * driver will eventually reset the device. The timeout can
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) * be determined by the calling function or it can be 0 and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) * then the timeout is the default timeout for the specific
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) * ASIC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) * @get_hw_state: retrieve the H/W state
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) * @pci_bars_map: Map PCI BARs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) * @init_iatu: Initialize the iATU unit inside the PCI controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) * @rreg: Read a register. Needed for simulator support.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) * @wreg: Write a register. Needed for simulator support.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) * @halt_coresight: stop the ETF and ETR traces.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) * @ctx_init: context dependent initialization.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) * @get_clk_rate: Retrieve the ASIC current and maximum clock rate in MHz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) * @get_queue_id_for_cq: Get the H/W queue id related to the given CQ index.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) * @read_device_fw_version: read the device's firmware versions that are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) * contained in registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) * @load_firmware_to_device: load the firmware to the device's memory
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) * @load_boot_fit_to_device: load boot fit to device's memory
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) * @get_signal_cb_size: Get signal CB size.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) * @get_wait_cb_size: Get wait CB size.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) * @gen_signal_cb: Generate a signal CB.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) * @gen_wait_cb: Generate a wait CB.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) * @reset_sob: Reset a SOB.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) * @set_dma_mask_from_fw: set the DMA mask in the driver according to the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) * firmware configuration
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) * @get_device_time: Get the device time.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) struct hl_asic_funcs {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) int (*early_init)(struct hl_device *hdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) int (*early_fini)(struct hl_device *hdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) int (*late_init)(struct hl_device *hdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) void (*late_fini)(struct hl_device *hdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) int (*sw_init)(struct hl_device *hdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) int (*sw_fini)(struct hl_device *hdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) int (*hw_init)(struct hl_device *hdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) void (*hw_fini)(struct hl_device *hdev, bool hard_reset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) void (*halt_engines)(struct hl_device *hdev, bool hard_reset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) int (*suspend)(struct hl_device *hdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) int (*resume)(struct hl_device *hdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) int (*cb_mmap)(struct hl_device *hdev, struct vm_area_struct *vma,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) void *cpu_addr, dma_addr_t dma_addr, size_t size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) void (*ring_doorbell)(struct hl_device *hdev, u32 hw_queue_id, u32 pi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) void (*pqe_write)(struct hl_device *hdev, __le64 *pqe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) struct hl_bd *bd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) void* (*asic_dma_alloc_coherent)(struct hl_device *hdev, size_t size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) dma_addr_t *dma_handle, gfp_t flag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) void (*asic_dma_free_coherent)(struct hl_device *hdev, size_t size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) void *cpu_addr, dma_addr_t dma_handle);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) void* (*get_int_queue_base)(struct hl_device *hdev, u32 queue_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) dma_addr_t *dma_handle, u16 *queue_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) int (*test_queues)(struct hl_device *hdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) void* (*asic_dma_pool_zalloc)(struct hl_device *hdev, size_t size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) gfp_t mem_flags, dma_addr_t *dma_handle);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) void (*asic_dma_pool_free)(struct hl_device *hdev, void *vaddr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) dma_addr_t dma_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) void* (*cpu_accessible_dma_pool_alloc)(struct hl_device *hdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) size_t size, dma_addr_t *dma_handle);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) void (*cpu_accessible_dma_pool_free)(struct hl_device *hdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) size_t size, void *vaddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) void (*hl_dma_unmap_sg)(struct hl_device *hdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) struct scatterlist *sgl, int nents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) enum dma_data_direction dir);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) int (*cs_parser)(struct hl_device *hdev, struct hl_cs_parser *parser);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) int (*asic_dma_map_sg)(struct hl_device *hdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) struct scatterlist *sgl, int nents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) enum dma_data_direction dir);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) u32 (*get_dma_desc_list_size)(struct hl_device *hdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) struct sg_table *sgt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) void (*add_end_of_cb_packets)(struct hl_device *hdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) void *kernel_address, u32 len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) u64 cq_addr, u32 cq_val, u32 msix_num,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) bool eb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) void (*update_eq_ci)(struct hl_device *hdev, u32 val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) int (*context_switch)(struct hl_device *hdev, u32 asid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) void (*restore_phase_topology)(struct hl_device *hdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) int (*debugfs_read32)(struct hl_device *hdev, u64 addr, u32 *val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) int (*debugfs_write32)(struct hl_device *hdev, u64 addr, u32 val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) int (*debugfs_read64)(struct hl_device *hdev, u64 addr, u64 *val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) int (*debugfs_write64)(struct hl_device *hdev, u64 addr, u64 val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) void (*add_device_attr)(struct hl_device *hdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) struct attribute_group *dev_attr_grp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) void (*handle_eqe)(struct hl_device *hdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) struct hl_eq_entry *eq_entry);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) void (*set_pll_profile)(struct hl_device *hdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) enum hl_pll_frequency freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) void* (*get_events_stat)(struct hl_device *hdev, bool aggregate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) u32 *size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) u64 (*read_pte)(struct hl_device *hdev, u64 addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) void (*write_pte)(struct hl_device *hdev, u64 addr, u64 val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) int (*mmu_invalidate_cache)(struct hl_device *hdev, bool is_hard,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) u32 flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) int (*mmu_invalidate_cache_range)(struct hl_device *hdev, bool is_hard,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) u32 asid, u64 va, u64 size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) int (*send_heartbeat)(struct hl_device *hdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) void (*set_clock_gating)(struct hl_device *hdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) void (*disable_clock_gating)(struct hl_device *hdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) int (*debug_coresight)(struct hl_device *hdev, void *data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) bool (*is_device_idle)(struct hl_device *hdev, u64 *mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) struct seq_file *s);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) int (*soft_reset_late_init)(struct hl_device *hdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) void (*hw_queues_lock)(struct hl_device *hdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) void (*hw_queues_unlock)(struct hl_device *hdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) u32 (*get_pci_id)(struct hl_device *hdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) int (*get_eeprom_data)(struct hl_device *hdev, void *data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) size_t max_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) int (*send_cpu_message)(struct hl_device *hdev, u32 *msg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) u16 len, u32 timeout, long *result);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) enum hl_device_hw_state (*get_hw_state)(struct hl_device *hdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) int (*pci_bars_map)(struct hl_device *hdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) int (*init_iatu)(struct hl_device *hdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) u32 (*rreg)(struct hl_device *hdev, u32 reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) void (*wreg)(struct hl_device *hdev, u32 reg, u32 val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) void (*halt_coresight)(struct hl_device *hdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) int (*ctx_init)(struct hl_ctx *ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) int (*get_clk_rate)(struct hl_device *hdev, u32 *cur_clk, u32 *max_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) u32 (*get_queue_id_for_cq)(struct hl_device *hdev, u32 cq_idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) void (*read_device_fw_version)(struct hl_device *hdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) enum hl_fw_component fwc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) int (*load_firmware_to_device)(struct hl_device *hdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) int (*load_boot_fit_to_device)(struct hl_device *hdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) u32 (*get_signal_cb_size)(struct hl_device *hdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) u32 (*get_wait_cb_size)(struct hl_device *hdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) void (*gen_signal_cb)(struct hl_device *hdev, void *data, u16 sob_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) void (*gen_wait_cb)(struct hl_device *hdev, void *data, u16 sob_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) u16 sob_val, u16 mon_id, u32 q_idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) void (*reset_sob)(struct hl_device *hdev, void *data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) void (*set_dma_mask_from_fw)(struct hl_device *hdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) u64 (*get_device_time)(struct hl_device *hdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) * CONTEXTS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) #define HL_KERNEL_ASID_ID 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) * struct hl_va_range - virtual addresses range.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) * @lock: protects the virtual addresses list.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) * @list: list of virtual addresses blocks available for mappings.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) * @start_addr: range start address.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) * @end_addr: range end address.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) struct hl_va_range {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) struct mutex lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) struct list_head list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) u64 start_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) u64 end_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) * struct hl_ctx - user/kernel context.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) * @mem_hash: holds mapping from virtual address to virtual memory area
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) * descriptor (hl_vm_phys_pg_list or hl_userptr).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) * @mmu_shadow_hash: holds a mapping from shadow address to pgt_info structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) * @hpriv: pointer to the private (Kernel Driver) data of the process (fd).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) * @hdev: pointer to the device structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) * @refcount: reference counter for the context. Context is released only when
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) * this hits 0l. It is incremented on CS and CS_WAIT.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) * @cs_pending: array of hl fence objects representing pending CS.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) * @host_va_range: holds available virtual addresses for host mappings.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) * @host_huge_va_range: holds available virtual addresses for host mappings
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) * with huge pages.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) * @dram_va_range: holds available virtual addresses for DRAM mappings.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) * @mem_hash_lock: protects the mem_hash.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) * @mmu_lock: protects the MMU page tables. Any change to the PGT, modifying the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) * MMU hash or walking the PGT requires talking this lock.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) * @debugfs_list: node in debugfs list of contexts.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) * @cb_va_pool: device VA pool for command buffers which are mapped to the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) * device's MMU.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) * @cs_sequence: sequence number for CS. Value is assigned to a CS and passed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) * to user so user could inquire about CS. It is used as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) * index to cs_pending array.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) * @dram_default_hops: array that holds all hops addresses needed for default
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) * DRAM mapping.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) * @cs_lock: spinlock to protect cs_sequence.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) * @dram_phys_mem: amount of used physical DRAM memory by this context.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) * @thread_ctx_switch_token: token to prevent multiple threads of the same
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) * context from running the context switch phase.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) * Only a single thread should run it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) * @thread_ctx_switch_wait_token: token to prevent the threads that didn't run
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) * the context switch phase from moving to their
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) * execution phase before the context switch phase
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) * has finished.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) * @asid: context's unique address space ID in the device's MMU.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) * @handle: context's opaque handle for user
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) struct hl_ctx {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) DECLARE_HASHTABLE(mem_hash, MEM_HASH_TABLE_BITS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) DECLARE_HASHTABLE(mmu_shadow_hash, MMU_HASH_TABLE_BITS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) struct hl_fpriv *hpriv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) struct hl_device *hdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) struct kref refcount;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) struct hl_fence **cs_pending;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) struct hl_va_range *host_va_range;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) struct hl_va_range *host_huge_va_range;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) struct hl_va_range *dram_va_range;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) struct mutex mem_hash_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) struct mutex mmu_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) struct list_head debugfs_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) struct hl_cs_counters cs_counters;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) struct gen_pool *cb_va_pool;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) u64 cs_sequence;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) u64 *dram_default_hops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) spinlock_t cs_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) atomic64_t dram_phys_mem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) atomic_t thread_ctx_switch_token;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) u32 thread_ctx_switch_wait_token;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) u32 asid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) u32 handle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) * struct hl_ctx_mgr - for handling multiple contexts.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) * @ctx_lock: protects ctx_handles.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) * @ctx_handles: idr to hold all ctx handles.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) struct hl_ctx_mgr {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) struct mutex ctx_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) struct idr ctx_handles;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) * COMMAND SUBMISSIONS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) * struct hl_userptr - memory mapping chunk information
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) * @vm_type: type of the VM.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) * @job_node: linked-list node for hanging the object on the Job's list.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) * @vec: pointer to the frame vector.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) * @sgt: pointer to the scatter-gather table that holds the pages.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) * @dir: for DMA unmapping, the direction must be supplied, so save it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) * @debugfs_list: node in debugfs list of command submissions.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) * @addr: user-space virtual address of the start of the memory area.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) * @size: size of the memory area to pin & map.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) * @dma_mapped: true if the SG was mapped to DMA addresses, false otherwise.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) struct hl_userptr {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) enum vm_type_t vm_type; /* must be first */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) struct list_head job_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) struct frame_vector *vec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) struct sg_table *sgt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) enum dma_data_direction dir;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) struct list_head debugfs_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) u64 addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) u32 size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) u8 dma_mapped;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) * struct hl_cs - command submission.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) * @jobs_in_queue_cnt: per each queue, maintain counter of submitted jobs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) * @ctx: the context this CS belongs to.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) * @job_list: list of the CS's jobs in the various queues.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) * @job_lock: spinlock for the CS's jobs list. Needed for free_job.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) * @refcount: reference counter for usage of the CS.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) * @fence: pointer to the fence object of this CS.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) * @signal_fence: pointer to the fence object of the signal CS (used by wait
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) * CS only).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) * @finish_work: workqueue object to run when CS is completed by H/W.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) * @work_tdr: delayed work node for TDR.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) * @mirror_node : node in device mirror list of command submissions.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) * @debugfs_list: node in debugfs list of command submissions.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) * @sequence: the sequence number of this CS.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) * @type: CS_TYPE_*.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) * @submitted: true if CS was submitted to H/W.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) * @completed: true if CS was completed by device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) * @timedout : true if CS was timedout.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) * @tdr_active: true if TDR was activated for this CS (to prevent
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) * double TDR activation).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) * @aborted: true if CS was aborted due to some device error.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) struct hl_cs {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) u16 *jobs_in_queue_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) struct hl_ctx *ctx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) struct list_head job_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) spinlock_t job_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) struct kref refcount;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) struct hl_fence *fence;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) struct hl_fence *signal_fence;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) struct work_struct finish_work;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) struct delayed_work work_tdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) struct list_head mirror_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) struct list_head debugfs_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) u64 sequence;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) enum hl_cs_type type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) u8 submitted;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) u8 completed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) u8 timedout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) u8 tdr_active;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) u8 aborted;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) * struct hl_cs_job - command submission job.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) * @cs_node: the node to hang on the CS jobs list.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) * @cs: the CS this job belongs to.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) * @user_cb: the CB we got from the user.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) * @patched_cb: in case of patching, this is internal CB which is submitted on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) * the queue instead of the CB we got from the IOCTL.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) * @finish_work: workqueue object to run when job is completed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) * @userptr_list: linked-list of userptr mappings that belong to this job and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) * wait for completion.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) * @debugfs_list: node in debugfs list of command submission jobs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) * @queue_type: the type of the H/W queue this job is submitted to.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) * @id: the id of this job inside a CS.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) * @hw_queue_id: the id of the H/W queue this job is submitted to.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) * @user_cb_size: the actual size of the CB we got from the user.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) * @job_cb_size: the actual size of the CB that we put on the queue.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) * @is_kernel_allocated_cb: true if the CB handle we got from the user holds a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) * handle to a kernel-allocated CB object, false
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) * otherwise (SRAM/DRAM/host address).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) * @contains_dma_pkt: whether the JOB contains at least one DMA packet. This
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) * info is needed later, when adding the 2xMSG_PROT at the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) * end of the JOB, to know which barriers to put in the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) * MSG_PROT packets. Relevant only for GAUDI as GOYA doesn't
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) * have streams so the engine can't be busy by another
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) * stream.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) struct hl_cs_job {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) struct list_head cs_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) struct hl_cs *cs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) struct hl_cb *user_cb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) struct hl_cb *patched_cb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) struct work_struct finish_work;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) struct list_head userptr_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) struct list_head debugfs_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) enum hl_queue_type queue_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) u32 id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) u32 hw_queue_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) u32 user_cb_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) u32 job_cb_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) u8 is_kernel_allocated_cb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) u8 contains_dma_pkt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) * struct hl_cs_parser - command submission parser properties.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) * @user_cb: the CB we got from the user.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) * @patched_cb: in case of patching, this is internal CB which is submitted on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) * the queue instead of the CB we got from the IOCTL.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) * @job_userptr_list: linked-list of userptr mappings that belong to the related
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) * job and wait for completion.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) * @cs_sequence: the sequence number of the related CS.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) * @queue_type: the type of the H/W queue this job is submitted to.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) * @ctx_id: the ID of the context the related CS belongs to.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) * @hw_queue_id: the id of the H/W queue this job is submitted to.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) * @user_cb_size: the actual size of the CB we got from the user.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) * @patched_cb_size: the size of the CB after parsing.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) * @job_id: the id of the related job inside the related CS.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) * @is_kernel_allocated_cb: true if the CB handle we got from the user holds a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) * handle to a kernel-allocated CB object, false
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) * otherwise (SRAM/DRAM/host address).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) * @contains_dma_pkt: whether the JOB contains at least one DMA packet. This
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) * info is needed later, when adding the 2xMSG_PROT at the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) * end of the JOB, to know which barriers to put in the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) * MSG_PROT packets. Relevant only for GAUDI as GOYA doesn't
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) * have streams so the engine can't be busy by another
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) * stream.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) struct hl_cs_parser {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) struct hl_cb *user_cb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) struct hl_cb *patched_cb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) struct list_head *job_userptr_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) u64 cs_sequence;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) enum hl_queue_type queue_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) u32 ctx_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) u32 hw_queue_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) u32 user_cb_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) u32 patched_cb_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) u8 job_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) u8 is_kernel_allocated_cb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) u8 contains_dma_pkt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) * MEMORY STRUCTURE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) * struct hl_vm_hash_node - hash element from virtual address to virtual
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) * memory area descriptor (hl_vm_phys_pg_list or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) * hl_userptr).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) * @node: node to hang on the hash table in context object.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) * @vaddr: key virtual address.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) * @ptr: value pointer (hl_vm_phys_pg_list or hl_userptr).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) struct hl_vm_hash_node {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) struct hlist_node node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) u64 vaddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) void *ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) * struct hl_vm_phys_pg_pack - physical page pack.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) * @vm_type: describes the type of the virtual area descriptor.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) * @pages: the physical page array.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) * @npages: num physical pages in the pack.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) * @total_size: total size of all the pages in this list.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) * @mapping_cnt: number of shared mappings.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) * @asid: the context related to this list.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) * @page_size: size of each page in the pack.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) * @flags: HL_MEM_* flags related to this list.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) * @handle: the provided handle related to this list.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) * @offset: offset from the first page.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) * @contiguous: is contiguous physical memory.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) * @created_from_userptr: is product of host virtual address.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) struct hl_vm_phys_pg_pack {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) enum vm_type_t vm_type; /* must be first */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) u64 *pages;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) u64 npages;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) u64 total_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) atomic_t mapping_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) u32 asid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) u32 page_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) u32 flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) u32 handle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) u32 offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) u8 contiguous;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) u8 created_from_userptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) * struct hl_vm_va_block - virtual range block information.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) * @node: node to hang on the virtual range list in context object.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) * @start: virtual range start address.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) * @end: virtual range end address.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) * @size: virtual range size.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) struct hl_vm_va_block {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) struct list_head node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) u64 start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) u64 end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) u64 size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) * struct hl_vm - virtual memory manager for MMU.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) * @dram_pg_pool: pool for DRAM physical pages of 2MB.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) * @dram_pg_pool_refcount: reference counter for the pool usage.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) * @idr_lock: protects the phys_pg_list_handles.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) * @phys_pg_pack_handles: idr to hold all device allocations handles.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) * @init_done: whether initialization was done. We need this because VM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) * initialization might be skipped during device initialization.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) struct hl_vm {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) struct gen_pool *dram_pg_pool;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) struct kref dram_pg_pool_refcount;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) spinlock_t idr_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) struct idr phys_pg_pack_handles;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) u8 init_done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) * DEBUG, PROFILING STRUCTURE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) * struct hl_debug_params - Coresight debug parameters.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) * @input: pointer to component specific input parameters.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) * @output: pointer to component specific output parameters.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) * @output_size: size of output buffer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) * @reg_idx: relevant register ID.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) * @op: component operation to execute.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) * @enable: true if to enable component debugging, false otherwise.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) struct hl_debug_params {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) void *input;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) void *output;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) u32 output_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) u32 reg_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) u32 op;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) bool enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) * FILE PRIVATE STRUCTURE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) * struct hl_fpriv - process information stored in FD private data.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) * @hdev: habanalabs device structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) * @filp: pointer to the given file structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) * @taskpid: current process ID.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) * @ctx: current executing context. TODO: remove for multiple ctx per process
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) * @ctx_mgr: context manager to handle multiple context for this FD.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) * @cb_mgr: command buffer manager to handle multiple buffers for this FD.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) * @debugfs_list: list of relevant ASIC debugfs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) * @dev_node: node in the device list of file private data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) * @refcount: number of related contexts.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) * @restore_phase_mutex: lock for context switch and restore phase.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) * @is_control: true for control device, false otherwise
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) struct hl_fpriv {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) struct hl_device *hdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) struct file *filp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) struct pid *taskpid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) struct hl_ctx *ctx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) struct hl_ctx_mgr ctx_mgr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) struct hl_cb_mgr cb_mgr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) struct list_head debugfs_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) struct list_head dev_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) struct kref refcount;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) struct mutex restore_phase_mutex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) u8 is_control;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) * DebugFS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) * struct hl_info_list - debugfs file ops.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) * @name: file name.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) * @show: function to output information.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) * @write: function to write to the file.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) struct hl_info_list {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) int (*show)(struct seq_file *s, void *data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) ssize_t (*write)(struct file *file, const char __user *buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) size_t count, loff_t *f_pos);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) * struct hl_debugfs_entry - debugfs dentry wrapper.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) * @dent: base debugfs entry structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) * @info_ent: dentry realted ops.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) * @dev_entry: ASIC specific debugfs manager.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) struct hl_debugfs_entry {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) struct dentry *dent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) const struct hl_info_list *info_ent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) struct hl_dbg_device_entry *dev_entry;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) * struct hl_dbg_device_entry - ASIC specific debugfs manager.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) * @root: root dentry.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) * @hdev: habanalabs device structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) * @entry_arr: array of available hl_debugfs_entry.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) * @file_list: list of available debugfs files.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) * @file_mutex: protects file_list.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) * @cb_list: list of available CBs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) * @cb_spinlock: protects cb_list.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) * @cs_list: list of available CSs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) * @cs_spinlock: protects cs_list.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) * @cs_job_list: list of available CB jobs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) * @cs_job_spinlock: protects cs_job_list.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) * @userptr_list: list of available userptrs (virtual memory chunk descriptor).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) * @userptr_spinlock: protects userptr_list.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) * @ctx_mem_hash_list: list of available contexts with MMU mappings.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) * @ctx_mem_hash_spinlock: protects cb_list.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) * @addr: next address to read/write from/to in read/write32.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) * @mmu_addr: next virtual address to translate to physical address in mmu_show.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) * @mmu_asid: ASID to use while translating in mmu_show.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) * @i2c_bus: generic u8 debugfs file for bus value to use in i2c_data_read.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) * @i2c_bus: generic u8 debugfs file for address value to use in i2c_data_read.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) * @i2c_bus: generic u8 debugfs file for register value to use in i2c_data_read.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) struct hl_dbg_device_entry {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) struct dentry *root;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) struct hl_device *hdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) struct hl_debugfs_entry *entry_arr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) struct list_head file_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) struct mutex file_mutex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) struct list_head cb_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) spinlock_t cb_spinlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) struct list_head cs_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) spinlock_t cs_spinlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) struct list_head cs_job_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) spinlock_t cs_job_spinlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) struct list_head userptr_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) spinlock_t userptr_spinlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) struct list_head ctx_mem_hash_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) spinlock_t ctx_mem_hash_spinlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) u64 addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) u64 mmu_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) u32 mmu_asid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) u8 i2c_bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) u8 i2c_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) u8 i2c_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) * DEVICES
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) /* Theoretical limit only. A single host can only contain up to 4 or 8 PCIe
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) * x16 cards. In extreme cases, there are hosts that can accommodate 16 cards.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) #define HL_MAX_MINORS 256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) * Registers read & write functions.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) u32 hl_rreg(struct hl_device *hdev, u32 reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) void hl_wreg(struct hl_device *hdev, u32 reg, u32 val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) #define RREG32(reg) hdev->asic_funcs->rreg(hdev, (reg))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) #define WREG32(reg, v) hdev->asic_funcs->wreg(hdev, (reg), (v))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) #define DREG32(reg) pr_info("REGISTER: " #reg " : 0x%08X\n", \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) hdev->asic_funcs->rreg(hdev, (reg)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) #define WREG32_P(reg, val, mask) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) do { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) u32 tmp_ = RREG32(reg); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) tmp_ &= (mask); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) tmp_ |= ((val) & ~(mask)); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) WREG32(reg, tmp_); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) } while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) #define WREG32_AND(reg, and) WREG32_P(reg, 0, and)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) #define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) #define RMWREG32(reg, val, mask) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) do { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) u32 tmp_ = RREG32(reg); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) tmp_ &= ~(mask); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) tmp_ |= ((val) << __ffs(mask)); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) WREG32(reg, tmp_); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) } while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) #define RREG32_MASK(reg, mask) ((RREG32(reg) & mask) >> __ffs(mask))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) #define REG_FIELD_SHIFT(reg, field) reg##_##field##_SHIFT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) #define REG_FIELD_MASK(reg, field) reg##_##field##_MASK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) #define WREG32_FIELD(reg, offset, field, val) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) WREG32(mm##reg + offset, (RREG32(mm##reg + offset) & \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) ~REG_FIELD_MASK(reg, field)) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) (val) << REG_FIELD_SHIFT(reg, field))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) /* Timeout should be longer when working with simulator but cap the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) * increased timeout to some maximum
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) #define hl_poll_timeout(hdev, addr, val, cond, sleep_us, timeout_us) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) ({ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) ktime_t __timeout; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) if (hdev->pdev) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) __timeout = ktime_add_us(ktime_get(), timeout_us); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) else \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) __timeout = ktime_add_us(ktime_get(),\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) min((u64)(timeout_us * 10), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) (u64) HL_SIM_MAX_TIMEOUT_US)); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) might_sleep_if(sleep_us); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) for (;;) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) (val) = RREG32(addr); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) if (cond) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) break; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) if (timeout_us && ktime_compare(ktime_get(), __timeout) > 0) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) (val) = RREG32(addr); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) break; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) } \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) if (sleep_us) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) usleep_range((sleep_us >> 2) + 1, sleep_us); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) } \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) (cond) ? 0 : -ETIMEDOUT; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) })
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) * address in this macro points always to a memory location in the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) * host's (server's) memory. That location is updated asynchronously
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) * either by the direct access of the device or by another core.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) * To work both in LE and BE architectures, we need to distinguish between the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) * two states (device or another core updates the memory location). Therefore,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) * if mem_written_by_device is true, the host memory being polled will be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) * updated directly by the device. If false, the host memory being polled will
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) * be updated by host CPU. Required so host knows whether or not the memory
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) * might need to be byte-swapped before returning value to caller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) #define hl_poll_timeout_memory(hdev, addr, val, cond, sleep_us, timeout_us, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) mem_written_by_device) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) ({ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) ktime_t __timeout; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) if (hdev->pdev) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) __timeout = ktime_add_us(ktime_get(), timeout_us); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) else \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) __timeout = ktime_add_us(ktime_get(),\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) min((u64)(timeout_us * 10), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) (u64) HL_SIM_MAX_TIMEOUT_US)); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) might_sleep_if(sleep_us); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) for (;;) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) /* Verify we read updates done by other cores or by device */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) mb(); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) (val) = *((u32 *)(addr)); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) if (mem_written_by_device) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) (val) = le32_to_cpu(*(__le32 *) &(val)); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) if (cond) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) break; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) if (timeout_us && ktime_compare(ktime_get(), __timeout) > 0) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) (val) = *((u32 *)(addr)); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) if (mem_written_by_device) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) (val) = le32_to_cpu(*(__le32 *) &(val)); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) break; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) } \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) if (sleep_us) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) usleep_range((sleep_us >> 2) + 1, sleep_us); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) } \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) (cond) ? 0 : -ETIMEDOUT; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) })
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) #define hl_poll_timeout_device_memory(hdev, addr, val, cond, sleep_us, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) timeout_us) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) ({ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) ktime_t __timeout; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) if (hdev->pdev) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) __timeout = ktime_add_us(ktime_get(), timeout_us); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) else \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) __timeout = ktime_add_us(ktime_get(),\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) min((u64)(timeout_us * 10), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) (u64) HL_SIM_MAX_TIMEOUT_US)); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) might_sleep_if(sleep_us); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) for (;;) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) (val) = readl(addr); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) if (cond) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) break; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) if (timeout_us && ktime_compare(ktime_get(), __timeout) > 0) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) (val) = readl(addr); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) break; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) } \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) if (sleep_us) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) usleep_range((sleep_us >> 2) + 1, sleep_us); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) } \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) (cond) ? 0 : -ETIMEDOUT; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) })
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) struct hwmon_chip_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) * struct hl_device_reset_work - reset workqueue task wrapper.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) * @reset_work: reset work to be done.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) * @hdev: habanalabs device structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) struct hl_device_reset_work {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) struct work_struct reset_work;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) struct hl_device *hdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) * struct hl_device_idle_busy_ts - used for calculating device utilization rate.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) * @idle_to_busy_ts: timestamp where device changed from idle to busy.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) * @busy_to_idle_ts: timestamp where device changed from busy to idle.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) struct hl_device_idle_busy_ts {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) ktime_t idle_to_busy_ts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) ktime_t busy_to_idle_ts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) * struct hl_mmu_priv - used for holding per-device mmu internal information.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) * @mmu_pgt_pool: pool of page tables used by MMU for allocating hops.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) * @mmu_shadow_hop0: shadow array of hop0 tables.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) struct hl_mmu_priv {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) struct gen_pool *mmu_pgt_pool;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) void *mmu_shadow_hop0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) * struct hl_mmu_funcs - Device related MMU functions.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) * @init: initialize the MMU module.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) * @fini: release the MMU module.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) * @ctx_init: Initialize a context for using the MMU module.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) * @ctx_fini: disable a ctx from using the mmu module.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) * @map: maps a virtual address to physical address for a context.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) * @unmap: unmap a virtual address of a context.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) * @flush: flush all writes from all cores to reach device MMU.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) * @swap_out: marks all mapping of the given context as swapped out.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) * @swap_in: marks all mapping of the given context as swapped in.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) struct hl_mmu_funcs {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) int (*init)(struct hl_device *hdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) void (*fini)(struct hl_device *hdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) int (*ctx_init)(struct hl_ctx *ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) void (*ctx_fini)(struct hl_ctx *ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) int (*map)(struct hl_ctx *ctx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) u64 virt_addr, u64 phys_addr, u32 page_size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) bool is_dram_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) int (*unmap)(struct hl_ctx *ctx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) u64 virt_addr, bool is_dram_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) void (*flush)(struct hl_ctx *ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) void (*swap_out)(struct hl_ctx *ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) void (*swap_in)(struct hl_ctx *ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) * struct hl_device - habanalabs device structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) * @pdev: pointer to PCI device, can be NULL in case of simulator device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) * @pcie_bar_phys: array of available PCIe bars physical addresses.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) * (required only for PCI address match mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) * @pcie_bar: array of available PCIe bars virtual addresses.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) * @rmmio: configuration area address on SRAM.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) * @cdev: related char device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) * @cdev_ctrl: char device for control operations only (INFO IOCTL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) * @dev: related kernel basic device structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) * @dev_ctrl: related kernel device structure for the control device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) * @work_freq: delayed work to lower device frequency if possible.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) * @work_heartbeat: delayed work for CPU-CP is-alive check.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) * @asic_name: ASIC specific name.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) * @asic_type: ASIC specific type.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) * @completion_queue: array of hl_cq.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) * @cq_wq: work queues of completion queues for executing work in process
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) * context.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) * @eq_wq: work queue of event queue for executing work in process context.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) * @kernel_ctx: Kernel driver context structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) * @kernel_queues: array of hl_hw_queue.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) * @hw_queues_mirror_list: CS mirror list for TDR.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) * @hw_queues_mirror_lock: protects hw_queues_mirror_list.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) * @kernel_cb_mgr: command buffer manager for creating/destroying/handling CGs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) * @event_queue: event queue for IRQ from CPU-CP.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) * @dma_pool: DMA pool for small allocations.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) * @cpu_accessible_dma_mem: Host <-> CPU-CP shared memory CPU address.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) * @cpu_accessible_dma_address: Host <-> CPU-CP shared memory DMA address.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) * @cpu_accessible_dma_pool: Host <-> CPU-CP shared memory pool.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) * @asid_bitmap: holds used/available ASIDs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) * @asid_mutex: protects asid_bitmap.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) * @send_cpu_message_lock: enforces only one message in Host <-> CPU-CP queue.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) * @debug_lock: protects critical section of setting debug mode for device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) * @asic_prop: ASIC specific immutable properties.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) * @asic_funcs: ASIC specific functions.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) * @asic_specific: ASIC specific information to use only from ASIC files.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) * @vm: virtual memory manager for MMU.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) * @mmu_cache_lock: protects MMU cache invalidation as it can serve one context.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) * @hwmon_dev: H/W monitor device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) * @pm_mng_profile: current power management profile.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) * @hl_chip_info: ASIC's sensors information.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) * @hl_debugfs: device's debugfs manager.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) * @cb_pool: list of preallocated CBs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) * @cb_pool_lock: protects the CB pool.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) * @internal_cb_pool_virt_addr: internal command buffer pool virtual address.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) * @internal_cb_pool_dma_addr: internal command buffer pool dma address.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533) * @internal_cb_pool: internal command buffer memory pool.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) * @internal_cb_va_base: internal cb pool mmu virtual address base
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) * @fpriv_list: list of file private data structures. Each structure is created
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) * when a user opens the device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) * @fpriv_list_lock: protects the fpriv_list
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) * @compute_ctx: current compute context executing.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) * @idle_busy_ts_arr: array to hold time stamps of transitions from idle to busy
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) * and vice-versa
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) * @aggregated_cs_counters: aggregated cs counters among all contexts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) * @mmu_priv: device-specific MMU data.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) * @mmu_func: device-related MMU functions.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) * @dram_used_mem: current DRAM memory consumption.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) * @timeout_jiffies: device CS timeout value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) * @max_power: the max power of the device, as configured by the sysadmin. This
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) * value is saved so in case of hard-reset, the driver will restore
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) * this value and update the F/W after the re-initialization
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549) * @clock_gating_mask: is clock gating enabled. bitmask that represents the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) * different engines. See debugfs-driver-habanalabs for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) * details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) * @in_reset: is device in reset flow.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) * @curr_pll_profile: current PLL profile.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) * @card_type: Various ASICs have several card types. This indicates the card
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) * type of the current device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) * @cs_active_cnt: number of active command submissions on this device (active
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557) * means already in H/W queues)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) * @major: habanalabs kernel driver major.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) * @high_pll: high PLL profile frequency.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) * @soft_reset_cnt: number of soft reset since the driver was loaded.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) * @hard_reset_cnt: number of hard reset since the driver was loaded.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) * @idle_busy_ts_idx: index of current entry in idle_busy_ts_arr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) * @clk_throttling_reason: bitmask represents the current clk throttling reasons
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) * @id: device minor.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) * @id_control: minor of the control device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) * @cpu_pci_msb_addr: 50-bit extension bits for the device CPU's 40-bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) * addresses.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) * @disabled: is device disabled.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569) * @late_init_done: is late init stage was done during initialization.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) * @hwmon_initialized: is H/W monitor sensors was initialized.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) * @hard_reset_pending: is there a hard reset work pending.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) * @heartbeat: is heartbeat sanity check towards CPU-CP enabled.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573) * @reset_on_lockup: true if a reset should be done in case of stuck CS, false
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574) * otherwise.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) * @dram_supports_virtual_memory: is MMU enabled towards DRAM.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) * @dram_default_page_mapping: is DRAM default page mapping enabled.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) * @pmmu_huge_range: is a different virtual addresses range used for PMMU with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) * huge pages.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) * @init_done: is the initialization of the device done.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580) * @mmu_enable: is MMU enabled.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581) * @mmu_huge_page_opt: is MMU huge pages optimization enabled.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582) * @device_cpu_disabled: is the device CPU disabled (due to timeouts)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) * @dma_mask: the dma mask that was set for this device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584) * @in_debug: is device under debug. This, together with fpriv_list, enforces
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585) * that only a single user is configuring the debug infrastructure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) * @power9_64bit_dma_enable: true to enable 64-bit DMA mask support. Relevant
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) * only to POWER9 machines.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) * @cdev_sysfs_created: were char devices and sysfs nodes created.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589) * @stop_on_err: true if engines should stop on error.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590) * @supports_sync_stream: is sync stream supported.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591) * @sync_stream_queue_idx: helper index for sync stream queues initialization.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) * @supports_coresight: is CoreSight supported.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593) * @supports_soft_reset: is soft reset supported.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594) * @supports_cb_mapping: is mapping a CB to the device's MMU supported.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596) struct hl_device {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597) struct pci_dev *pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598) u64 pcie_bar_phys[HL_PCI_NUM_BARS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599) void __iomem *pcie_bar[HL_PCI_NUM_BARS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) void __iomem *rmmio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601) struct cdev cdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602) struct cdev cdev_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604) struct device *dev_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605) struct delayed_work work_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606) struct delayed_work work_heartbeat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607) char asic_name[32];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608) enum hl_asic_type asic_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609) struct hl_cq *completion_queue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610) struct workqueue_struct **cq_wq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) struct workqueue_struct *eq_wq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612) struct hl_ctx *kernel_ctx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613) struct hl_hw_queue *kernel_queues;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614) struct list_head hw_queues_mirror_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615) spinlock_t hw_queues_mirror_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616) struct hl_cb_mgr kernel_cb_mgr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617) struct hl_eq event_queue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618) struct dma_pool *dma_pool;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619) void *cpu_accessible_dma_mem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620) dma_addr_t cpu_accessible_dma_address;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621) struct gen_pool *cpu_accessible_dma_pool;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622) unsigned long *asid_bitmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623) struct mutex asid_mutex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) struct mutex send_cpu_message_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625) struct mutex debug_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626) struct asic_fixed_properties asic_prop;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627) const struct hl_asic_funcs *asic_funcs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628) void *asic_specific;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629) struct hl_vm vm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630) struct mutex mmu_cache_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631) struct device *hwmon_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632) enum hl_pm_mng_profile pm_mng_profile;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633) struct hwmon_chip_info *hl_chip_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635) struct hl_dbg_device_entry hl_debugfs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637) struct list_head cb_pool;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638) spinlock_t cb_pool_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640) void *internal_cb_pool_virt_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641) dma_addr_t internal_cb_pool_dma_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642) struct gen_pool *internal_cb_pool;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643) u64 internal_cb_va_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645) struct list_head fpriv_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646) struct mutex fpriv_list_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648) struct hl_ctx *compute_ctx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650) struct hl_device_idle_busy_ts *idle_busy_ts_arr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652) struct hl_cs_counters aggregated_cs_counters;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654) struct hl_mmu_priv mmu_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655) struct hl_mmu_funcs mmu_func;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657) atomic64_t dram_used_mem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658) u64 timeout_jiffies;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659) u64 max_power;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660) u64 clock_gating_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661) atomic_t in_reset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662) enum hl_pll_frequency curr_pll_profile;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663) enum cpucp_card_types card_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664) int cs_active_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665) u32 major;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666) u32 high_pll;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667) u32 soft_reset_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668) u32 hard_reset_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669) u32 idle_busy_ts_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670) u32 clk_throttling_reason;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671) u16 id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672) u16 id_control;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673) u16 cpu_pci_msb_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674) u8 disabled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675) u8 late_init_done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676) u8 hwmon_initialized;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677) u8 hard_reset_pending;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678) u8 heartbeat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679) u8 reset_on_lockup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680) u8 dram_supports_virtual_memory;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681) u8 dram_default_page_mapping;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682) u8 pmmu_huge_range;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683) u8 init_done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684) u8 device_cpu_disabled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685) u8 dma_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686) u8 in_debug;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687) u8 power9_64bit_dma_enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688) u8 cdev_sysfs_created;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689) u8 stop_on_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690) u8 supports_sync_stream;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691) u8 sync_stream_queue_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692) u8 supports_coresight;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693) u8 supports_soft_reset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694) u8 supports_cb_mapping;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696) /* Parameters for bring-up */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697) u8 mmu_enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698) u8 mmu_huge_page_opt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699) u8 cpu_enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700) u8 reset_pcilink;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701) u8 cpu_queues_enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702) u8 fw_loading;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703) u8 pldm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704) u8 axi_drain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705) u8 sram_scrambler_enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706) u8 dram_scrambler_enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1707) u8 hard_reset_on_fw_events;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1708) u8 bmc_enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1709) u8 rl_enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1710) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1711)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1712)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1713) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1714) * IOCTLs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1715) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1716)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1717) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1718) * typedef hl_ioctl_t - typedef for ioctl function in the driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1719) * @hpriv: pointer to the FD's private data, which contains state of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1720) * user process
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1721) * @data: pointer to the input/output arguments structure of the IOCTL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1722) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1723) * Return: 0 for success, negative value for error
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1724) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1725) typedef int hl_ioctl_t(struct hl_fpriv *hpriv, void *data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1726)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1727) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1728) * struct hl_ioctl_desc - describes an IOCTL entry of the driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1729) * @cmd: the IOCTL code as created by the kernel macros.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1730) * @func: pointer to the driver's function that should be called for this IOCTL.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1731) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1732) struct hl_ioctl_desc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1733) unsigned int cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1734) hl_ioctl_t *func;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1735) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1736)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1737)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1738) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1739) * Kernel module functions that can be accessed by entire module
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1740) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1741)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1742) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1743) * hl_mem_area_inside_range() - Checks whether address+size are inside a range.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1744) * @address: The start address of the area we want to validate.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1745) * @size: The size in bytes of the area we want to validate.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1746) * @range_start_address: The start address of the valid range.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1747) * @range_end_address: The end address of the valid range.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1748) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1749) * Return: true if the area is inside the valid range, false otherwise.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1750) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1751) static inline bool hl_mem_area_inside_range(u64 address, u64 size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1752) u64 range_start_address, u64 range_end_address)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1753) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1754) u64 end_address = address + size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1755)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1756) if ((address >= range_start_address) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1757) (end_address <= range_end_address) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1758) (end_address > address))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1759) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1760)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1761) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1762) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1763)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1764) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1765) * hl_mem_area_crosses_range() - Checks whether address+size crossing a range.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1766) * @address: The start address of the area we want to validate.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1767) * @size: The size in bytes of the area we want to validate.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1768) * @range_start_address: The start address of the valid range.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1769) * @range_end_address: The end address of the valid range.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1770) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1771) * Return: true if the area overlaps part or all of the valid range,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1772) * false otherwise.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1773) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1774) static inline bool hl_mem_area_crosses_range(u64 address, u32 size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1775) u64 range_start_address, u64 range_end_address)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1776) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1777) u64 end_address = address + size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1778)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1779) if ((address >= range_start_address) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1780) (address < range_end_address))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1781) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1782)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1783) if ((end_address >= range_start_address) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1784) (end_address < range_end_address))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1785) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1786)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1787) if ((address < range_start_address) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1788) (end_address >= range_end_address))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1789) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1790)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1791) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1792) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1793)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1794) int hl_device_open(struct inode *inode, struct file *filp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1795) int hl_device_open_ctrl(struct inode *inode, struct file *filp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1796) bool hl_device_disabled_or_in_reset(struct hl_device *hdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1797) enum hl_device_status hl_device_status(struct hl_device *hdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1798) int hl_device_set_debug_mode(struct hl_device *hdev, bool enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1799) int create_hdev(struct hl_device **dev, struct pci_dev *pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1800) enum hl_asic_type asic_type, int minor);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1801) void destroy_hdev(struct hl_device *hdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1802) int hl_hw_queues_create(struct hl_device *hdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1803) void hl_hw_queues_destroy(struct hl_device *hdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1804) int hl_hw_queue_send_cb_no_cmpl(struct hl_device *hdev, u32 hw_queue_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1805) u32 cb_size, u64 cb_ptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1806) int hl_hw_queue_schedule_cs(struct hl_cs *cs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1807) u32 hl_hw_queue_add_ptr(u32 ptr, u16 val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1808) void hl_hw_queue_inc_ci_kernel(struct hl_device *hdev, u32 hw_queue_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1809) void hl_int_hw_queue_update_ci(struct hl_cs *cs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1810) void hl_hw_queue_reset(struct hl_device *hdev, bool hard_reset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1811)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1812) #define hl_queue_inc_ptr(p) hl_hw_queue_add_ptr(p, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1813) #define hl_pi_2_offset(pi) ((pi) & (HL_QUEUE_LENGTH - 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1814)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1815) int hl_cq_init(struct hl_device *hdev, struct hl_cq *q, u32 hw_queue_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1816) void hl_cq_fini(struct hl_device *hdev, struct hl_cq *q);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1817) int hl_eq_init(struct hl_device *hdev, struct hl_eq *q);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1818) void hl_eq_fini(struct hl_device *hdev, struct hl_eq *q);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1819) void hl_cq_reset(struct hl_device *hdev, struct hl_cq *q);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1820) void hl_eq_reset(struct hl_device *hdev, struct hl_eq *q);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1821) irqreturn_t hl_irq_handler_cq(int irq, void *arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1822) irqreturn_t hl_irq_handler_eq(int irq, void *arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1823) u32 hl_cq_inc_ptr(u32 ptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1824)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1825) int hl_asid_init(struct hl_device *hdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1826) void hl_asid_fini(struct hl_device *hdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1827) unsigned long hl_asid_alloc(struct hl_device *hdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1828) void hl_asid_free(struct hl_device *hdev, unsigned long asid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1829)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1830) int hl_ctx_create(struct hl_device *hdev, struct hl_fpriv *hpriv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1831) void hl_ctx_free(struct hl_device *hdev, struct hl_ctx *ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1832) int hl_ctx_init(struct hl_device *hdev, struct hl_ctx *ctx, bool is_kernel_ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1833) void hl_ctx_do_release(struct kref *ref);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1834) void hl_ctx_get(struct hl_device *hdev, struct hl_ctx *ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1835) int hl_ctx_put(struct hl_ctx *ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1836) struct hl_fence *hl_ctx_get_fence(struct hl_ctx *ctx, u64 seq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1837) void hl_ctx_mgr_init(struct hl_ctx_mgr *mgr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1838) void hl_ctx_mgr_fini(struct hl_device *hdev, struct hl_ctx_mgr *mgr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1839)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1840) int hl_device_init(struct hl_device *hdev, struct class *hclass);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1841) void hl_device_fini(struct hl_device *hdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1842) int hl_device_suspend(struct hl_device *hdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1843) int hl_device_resume(struct hl_device *hdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1844) int hl_device_reset(struct hl_device *hdev, bool hard_reset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1845) bool from_hard_reset_thread);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1846) void hl_hpriv_get(struct hl_fpriv *hpriv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1847) void hl_hpriv_put(struct hl_fpriv *hpriv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1848) int hl_device_set_frequency(struct hl_device *hdev, enum hl_pll_frequency freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1849) uint32_t hl_device_utilization(struct hl_device *hdev, uint32_t period_ms);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1850)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1851) int hl_build_hwmon_channel_info(struct hl_device *hdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1852) struct cpucp_sensor *sensors_arr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1853)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1854) int hl_sysfs_init(struct hl_device *hdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1855) void hl_sysfs_fini(struct hl_device *hdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1856)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1857) int hl_hwmon_init(struct hl_device *hdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1858) void hl_hwmon_fini(struct hl_device *hdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1859)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1860) int hl_cb_create(struct hl_device *hdev, struct hl_cb_mgr *mgr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1861) struct hl_ctx *ctx, u32 cb_size, bool internal_cb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1862) bool map_cb, u64 *handle);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1863) int hl_cb_destroy(struct hl_device *hdev, struct hl_cb_mgr *mgr, u64 cb_handle);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1864) int hl_cb_mmap(struct hl_fpriv *hpriv, struct vm_area_struct *vma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1865) struct hl_cb *hl_cb_get(struct hl_device *hdev, struct hl_cb_mgr *mgr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1866) u32 handle);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1867) void hl_cb_put(struct hl_cb *cb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1868) void hl_cb_mgr_init(struct hl_cb_mgr *mgr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1869) void hl_cb_mgr_fini(struct hl_device *hdev, struct hl_cb_mgr *mgr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1870) struct hl_cb *hl_cb_kernel_create(struct hl_device *hdev, u32 cb_size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1871) bool internal_cb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1872) int hl_cb_pool_init(struct hl_device *hdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1873) int hl_cb_pool_fini(struct hl_device *hdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1874) int hl_cb_va_pool_init(struct hl_ctx *ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1875) void hl_cb_va_pool_fini(struct hl_ctx *ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1876)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1877) void hl_cs_rollback_all(struct hl_device *hdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1878) struct hl_cs_job *hl_cs_allocate_job(struct hl_device *hdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1879) enum hl_queue_type queue_type, bool is_kernel_allocated_cb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1880) void hl_sob_reset_error(struct kref *ref);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1881) void hl_fence_put(struct hl_fence *fence);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1882) void hl_fence_get(struct hl_fence *fence);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1883)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1884) void goya_set_asic_funcs(struct hl_device *hdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1885) void gaudi_set_asic_funcs(struct hl_device *hdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1886)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1887) int hl_vm_ctx_init(struct hl_ctx *ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1888) void hl_vm_ctx_fini(struct hl_ctx *ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1889)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1890) int hl_vm_init(struct hl_device *hdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1891) void hl_vm_fini(struct hl_device *hdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1892)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1893) int hl_pin_host_memory(struct hl_device *hdev, u64 addr, u64 size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1894) struct hl_userptr *userptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1895) void hl_unpin_host_memory(struct hl_device *hdev, struct hl_userptr *userptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1896) void hl_userptr_delete_list(struct hl_device *hdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1897) struct list_head *userptr_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1898) bool hl_userptr_is_pinned(struct hl_device *hdev, u64 addr, u32 size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1899) struct list_head *userptr_list,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1900) struct hl_userptr **userptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1901)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1902) int hl_mmu_init(struct hl_device *hdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1903) void hl_mmu_fini(struct hl_device *hdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1904) int hl_mmu_ctx_init(struct hl_ctx *ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1905) void hl_mmu_ctx_fini(struct hl_ctx *ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1906) int hl_mmu_map(struct hl_ctx *ctx, u64 virt_addr, u64 phys_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1907) u32 page_size, bool flush_pte);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1908) int hl_mmu_unmap(struct hl_ctx *ctx, u64 virt_addr, u32 page_size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1909) bool flush_pte);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1910) void hl_mmu_swap_out(struct hl_ctx *ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1911) void hl_mmu_swap_in(struct hl_ctx *ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1912) int hl_mmu_if_set_funcs(struct hl_device *hdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1913) void hl_mmu_v1_set_funcs(struct hl_device *hdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1914)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1915) int hl_fw_load_fw_to_device(struct hl_device *hdev, const char *fw_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1916) void __iomem *dst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1917) int hl_fw_send_pci_access_msg(struct hl_device *hdev, u32 opcode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1918) int hl_fw_send_cpu_message(struct hl_device *hdev, u32 hw_queue_id, u32 *msg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1919) u16 len, u32 timeout, long *result);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1920) int hl_fw_unmask_irq(struct hl_device *hdev, u16 event_type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1921) int hl_fw_unmask_irq_arr(struct hl_device *hdev, const u32 *irq_arr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1922) size_t irq_arr_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1923) int hl_fw_test_cpu_queue(struct hl_device *hdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1924) void *hl_fw_cpu_accessible_dma_pool_alloc(struct hl_device *hdev, size_t size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1925) dma_addr_t *dma_handle);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1926) void hl_fw_cpu_accessible_dma_pool_free(struct hl_device *hdev, size_t size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1927) void *vaddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1928) int hl_fw_send_heartbeat(struct hl_device *hdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1929) int hl_fw_cpucp_info_get(struct hl_device *hdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1930) int hl_fw_get_eeprom_data(struct hl_device *hdev, void *data, size_t max_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1931) int hl_fw_cpucp_pci_counters_get(struct hl_device *hdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1932) struct hl_info_pci_counters *counters);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1933) int hl_fw_cpucp_total_energy_get(struct hl_device *hdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1934) u64 *total_energy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1935) int hl_fw_init_cpu(struct hl_device *hdev, u32 cpu_boot_status_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1936) u32 msg_to_cpu_reg, u32 cpu_msg_status_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1937) u32 boot_err0_reg, bool skip_bmc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1938) u32 cpu_timeout, u32 boot_fit_timeout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1939) int hl_fw_read_preboot_ver(struct hl_device *hdev, u32 cpu_boot_status_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1940) u32 boot_err0_reg, u32 timeout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1941)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1942) int hl_pci_bars_map(struct hl_device *hdev, const char * const name[3],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1943) bool is_wc[3]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1944) int hl_pci_iatu_write(struct hl_device *hdev, u32 addr, u32 data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1945) int hl_pci_set_inbound_region(struct hl_device *hdev, u8 region,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1946) struct hl_inbound_pci_region *pci_region);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1947) int hl_pci_set_outbound_region(struct hl_device *hdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1948) struct hl_outbound_pci_region *pci_region);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1949) int hl_pci_init(struct hl_device *hdev, u32 cpu_boot_status_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1950) u32 boot_err0_reg, u32 preboot_ver_timeout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1951) void hl_pci_fini(struct hl_device *hdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1952)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1953) long hl_get_frequency(struct hl_device *hdev, u32 pll_index, bool curr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1954) void hl_set_frequency(struct hl_device *hdev, u32 pll_index, u64 freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1955) int hl_get_temperature(struct hl_device *hdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1956) int sensor_index, u32 attr, long *value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1957) int hl_set_temperature(struct hl_device *hdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1958) int sensor_index, u32 attr, long value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1959) int hl_get_voltage(struct hl_device *hdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1960) int sensor_index, u32 attr, long *value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1961) int hl_get_current(struct hl_device *hdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1962) int sensor_index, u32 attr, long *value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1963) int hl_get_fan_speed(struct hl_device *hdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1964) int sensor_index, u32 attr, long *value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1965) int hl_get_pwm_info(struct hl_device *hdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1966) int sensor_index, u32 attr, long *value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1967) void hl_set_pwm_info(struct hl_device *hdev, int sensor_index, u32 attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1968) long value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1969) u64 hl_get_max_power(struct hl_device *hdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1970) void hl_set_max_power(struct hl_device *hdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1971) int hl_set_voltage(struct hl_device *hdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1972) int sensor_index, u32 attr, long value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1973) int hl_set_current(struct hl_device *hdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1974) int sensor_index, u32 attr, long value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1975)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1976) #ifdef CONFIG_DEBUG_FS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1977)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1978) void hl_debugfs_init(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1979) void hl_debugfs_fini(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1980) void hl_debugfs_add_device(struct hl_device *hdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1981) void hl_debugfs_remove_device(struct hl_device *hdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1982) void hl_debugfs_add_file(struct hl_fpriv *hpriv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1983) void hl_debugfs_remove_file(struct hl_fpriv *hpriv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1984) void hl_debugfs_add_cb(struct hl_cb *cb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1985) void hl_debugfs_remove_cb(struct hl_cb *cb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1986) void hl_debugfs_add_cs(struct hl_cs *cs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1987) void hl_debugfs_remove_cs(struct hl_cs *cs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1988) void hl_debugfs_add_job(struct hl_device *hdev, struct hl_cs_job *job);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1989) void hl_debugfs_remove_job(struct hl_device *hdev, struct hl_cs_job *job);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1990) void hl_debugfs_add_userptr(struct hl_device *hdev, struct hl_userptr *userptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1991) void hl_debugfs_remove_userptr(struct hl_device *hdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1992) struct hl_userptr *userptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1993) void hl_debugfs_add_ctx_mem_hash(struct hl_device *hdev, struct hl_ctx *ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1994) void hl_debugfs_remove_ctx_mem_hash(struct hl_device *hdev, struct hl_ctx *ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1995)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1996) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1997)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1998) static inline void __init hl_debugfs_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1999) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2000) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2002) static inline void hl_debugfs_fini(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2003) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2004) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2005)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2006) static inline void hl_debugfs_add_device(struct hl_device *hdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2007) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2008) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2009)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2010) static inline void hl_debugfs_remove_device(struct hl_device *hdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2011) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2012) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2013)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2014) static inline void hl_debugfs_add_file(struct hl_fpriv *hpriv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2015) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2016) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2017)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2018) static inline void hl_debugfs_remove_file(struct hl_fpriv *hpriv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2019) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2020) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2021)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2022) static inline void hl_debugfs_add_cb(struct hl_cb *cb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2023) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2024) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2025)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2026) static inline void hl_debugfs_remove_cb(struct hl_cb *cb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2027) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2028) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2029)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2030) static inline void hl_debugfs_add_cs(struct hl_cs *cs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2031) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2032) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2033)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2034) static inline void hl_debugfs_remove_cs(struct hl_cs *cs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2035) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2036) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2037)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2038) static inline void hl_debugfs_add_job(struct hl_device *hdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2039) struct hl_cs_job *job)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2040) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2041) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2042)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2043) static inline void hl_debugfs_remove_job(struct hl_device *hdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2044) struct hl_cs_job *job)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2045) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2046) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2047)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2048) static inline void hl_debugfs_add_userptr(struct hl_device *hdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2049) struct hl_userptr *userptr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2050) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2051) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2052)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2053) static inline void hl_debugfs_remove_userptr(struct hl_device *hdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2054) struct hl_userptr *userptr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2055) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2056) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2057)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2058) static inline void hl_debugfs_add_ctx_mem_hash(struct hl_device *hdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2059) struct hl_ctx *ctx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2060) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2061) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2062)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2063) static inline void hl_debugfs_remove_ctx_mem_hash(struct hl_device *hdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2064) struct hl_ctx *ctx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2065) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2066) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2067)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2068) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2069)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2070) /* IOCTLs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2071) long hl_ioctl(struct file *filep, unsigned int cmd, unsigned long arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2072) long hl_ioctl_control(struct file *filep, unsigned int cmd, unsigned long arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2073) int hl_cb_ioctl(struct hl_fpriv *hpriv, void *data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2074) int hl_cs_ioctl(struct hl_fpriv *hpriv, void *data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2075) int hl_cs_wait_ioctl(struct hl_fpriv *hpriv, void *data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2076) int hl_mem_ioctl(struct hl_fpriv *hpriv, void *data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2077)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2078) #endif /* HABANALABSP_H_ */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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