^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-or-later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) #ifndef __CARD_DDCB_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) #define __CARD_DDCB_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * IBM Accelerator Family 'GenWQE'
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * (C) Copyright IBM Corp. 2013
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * Author: Frank Haverkamp <haver@linux.vnet.ibm.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * Author: Joerg-Stephan Vogt <jsvogt@de.ibm.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * Author: Michael Jung <mijung@gmx.net>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * Author: Michael Ruettger <michael@ibmra.de>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <asm/byteorder.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include "genwqe_driver.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include "card_base.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) * struct ddcb - Device Driver Control Block DDCB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) * @hsi: Hardware software interlock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * @shi: Software hardware interlock. Hsi and shi are used to interlock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) * software and hardware activities. We are using a compare and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) * swap operation to ensure that there are no races when
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) * activating new DDCBs on the queue, or when we need to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) * purge a DDCB from a running queue.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) * @acfunc: Accelerator function addresses a unit within the chip
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) * @cmd: Command to work on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) * @cmdopts_16: Options for the command
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) * @asiv: Input data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) * @asv: Output data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) * The DDCB data format is big endian. Multiple consequtive DDBCs form
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) * a DDCB queue.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define ASIV_LENGTH 104 /* Old specification without ATS field */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define ASIV_LENGTH_ATS 96 /* New specification with ATS field */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define ASV_LENGTH 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) struct ddcb {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) __be32 icrc_hsi_shi_32; /* iCRC, Hardware/SW interlock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) __be16 icrc_16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) u8 hsi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) u8 shi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) u8 pre; /* Preamble */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) u8 xdir; /* Execution Directives */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) __be16 seqnum_16; /* Sequence Number */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) u8 acfunc; /* Accelerator Function.. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) u8 cmd; /* Command. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) __be16 cmdopts_16; /* Command Options */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) u8 sur; /* Status Update Rate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) u8 psp; /* Protection Section Pointer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) __be16 rsvd_0e_16; /* Reserved invariant */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) __be64 fwiv_64; /* Firmware Invariant. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) __be64 ats_64; /* Address Translation Spec */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) u8 asiv[ASIV_LENGTH_ATS]; /* New ASIV */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) } n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) u8 __asiv[ASIV_LENGTH]; /* obsolete */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) u8 asv[ASV_LENGTH]; /* Appl Spec Variant */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) __be16 rsvd_c0_16; /* Reserved Variant */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) __be16 vcrc_16; /* Variant CRC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) __be32 rsvd_32; /* Reserved unprotected */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) __be64 deque_ts_64; /* Deque Time Stamp. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) __be16 retc_16; /* Return Code */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) __be16 attn_16; /* Attention/Extended Error Codes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) __be32 progress_32; /* Progress indicator. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) __be64 cmplt_ts_64; /* Completion Time Stamp. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) /* The following layout matches the new service layer format */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) __be32 ibdc_32; /* Inbound Data Count (* 256) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) __be32 obdc_32; /* Outbound Data Count (* 256) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) __be64 rsvd_SLH_64; /* Reserved for hardware */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) union { /* private data for driver */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) u8 priv[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) __be64 priv_64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) __be64 disp_ts_64; /* Dispatch TimeStamp */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) } __attribute__((__packed__));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) /* CRC polynomials for DDCB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define CRC16_POLYNOMIAL 0x1021
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) * SHI: Software to Hardware Interlock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) * This 1 byte field is written by software to interlock the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) * movement of one queue entry to another with the hardware in the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) * chip.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define DDCB_SHI_INTR 0x04 /* Bit 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define DDCB_SHI_PURGE 0x02 /* Bit 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define DDCB_SHI_NEXT 0x01 /* Bit 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) * HSI: Hardware to Software interlock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) * This 1 byte field is written by hardware to interlock the movement
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) * of one queue entry to another with the software in the chip.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define DDCB_HSI_COMPLETED 0x40 /* Bit 6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define DDCB_HSI_FETCHED 0x04 /* Bit 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) * Accessing HSI/SHI is done 32-bit wide
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) * Normally 16-bit access would work too, but on some platforms the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) * 16 compare and swap operation is not supported. Therefore
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) * switching to 32-bit such that those platforms will work too.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) * iCRC HSI/SHI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define DDCB_INTR_BE32 cpu_to_be32(0x00000004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define DDCB_PURGE_BE32 cpu_to_be32(0x00000002)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define DDCB_NEXT_BE32 cpu_to_be32(0x00000001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define DDCB_COMPLETED_BE32 cpu_to_be32(0x00004000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define DDCB_FETCHED_BE32 cpu_to_be32(0x00000400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) /* Definitions of DDCB presets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define DDCB_PRESET_PRE 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define ICRC_LENGTH(n) ((n) + 8 + 8 + 8) /* used ASIV + hdr fields */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define VCRC_LENGTH(n) ((n)) /* used ASV */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) * Genwqe Scatter Gather list
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) * Each element has up to 8 entries.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) * The chaining element is element 0 cause of prefetching needs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) * 0b0110 Chained descriptor. The descriptor is describing the next
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) * descriptor list.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define SG_CHAINED (0x6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) * 0b0010 First entry of a descriptor list. Start from a Buffer-Empty
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) * condition.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define SG_DATA (0x2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) * 0b0000 Early terminator. This is the last entry on the list
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) * irregardless of the length indicated.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define SG_END_LIST (0x0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) * struct sglist - Scatter gather list
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) * @target_addr: Either a dma addr of memory to work on or a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) * dma addr or a subsequent sglist block.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) * @len: Length of the data block.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) * @flags: See above.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) * Depending on the command the GenWQE card can use a scatter gather
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) * list to describe the memory it works on. Always 8 sg_entry's form
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) * a block.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) struct sg_entry {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) __be64 target_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) __be32 len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) __be32 flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #endif /* __CARD_DDCB_H__ */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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