^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * IBM Accelerator Family 'GenWQE'
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * (C) Copyright IBM Corp. 2013
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Author: Frank Haverkamp <haver@linux.vnet.ibm.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Author: Joerg-Stephan Vogt <jsvogt@de.ibm.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Author: Michael Jung <mijung@gmx.net>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * Author: Michael Ruettger <michael@ibmra.de>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * Module initialization and PCIe setup. Card health monitoring and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * recovery functionality. Character device creation and deletion are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * controlled from here.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/aer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/string.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/sched.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/wait.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <linux/dma-mapping.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <linux/notifier.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include <linux/log2.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #include "card_base.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #include "card_ddcb.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) MODULE_AUTHOR("Frank Haverkamp <haver@linux.vnet.ibm.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) MODULE_AUTHOR("Michael Ruettger <michael@ibmra.de>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) MODULE_AUTHOR("Joerg-Stephan Vogt <jsvogt@de.ibm.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) MODULE_AUTHOR("Michael Jung <mijung@gmx.net>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) MODULE_DESCRIPTION("GenWQE Card");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) MODULE_VERSION(DRV_VERSION);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) static char genwqe_driver_name[] = GENWQE_DEVNAME;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) static struct class *class_genwqe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) static struct dentry *debugfs_genwqe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) static struct genwqe_dev *genwqe_devices[GENWQE_CARD_NO_MAX];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) /* PCI structure for identifying device by PCI vendor and device ID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) static const struct pci_device_id genwqe_device_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) { .vendor = PCI_VENDOR_ID_IBM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) .device = PCI_DEVICE_GENWQE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) .subvendor = PCI_SUBVENDOR_ID_IBM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) .subdevice = PCI_SUBSYSTEM_ID_GENWQE5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) .class = (PCI_CLASSCODE_GENWQE5 << 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) .class_mask = ~0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) .driver_data = 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) /* Initial SR-IOV bring-up image */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) { .vendor = PCI_VENDOR_ID_IBM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) .device = PCI_DEVICE_GENWQE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) .subvendor = PCI_SUBVENDOR_ID_IBM_SRIOV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) .subdevice = PCI_SUBSYSTEM_ID_GENWQE5_SRIOV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) .class = (PCI_CLASSCODE_GENWQE5_SRIOV << 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) .class_mask = ~0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) .driver_data = 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) { .vendor = PCI_VENDOR_ID_IBM, /* VF Vendor ID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) .device = 0x0000, /* VF Device ID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) .subvendor = PCI_SUBVENDOR_ID_IBM_SRIOV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) .subdevice = PCI_SUBSYSTEM_ID_GENWQE5_SRIOV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) .class = (PCI_CLASSCODE_GENWQE5_SRIOV << 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) .class_mask = ~0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) .driver_data = 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) /* Fixed up image */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) { .vendor = PCI_VENDOR_ID_IBM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) .device = PCI_DEVICE_GENWQE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) .subvendor = PCI_SUBVENDOR_ID_IBM_SRIOV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) .subdevice = PCI_SUBSYSTEM_ID_GENWQE5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) .class = (PCI_CLASSCODE_GENWQE5_SRIOV << 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) .class_mask = ~0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) .driver_data = 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) { .vendor = PCI_VENDOR_ID_IBM, /* VF Vendor ID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) .device = 0x0000, /* VF Device ID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) .subvendor = PCI_SUBVENDOR_ID_IBM_SRIOV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) .subdevice = PCI_SUBSYSTEM_ID_GENWQE5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) .class = (PCI_CLASSCODE_GENWQE5_SRIOV << 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) .class_mask = ~0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) .driver_data = 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) /* Even one more ... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) { .vendor = PCI_VENDOR_ID_IBM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) .device = PCI_DEVICE_GENWQE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) .subvendor = PCI_SUBVENDOR_ID_IBM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) .subdevice = PCI_SUBSYSTEM_ID_GENWQE5_NEW,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) .class = (PCI_CLASSCODE_GENWQE5 << 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) .class_mask = ~0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) .driver_data = 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) { 0, } /* 0 terminated list. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) MODULE_DEVICE_TABLE(pci, genwqe_device_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) * genwqe_dev_alloc() - Create and prepare a new card descriptor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) * Return: Pointer to card descriptor, or ERR_PTR(err) on error
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) static struct genwqe_dev *genwqe_dev_alloc(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) unsigned int i = 0, j;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) struct genwqe_dev *cd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) for (i = 0; i < GENWQE_CARD_NO_MAX; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) if (genwqe_devices[i] == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) if (i >= GENWQE_CARD_NO_MAX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) return ERR_PTR(-ENODEV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) cd = kzalloc(sizeof(struct genwqe_dev), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) if (!cd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) return ERR_PTR(-ENOMEM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) cd->card_idx = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) cd->class_genwqe = class_genwqe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) cd->debugfs_genwqe = debugfs_genwqe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) * This comes from kernel config option and can be overritten via
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) * debugfs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) cd->use_platform_recovery = CONFIG_GENWQE_PLATFORM_ERROR_RECOVERY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) init_waitqueue_head(&cd->queue_waitq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) spin_lock_init(&cd->file_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) INIT_LIST_HEAD(&cd->file_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) cd->card_state = GENWQE_CARD_UNUSED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) spin_lock_init(&cd->print_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) cd->ddcb_software_timeout = GENWQE_DDCB_SOFTWARE_TIMEOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) cd->kill_timeout = GENWQE_KILL_TIMEOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) for (j = 0; j < GENWQE_MAX_VFS; j++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) cd->vf_jobtimeout_msec[j] = GENWQE_VF_JOBTIMEOUT_MSEC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) genwqe_devices[i] = cd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) return cd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) static void genwqe_dev_free(struct genwqe_dev *cd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) if (!cd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) genwqe_devices[cd->card_idx] = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) kfree(cd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) * genwqe_bus_reset() - Card recovery
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) * @cd: GenWQE device information
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) * pci_reset_function() will recover the device and ensure that the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) * registers are accessible again when it completes with success. If
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) * not, the card will stay dead and registers will be unaccessible
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) * still.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) static int genwqe_bus_reset(struct genwqe_dev *cd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) int rc = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) struct pci_dev *pci_dev = cd->pci_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) void __iomem *mmio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) if (cd->err_inject & GENWQE_INJECT_BUS_RESET_FAILURE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) mmio = cd->mmio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) cd->mmio = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) pci_iounmap(pci_dev, mmio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) pci_release_mem_regions(pci_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) * Firmware/BIOS might change memory mapping during bus reset.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) * Settings like enable bus-mastering, ... are backuped and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) * restored by the pci_reset_function().
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) dev_dbg(&pci_dev->dev, "[%s] pci_reset function ...\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) rc = pci_reset_function(pci_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) if (rc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) dev_err(&pci_dev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) "[%s] err: failed reset func (rc %d)\n", __func__, rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) dev_dbg(&pci_dev->dev, "[%s] done with rc=%d\n", __func__, rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) * Here is the right spot to clear the register read
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) * failure. pci_bus_reset() does this job in real systems.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) cd->err_inject &= ~(GENWQE_INJECT_HARDWARE_FAILURE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) GENWQE_INJECT_GFIR_FATAL |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) GENWQE_INJECT_GFIR_INFO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) rc = pci_request_mem_regions(pci_dev, genwqe_driver_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) if (rc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) dev_err(&pci_dev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) "[%s] err: request bars failed (%d)\n", __func__, rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) cd->mmio = pci_iomap(pci_dev, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) if (cd->mmio == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) dev_err(&pci_dev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) "[%s] err: mapping BAR0 failed\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) * Hardware circumvention section. Certain bitstreams in our test-lab
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) * had different kinds of problems. Here is where we adjust those
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) * bitstreams to function will with this version of our device driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) * Thise circumventions are applied to the physical function only.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) * The magical numbers below are identifying development/manufacturing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) * versions of the bitstream used on the card.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) * Turn off error reporting for old/manufacturing images.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) bool genwqe_need_err_masking(struct genwqe_dev *cd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) return (cd->slu_unitcfg & 0xFFFF0ull) < 0x32170ull;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) static void genwqe_tweak_hardware(struct genwqe_dev *cd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) struct pci_dev *pci_dev = cd->pci_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) /* Mask FIRs for development images */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) if (((cd->slu_unitcfg & 0xFFFF0ull) >= 0x32000ull) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) ((cd->slu_unitcfg & 0xFFFF0ull) <= 0x33250ull)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) dev_warn(&pci_dev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) "FIRs masked due to bitstream %016llx.%016llx\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) cd->slu_unitcfg, cd->app_unitcfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) __genwqe_writeq(cd, IO_APP_SEC_LEM_DEBUG_OVR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 0xFFFFFFFFFFFFFFFFull);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) __genwqe_writeq(cd, IO_APP_ERR_ACT_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 0x0000000000000000ull);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) * genwqe_recovery_on_fatal_gfir_required() - Version depended actions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) * @cd: GenWQE device information
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) * Bitstreams older than 2013-02-17 have a bug where fatal GFIRs must
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) * be ignored. This is e.g. true for the bitstream we gave to the card
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) * manufacturer, but also for some old bitstreams we released to our
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) * test-lab.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) int genwqe_recovery_on_fatal_gfir_required(struct genwqe_dev *cd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) return (cd->slu_unitcfg & 0xFFFF0ull) >= 0x32170ull;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) int genwqe_flash_readback_fails(struct genwqe_dev *cd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) return (cd->slu_unitcfg & 0xFFFF0ull) < 0x32170ull;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) * genwqe_T_psec() - Calculate PF/VF timeout register content
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) * @cd: GenWQE device information
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) * Note: From a design perspective it turned out to be a bad idea to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) * use codes here to specifiy the frequency/speed values. An old
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) * driver cannot understand new codes and is therefore always a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) * problem. Better is to measure out the value or put the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) * speed/frequency directly into a register which is always a valid
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) * value for old as well as for new software.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) /* T = 1/f */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) static int genwqe_T_psec(struct genwqe_dev *cd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) u16 speed; /* 1/f -> 250, 200, 166, 175 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) static const int T[] = { 4000, 5000, 6000, 5714 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) speed = (u16)((cd->slu_unitcfg >> 28) & 0x0full);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) if (speed >= ARRAY_SIZE(T))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) return -1; /* illegal value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) return T[speed];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) * genwqe_setup_pf_jtimer() - Setup PF hardware timeouts for DDCB execution
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) * @cd: GenWQE device information
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) * Do this _after_ card_reset() is called. Otherwise the values will
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) * vanish. The settings need to be done when the queues are inactive.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) * The max. timeout value is 2^(10+x) * T (6ns for 166MHz) * 15/16.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) * The min. timeout value is 2^(10+x) * T (6ns for 166MHz) * 14/16.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) static bool genwqe_setup_pf_jtimer(struct genwqe_dev *cd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) u32 T = genwqe_T_psec(cd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) u64 x;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) if (GENWQE_PF_JOBTIMEOUT_MSEC == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) /* PF: large value needed, flash update 2sec per block */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) x = ilog2(GENWQE_PF_JOBTIMEOUT_MSEC *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 16000000000uL/(T * 15)) - 10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) genwqe_write_vreg(cd, IO_SLC_VF_APPJOB_TIMEOUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 0xff00 | (x & 0xff), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) * genwqe_setup_vf_jtimer() - Setup VF hardware timeouts for DDCB execution
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) * @cd: GenWQE device information
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) static bool genwqe_setup_vf_jtimer(struct genwqe_dev *cd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) struct pci_dev *pci_dev = cd->pci_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) unsigned int vf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) u32 T = genwqe_T_psec(cd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) u64 x;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) int totalvfs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) totalvfs = pci_sriov_get_totalvfs(pci_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) if (totalvfs <= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) for (vf = 0; vf < totalvfs; vf++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) if (cd->vf_jobtimeout_msec[vf] == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) x = ilog2(cd->vf_jobtimeout_msec[vf] *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 16000000000uL/(T * 15)) - 10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) genwqe_write_vreg(cd, IO_SLC_VF_APPJOB_TIMEOUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) 0xff00 | (x & 0xff), vf + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) static int genwqe_ffdc_buffs_alloc(struct genwqe_dev *cd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) unsigned int type, e = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) for (type = 0; type < GENWQE_DBG_UNITS; type++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) switch (type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) case GENWQE_DBG_UNIT0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) e = genwqe_ffdc_buff_size(cd, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) case GENWQE_DBG_UNIT1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) e = genwqe_ffdc_buff_size(cd, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) case GENWQE_DBG_UNIT2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) e = genwqe_ffdc_buff_size(cd, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) case GENWQE_DBG_REGS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) e = GENWQE_FFDC_REGS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) /* currently support only the debug units mentioned here */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) cd->ffdc[type].entries = e;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) cd->ffdc[type].regs =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) kmalloc_array(e, sizeof(struct genwqe_reg),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) * regs == NULL is ok, the using code treats this as no regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) * Printing warning is ok in this case.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) static void genwqe_ffdc_buffs_free(struct genwqe_dev *cd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) unsigned int type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) for (type = 0; type < GENWQE_DBG_UNITS; type++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) kfree(cd->ffdc[type].regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) cd->ffdc[type].regs = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) static int genwqe_read_ids(struct genwqe_dev *cd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) int err = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) int slu_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) struct pci_dev *pci_dev = cd->pci_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) cd->slu_unitcfg = __genwqe_readq(cd, IO_SLU_UNITCFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) if (cd->slu_unitcfg == IO_ILLEGAL_VALUE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) dev_err(&pci_dev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) "err: SLUID=%016llx\n", cd->slu_unitcfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) err = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) goto out_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) slu_id = genwqe_get_slu_id(cd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) if (slu_id < GENWQE_SLU_ARCH_REQ || slu_id == 0xff) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) dev_err(&pci_dev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) "err: incompatible SLU Architecture %u\n", slu_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) err = -ENOENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) goto out_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) cd->app_unitcfg = __genwqe_readq(cd, IO_APP_UNITCFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) if (cd->app_unitcfg == IO_ILLEGAL_VALUE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) dev_err(&pci_dev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) "err: APPID=%016llx\n", cd->app_unitcfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) err = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) goto out_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) genwqe_read_app_id(cd, cd->app_name, sizeof(cd->app_name));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) * Is access to all registers possible? If we are a VF the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) * answer is obvious. If we run fully virtualized, we need to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) * check if we can access all registers. If we do not have
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) * full access we will cause an UR and some informational FIRs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) * in the PF, but that should not harm.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) if (pci_dev->is_virtfn)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) cd->is_privileged = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) cd->is_privileged = (__genwqe_readq(cd, IO_SLU_BITSTREAM)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) != IO_ILLEGAL_VALUE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) out_err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) static int genwqe_start(struct genwqe_dev *cd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) struct pci_dev *pci_dev = cd->pci_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) err = genwqe_read_ids(cd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) if (genwqe_is_privileged(cd)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) /* do this after the tweaks. alloc fail is acceptable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) genwqe_ffdc_buffs_alloc(cd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) genwqe_stop_traps(cd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) /* Collect registers e.g. FIRs, UNITIDs, traces ... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) genwqe_read_ffdc_regs(cd, cd->ffdc[GENWQE_DBG_REGS].regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) cd->ffdc[GENWQE_DBG_REGS].entries, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) genwqe_ffdc_buff_read(cd, GENWQE_DBG_UNIT0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) cd->ffdc[GENWQE_DBG_UNIT0].regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) cd->ffdc[GENWQE_DBG_UNIT0].entries);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) genwqe_ffdc_buff_read(cd, GENWQE_DBG_UNIT1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) cd->ffdc[GENWQE_DBG_UNIT1].regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) cd->ffdc[GENWQE_DBG_UNIT1].entries);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) genwqe_ffdc_buff_read(cd, GENWQE_DBG_UNIT2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) cd->ffdc[GENWQE_DBG_UNIT2].regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) cd->ffdc[GENWQE_DBG_UNIT2].entries);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) genwqe_start_traps(cd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) if (cd->card_state == GENWQE_CARD_FATAL_ERROR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) dev_warn(&pci_dev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) "[%s] chip reload/recovery!\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) * Stealth Mode: Reload chip on either hot
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) * reset or PERST.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) cd->softreset = 0x7Cull;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) __genwqe_writeq(cd, IO_SLC_CFGREG_SOFTRESET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) cd->softreset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) err = genwqe_bus_reset(cd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) if (err != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) dev_err(&pci_dev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) "[%s] err: bus reset failed!\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) * Re-read the IDs because
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) * it could happen that the bitstream load
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) * failed!
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) err = genwqe_read_ids(cd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) err = genwqe_setup_service_layer(cd); /* does a reset to the card */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) if (err != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) dev_err(&pci_dev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) "[%s] err: could not setup servicelayer!\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) err = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) if (genwqe_is_privileged(cd)) { /* code is running _after_ reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) genwqe_tweak_hardware(cd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) genwqe_setup_pf_jtimer(cd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) genwqe_setup_vf_jtimer(cd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) err = genwqe_device_create(cd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) dev_err(&pci_dev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) "err: chdev init failed! (err=%d)\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) goto out_release_service_layer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) out_release_service_layer:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) genwqe_release_service_layer(cd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) if (genwqe_is_privileged(cd))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) genwqe_ffdc_buffs_free(cd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) * genwqe_stop() - Stop card operation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) * @cd: GenWQE device information
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) * Recovery notes:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) * As long as genwqe_thread runs we might access registers during
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) * error data capture. Same is with the genwqe_health_thread.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) * When genwqe_bus_reset() fails this function might called two times:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) * first by the genwqe_health_thread() and later by genwqe_remove() to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) * unbind the device. We must be able to survive that.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) * This function must be robust enough to be called twice.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) static int genwqe_stop(struct genwqe_dev *cd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) genwqe_finish_queue(cd); /* no register access */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) genwqe_device_remove(cd); /* device removed, procs killed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) genwqe_release_service_layer(cd); /* here genwqe_thread is stopped */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) if (genwqe_is_privileged(cd)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) pci_disable_sriov(cd->pci_dev); /* access pci config space */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) genwqe_ffdc_buffs_free(cd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) * genwqe_recover_card() - Try to recover the card if it is possible
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) * @cd: GenWQE device information
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) * @fatal_err: Indicate whether to attempt soft reset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) * If fatal_err is set no register access is possible anymore. It is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) * likely that genwqe_start fails in that situation. Proper error
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) * handling is required in this case.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) * genwqe_bus_reset() will cause the pci code to call genwqe_remove()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) * and later genwqe_probe() for all virtual functions.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) static int genwqe_recover_card(struct genwqe_dev *cd, int fatal_err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) struct pci_dev *pci_dev = cd->pci_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) genwqe_stop(cd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) * Make sure chip is not reloaded to maintain FFDC. Write SLU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) * Reset Register, CPLDReset field to 0.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) if (!fatal_err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) cd->softreset = 0x70ull;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) __genwqe_writeq(cd, IO_SLC_CFGREG_SOFTRESET, cd->softreset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) rc = genwqe_bus_reset(cd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) dev_err(&pci_dev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) "[%s] err: card recovery impossible!\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) rc = genwqe_start(cd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) if (rc < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) dev_err(&pci_dev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) "[%s] err: failed to launch device!\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) static int genwqe_health_check_cond(struct genwqe_dev *cd, u64 *gfir)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) *gfir = __genwqe_readq(cd, IO_SLC_CFGREG_GFIR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) return (*gfir & GFIR_ERR_TRIGGER) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) genwqe_recovery_on_fatal_gfir_required(cd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) * genwqe_fir_checking() - Check the fault isolation registers of the card
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) * @cd: GenWQE device information
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) * If this code works ok, can be tried out with help of the genwqe_poke tool:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) * sudo ./tools/genwqe_poke 0x8 0xfefefefefef
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) * Now the relevant FIRs/sFIRs should be printed out and the driver should
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) * invoke recovery (devices are removed and readded).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) static u64 genwqe_fir_checking(struct genwqe_dev *cd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) int j, iterations = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) u64 mask, fir, fec, uid, gfir, gfir_masked, sfir, sfec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) u32 fir_addr, fir_clr_addr, fec_addr, sfir_addr, sfec_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) struct pci_dev *pci_dev = cd->pci_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) healthMonitor:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) iterations++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) if (iterations > 16) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) dev_err(&pci_dev->dev, "* exit looping after %d times\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) iterations);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) goto fatal_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) gfir = __genwqe_readq(cd, IO_SLC_CFGREG_GFIR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) if (gfir != 0x0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) dev_err(&pci_dev->dev, "* 0x%08x 0x%016llx\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) IO_SLC_CFGREG_GFIR, gfir);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) if (gfir == IO_ILLEGAL_VALUE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) goto fatal_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) * Avoid printing when to GFIR bit is on prevents contignous
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) * printout e.g. for the following bug:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) * FIR set without a 2ndary FIR/FIR cannot be cleared
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) * Comment out the following if to get the prints:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) if (gfir == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) gfir_masked = gfir & GFIR_ERR_TRIGGER; /* fatal errors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) for (uid = 0; uid < GENWQE_MAX_UNITS; uid++) { /* 0..2 in zEDC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) /* read the primary FIR (pfir) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) fir_addr = (uid << 24) + 0x08;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) fir = __genwqe_readq(cd, fir_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) if (fir == 0x0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) continue; /* no error in this unit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) dev_err(&pci_dev->dev, "* 0x%08x 0x%016llx\n", fir_addr, fir);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) if (fir == IO_ILLEGAL_VALUE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) goto fatal_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) /* read primary FEC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) fec_addr = (uid << 24) + 0x18;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) fec = __genwqe_readq(cd, fec_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) dev_err(&pci_dev->dev, "* 0x%08x 0x%016llx\n", fec_addr, fec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) if (fec == IO_ILLEGAL_VALUE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) goto fatal_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) for (j = 0, mask = 1ULL; j < 64; j++, mask <<= 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) /* secondary fir empty, skip it */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) if ((fir & mask) == 0x0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) sfir_addr = (uid << 24) + 0x100 + 0x08 * j;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) sfir = __genwqe_readq(cd, sfir_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) if (sfir == IO_ILLEGAL_VALUE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) goto fatal_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) dev_err(&pci_dev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) "* 0x%08x 0x%016llx\n", sfir_addr, sfir);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) sfec_addr = (uid << 24) + 0x300 + 0x08 * j;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) sfec = __genwqe_readq(cd, sfec_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) if (sfec == IO_ILLEGAL_VALUE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) goto fatal_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) dev_err(&pci_dev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) "* 0x%08x 0x%016llx\n", sfec_addr, sfec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) gfir = __genwqe_readq(cd, IO_SLC_CFGREG_GFIR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) if (gfir == IO_ILLEGAL_VALUE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) goto fatal_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) /* gfir turned on during routine! get out and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) start over. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) if ((gfir_masked == 0x0) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) (gfir & GFIR_ERR_TRIGGER)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) goto healthMonitor;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) /* do not clear if we entered with a fatal gfir */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) if (gfir_masked == 0x0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) /* NEW clear by mask the logged bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) sfir_addr = (uid << 24) + 0x100 + 0x08 * j;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) __genwqe_writeq(cd, sfir_addr, sfir);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) dev_dbg(&pci_dev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) "[HM] Clearing 2ndary FIR 0x%08x with 0x%016llx\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) sfir_addr, sfir);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) * note, these cannot be error-Firs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) * since gfir_masked is 0 after sfir
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) * was read. Also, it is safe to do
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) * this write if sfir=0. Still need to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) * clear the primary. This just means
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) * there is no secondary FIR.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) /* clear by mask the logged bit. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) fir_clr_addr = (uid << 24) + 0x10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) __genwqe_writeq(cd, fir_clr_addr, mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) dev_dbg(&pci_dev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) "[HM] Clearing primary FIR 0x%08x with 0x%016llx\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) fir_clr_addr, mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) gfir = __genwqe_readq(cd, IO_SLC_CFGREG_GFIR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) if (gfir == IO_ILLEGAL_VALUE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) goto fatal_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) if ((gfir_masked == 0x0) && (gfir & GFIR_ERR_TRIGGER)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) * Check once more that it didn't go on after all the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) * FIRS were cleared.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) dev_dbg(&pci_dev->dev, "ACK! Another FIR! Recursing %d!\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) iterations);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) goto healthMonitor;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) return gfir_masked;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) fatal_error:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) return IO_ILLEGAL_VALUE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) * genwqe_pci_fundamental_reset() - trigger a PCIe fundamental reset on the slot
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) * @pci_dev: PCI device information struct
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) * Note: pci_set_pcie_reset_state() is not implemented on all archs, so this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) * reset method will not work in all cases.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) * Return: 0 on success or error code from pci_set_pcie_reset_state()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) static int genwqe_pci_fundamental_reset(struct pci_dev *pci_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) * lock pci config space access from userspace,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) * save state and issue PCIe fundamental reset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) pci_cfg_access_lock(pci_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) pci_save_state(pci_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) rc = pci_set_pcie_reset_state(pci_dev, pcie_warm_reset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) if (!rc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) /* keep PCIe reset asserted for 250ms */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) msleep(250);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) pci_set_pcie_reset_state(pci_dev, pcie_deassert_reset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) /* Wait for 2s to reload flash and train the link */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) msleep(2000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) pci_restore_state(pci_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) pci_cfg_access_unlock(pci_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) static int genwqe_platform_recovery(struct genwqe_dev *cd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) struct pci_dev *pci_dev = cd->pci_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) dev_info(&pci_dev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) "[%s] resetting card for error recovery\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) /* Clear out error injection flags */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) cd->err_inject &= ~(GENWQE_INJECT_HARDWARE_FAILURE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) GENWQE_INJECT_GFIR_FATAL |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) GENWQE_INJECT_GFIR_INFO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) genwqe_stop(cd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) /* Try recoverying the card with fundamental reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) rc = genwqe_pci_fundamental_reset(pci_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) if (!rc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) rc = genwqe_start(cd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) if (!rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) dev_info(&pci_dev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) "[%s] card recovered\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) dev_err(&pci_dev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) "[%s] err: cannot start card services! (err=%d)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) __func__, rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) dev_err(&pci_dev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) "[%s] card reset failed\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) * genwqe_reload_bistream() - reload card bitstream
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) * @cd: GenWQE device information
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) * Set the appropriate register and call fundamental reset to reaload the card
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) * bitstream.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) * Return: 0 on success, error code otherwise
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) static int genwqe_reload_bistream(struct genwqe_dev *cd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) struct pci_dev *pci_dev = cd->pci_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) dev_info(&pci_dev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) "[%s] resetting card for bitstream reload\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) genwqe_stop(cd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) * Cause a CPLD reprogram with the 'next_bitstream'
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) * partition on PCIe hot or fundamental reset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) __genwqe_writeq(cd, IO_SLC_CFGREG_SOFTRESET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) (cd->softreset & 0xcull) | 0x70ull);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) rc = genwqe_pci_fundamental_reset(pci_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) if (rc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) * A fundamental reset failure can be caused
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) * by lack of support on the arch, so we just
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) * log the error and try to start the card
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) * again.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) dev_err(&pci_dev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) "[%s] err: failed to reset card for bitstream reload\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) rc = genwqe_start(cd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) if (rc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) dev_err(&pci_dev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) "[%s] err: cannot start card services! (err=%d)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) __func__, rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) dev_info(&pci_dev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) "[%s] card reloaded\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) * genwqe_health_thread() - Health checking thread
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) * @data: GenWQE device information
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) * This thread is only started for the PF of the card.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) * This thread monitors the health of the card. A critical situation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) * is when we read registers which contain -1 (IO_ILLEGAL_VALUE). In
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) * this case we need to be recovered from outside. Writing to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) * registers will very likely not work either.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) * This thread must only exit if kthread_should_stop() becomes true.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) * Condition for the health-thread to trigger:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) * a) when a kthread_stop() request comes in or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) * b) a critical GFIR occured
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) * Informational GFIRs are checked and potentially printed in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) * GENWQE_HEALTH_CHECK_INTERVAL seconds.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) static int genwqe_health_thread(void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) int rc, should_stop = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) struct genwqe_dev *cd = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) struct pci_dev *pci_dev = cd->pci_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) u64 gfir, gfir_masked, slu_unitcfg, app_unitcfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) health_thread_begin:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) while (!kthread_should_stop()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) rc = wait_event_interruptible_timeout(cd->health_waitq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) (genwqe_health_check_cond(cd, &gfir) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) (should_stop = kthread_should_stop())),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) GENWQE_HEALTH_CHECK_INTERVAL * HZ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) if (should_stop)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) if (gfir == IO_ILLEGAL_VALUE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) dev_err(&pci_dev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) "[%s] GFIR=%016llx\n", __func__, gfir);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) goto fatal_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) slu_unitcfg = __genwqe_readq(cd, IO_SLU_UNITCFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) if (slu_unitcfg == IO_ILLEGAL_VALUE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) dev_err(&pci_dev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) "[%s] SLU_UNITCFG=%016llx\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) __func__, slu_unitcfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) goto fatal_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) app_unitcfg = __genwqe_readq(cd, IO_APP_UNITCFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) if (app_unitcfg == IO_ILLEGAL_VALUE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) dev_err(&pci_dev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) "[%s] APP_UNITCFG=%016llx\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) __func__, app_unitcfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) goto fatal_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) gfir = __genwqe_readq(cd, IO_SLC_CFGREG_GFIR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) if (gfir == IO_ILLEGAL_VALUE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) dev_err(&pci_dev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) "[%s] %s: GFIR=%016llx\n", __func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) (gfir & GFIR_ERR_TRIGGER) ? "err" : "info",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) gfir);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) goto fatal_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) gfir_masked = genwqe_fir_checking(cd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) if (gfir_masked == IO_ILLEGAL_VALUE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) goto fatal_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) * GFIR ErrorTrigger bits set => reset the card!
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) * Never do this for old/manufacturing images!
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) if ((gfir_masked) && !cd->skip_recovery &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) genwqe_recovery_on_fatal_gfir_required(cd)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) cd->card_state = GENWQE_CARD_FATAL_ERROR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) rc = genwqe_recover_card(cd, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) if (rc < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) /* FIXME Card is unusable and needs unbind! */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) goto fatal_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) if (cd->card_state == GENWQE_CARD_RELOAD_BITSTREAM) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) /* Userspace requested card bitstream reload */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) rc = genwqe_reload_bistream(cd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) goto fatal_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) cd->last_gfir = gfir;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) cond_resched();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) fatal_error:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) if (cd->use_platform_recovery) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) * Since we use raw accessors, EEH errors won't be detected
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) * by the platform until we do a non-raw MMIO or config space
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) * read
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) readq(cd->mmio + IO_SLC_CFGREG_GFIR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) /* We do nothing if the card is going over PCI recovery */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) if (pci_channel_offline(pci_dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) * If it's supported by the platform, we try a fundamental reset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) * to recover from a fatal error. Otherwise, we continue to wait
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) * for an external recovery procedure to take care of it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) rc = genwqe_platform_recovery(cd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) if (!rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) goto health_thread_begin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) dev_err(&pci_dev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) "[%s] card unusable. Please trigger unbind!\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) /* Bring down logical devices to inform user space via udev remove. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) cd->card_state = GENWQE_CARD_FATAL_ERROR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) genwqe_stop(cd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) /* genwqe_bus_reset failed(). Now wait for genwqe_remove(). */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) while (!kthread_should_stop())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) cond_resched();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) static int genwqe_health_check_start(struct genwqe_dev *cd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) if (GENWQE_HEALTH_CHECK_INTERVAL <= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) return 0; /* valid for disabling the service */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) /* moved before request_irq() */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) /* init_waitqueue_head(&cd->health_waitq); */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) cd->health_thread = kthread_run(genwqe_health_thread, cd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) GENWQE_DEVNAME "%d_health",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) cd->card_idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) if (IS_ERR(cd->health_thread)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) rc = PTR_ERR(cd->health_thread);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) cd->health_thread = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) static int genwqe_health_thread_running(struct genwqe_dev *cd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) return cd->health_thread != NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) static int genwqe_health_check_stop(struct genwqe_dev *cd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) if (!genwqe_health_thread_running(cd))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) kthread_stop(cd->health_thread);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) cd->health_thread = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) * genwqe_pci_setup() - Allocate PCIe related resources for our card
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) * @cd: GenWQE device information
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) static int genwqe_pci_setup(struct genwqe_dev *cd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) struct pci_dev *pci_dev = cd->pci_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) err = pci_enable_device_mem(pci_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) dev_err(&pci_dev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) "err: failed to enable pci memory (err=%d)\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) goto err_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) /* Reserve PCI I/O and memory resources */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) err = pci_request_mem_regions(pci_dev, genwqe_driver_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) dev_err(&pci_dev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) "[%s] err: request bars failed (%d)\n", __func__, err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) err = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) goto err_disable_device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) /* check for 64-bit DMA address supported (DAC) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) if (!pci_set_dma_mask(pci_dev, DMA_BIT_MASK(64))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) err = pci_set_consistent_dma_mask(pci_dev, DMA_BIT_MASK(64));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) dev_err(&pci_dev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) "err: DMA64 consistent mask error\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) err = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) goto out_release_resources;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) /* check for 32-bit DMA address supported (SAC) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) } else if (!pci_set_dma_mask(pci_dev, DMA_BIT_MASK(32))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) err = pci_set_consistent_dma_mask(pci_dev, DMA_BIT_MASK(32));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) dev_err(&pci_dev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) "err: DMA32 consistent mask error\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) err = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) goto out_release_resources;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) dev_err(&pci_dev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) "err: neither DMA32 nor DMA64 supported\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) err = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) goto out_release_resources;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) pci_set_master(pci_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) pci_enable_pcie_error_reporting(pci_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) /* EEH recovery requires PCIe fundamental reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) pci_dev->needs_freset = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) /* request complete BAR-0 space (length = 0) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) cd->mmio_len = pci_resource_len(pci_dev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) cd->mmio = pci_iomap(pci_dev, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) if (cd->mmio == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) dev_err(&pci_dev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) "[%s] err: mapping BAR0 failed\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) err = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) goto out_release_resources;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) cd->num_vfs = pci_sriov_get_totalvfs(pci_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) if (cd->num_vfs < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) cd->num_vfs = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) err = genwqe_read_ids(cd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) goto out_iounmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) out_iounmap:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) pci_iounmap(pci_dev, cd->mmio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) out_release_resources:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) pci_release_mem_regions(pci_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) err_disable_device:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) pci_disable_device(pci_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) err_out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) * genwqe_pci_remove() - Free PCIe related resources for our card
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) * @cd: GenWQE device information
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) static void genwqe_pci_remove(struct genwqe_dev *cd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) struct pci_dev *pci_dev = cd->pci_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) if (cd->mmio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) pci_iounmap(pci_dev, cd->mmio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) pci_release_mem_regions(pci_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) pci_disable_device(pci_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) * genwqe_probe() - Device initialization
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) * @pci_dev: PCI device information struct
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) * @id: PCI device ID
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) * Callable for multiple cards. This function is called on bind.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) * Return: 0 if succeeded, < 0 when failed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) static int genwqe_probe(struct pci_dev *pci_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) const struct pci_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) struct genwqe_dev *cd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) genwqe_init_crc32();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) cd = genwqe_dev_alloc();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) if (IS_ERR(cd)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) dev_err(&pci_dev->dev, "err: could not alloc mem (err=%d)!\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) (int)PTR_ERR(cd));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) return PTR_ERR(cd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) dev_set_drvdata(&pci_dev->dev, cd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) cd->pci_dev = pci_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) err = genwqe_pci_setup(cd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) dev_err(&pci_dev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) "err: problems with PCI setup (err=%d)\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) goto out_free_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) err = genwqe_start(cd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) dev_err(&pci_dev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) "err: cannot start card services! (err=%d)\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) goto out_pci_remove;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) if (genwqe_is_privileged(cd)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) err = genwqe_health_check_start(cd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) dev_err(&pci_dev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) "err: cannot start health checking! (err=%d)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) goto out_stop_services;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) out_stop_services:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) genwqe_stop(cd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) out_pci_remove:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) genwqe_pci_remove(cd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) out_free_dev:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) genwqe_dev_free(cd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) * genwqe_remove() - Called when device is removed (hot-plugable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) * @pci_dev: PCI device information struct
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) * Or when driver is unloaded respecitively when unbind is done.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) static void genwqe_remove(struct pci_dev *pci_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) struct genwqe_dev *cd = dev_get_drvdata(&pci_dev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) genwqe_health_check_stop(cd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) * genwqe_stop() must survive if it is called twice
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) * sequentially. This happens when the health thread calls it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) * and fails on genwqe_bus_reset().
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) genwqe_stop(cd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) genwqe_pci_remove(cd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) genwqe_dev_free(cd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) * genwqe_err_error_detected() - Error detection callback
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) * @pci_dev: PCI device information struct
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) * @state: PCI channel state
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) * This callback is called by the PCI subsystem whenever a PCI bus
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) * error is detected.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) static pci_ers_result_t genwqe_err_error_detected(struct pci_dev *pci_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) pci_channel_state_t state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) struct genwqe_dev *cd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) dev_err(&pci_dev->dev, "[%s] state=%d\n", __func__, state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) cd = dev_get_drvdata(&pci_dev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) if (cd == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) return PCI_ERS_RESULT_DISCONNECT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) /* Stop the card */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) genwqe_health_check_stop(cd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) genwqe_stop(cd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) * On permanent failure, the PCI code will call device remove
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) * after the return of this function.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) * genwqe_stop() can be called twice.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) if (state == pci_channel_io_perm_failure) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) return PCI_ERS_RESULT_DISCONNECT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) genwqe_pci_remove(cd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) return PCI_ERS_RESULT_NEED_RESET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) static pci_ers_result_t genwqe_err_slot_reset(struct pci_dev *pci_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) struct genwqe_dev *cd = dev_get_drvdata(&pci_dev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) rc = genwqe_pci_setup(cd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) if (!rc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) return PCI_ERS_RESULT_RECOVERED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) dev_err(&pci_dev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) "err: problems with PCI setup (err=%d)\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) return PCI_ERS_RESULT_DISCONNECT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) static pci_ers_result_t genwqe_err_result_none(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) return PCI_ERS_RESULT_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) static void genwqe_err_resume(struct pci_dev *pci_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) struct genwqe_dev *cd = dev_get_drvdata(&pci_dev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) rc = genwqe_start(cd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) if (!rc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) rc = genwqe_health_check_start(cd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) dev_err(&pci_dev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) "err: cannot start health checking! (err=%d)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) dev_err(&pci_dev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) "err: cannot start card services! (err=%d)\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) static int genwqe_sriov_configure(struct pci_dev *dev, int numvfs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) struct genwqe_dev *cd = dev_get_drvdata(&dev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) if (numvfs > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) genwqe_setup_vf_jtimer(cd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) rc = pci_enable_sriov(dev, numvfs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) if (rc < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) return numvfs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) if (numvfs == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) pci_disable_sriov(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) static const struct pci_error_handlers genwqe_err_handler = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) .error_detected = genwqe_err_error_detected,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) .mmio_enabled = genwqe_err_result_none,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) .slot_reset = genwqe_err_slot_reset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) .resume = genwqe_err_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) static struct pci_driver genwqe_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) .name = genwqe_driver_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) .id_table = genwqe_device_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) .probe = genwqe_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) .remove = genwqe_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) .sriov_configure = genwqe_sriov_configure,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) .err_handler = &genwqe_err_handler,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) * genwqe_devnode() - Set default access mode for genwqe devices.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) * @dev: Pointer to device (unused)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) * @mode: Carrier to pass-back given mode (permissions)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) * Default mode should be rw for everybody. Do not change default
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) * device name.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) static char *genwqe_devnode(struct device *dev, umode_t *mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) if (mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) *mode = 0666;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) * genwqe_init_module() - Driver registration and initialization
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) static int __init genwqe_init_module(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) class_genwqe = class_create(THIS_MODULE, GENWQE_DEVNAME);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) if (IS_ERR(class_genwqe)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) pr_err("[%s] create class failed\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) class_genwqe->devnode = genwqe_devnode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) debugfs_genwqe = debugfs_create_dir(GENWQE_DEVNAME, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) rc = pci_register_driver(&genwqe_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) pr_err("[%s] pci_reg_driver (rc=%d)\n", __func__, rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) goto err_out0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) err_out0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) debugfs_remove(debugfs_genwqe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) class_destroy(class_genwqe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) * genwqe_exit_module() - Driver exit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) static void __exit genwqe_exit_module(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) pci_unregister_driver(&genwqe_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) debugfs_remove(debugfs_genwqe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) class_destroy(class_genwqe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) module_init(genwqe_init_module);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) module_exit(genwqe_exit_module);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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