Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Driver for 93xx46 EEPROMs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * (C) 2011 DENX Software Engineering, Anatolij Gustschin <agust@denx.de>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/gpio/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/mutex.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/of_gpio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include <linux/spi/spi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #include <linux/nvmem-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #include <linux/eeprom_93xx46.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #define OP_START	0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #define OP_WRITE	(OP_START | 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #define OP_READ		(OP_START | 0x2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #define ADDR_EWDS	0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define ADDR_ERAL	0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #define ADDR_EWEN	0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) struct eeprom_93xx46_devtype_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 	unsigned int quirks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) static const struct eeprom_93xx46_devtype_data atmel_at93c46d_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 	.quirks = EEPROM_93XX46_QUIRK_SINGLE_WORD_READ |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 		  EEPROM_93XX46_QUIRK_INSTRUCTION_LENGTH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) static const struct eeprom_93xx46_devtype_data microchip_93lc46b_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 	.quirks = EEPROM_93XX46_QUIRK_EXTRA_READ_CYCLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) struct eeprom_93xx46_dev {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 	struct spi_device *spi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 	struct eeprom_93xx46_platform_data *pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 	struct mutex lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 	struct nvmem_config nvmem_config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 	struct nvmem_device *nvmem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 	int addrlen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 	int size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) static inline bool has_quirk_single_word_read(struct eeprom_93xx46_dev *edev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 	return edev->pdata->quirks & EEPROM_93XX46_QUIRK_SINGLE_WORD_READ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) static inline bool has_quirk_instruction_length(struct eeprom_93xx46_dev *edev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	return edev->pdata->quirks & EEPROM_93XX46_QUIRK_INSTRUCTION_LENGTH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) static inline bool has_quirk_extra_read_cycle(struct eeprom_93xx46_dev *edev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	return edev->pdata->quirks & EEPROM_93XX46_QUIRK_EXTRA_READ_CYCLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) static int eeprom_93xx46_read(void *priv, unsigned int off,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 			      void *val, size_t count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	struct eeprom_93xx46_dev *edev = priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	char *buf = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	int err = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	if (unlikely(off >= edev->size))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	if ((off + count) > edev->size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 		count = edev->size - off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	if (unlikely(!count))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 		return count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	mutex_lock(&edev->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	if (edev->pdata->prepare)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 		edev->pdata->prepare(edev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	while (count) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 		struct spi_message m;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 		struct spi_transfer t[2] = { { 0 } };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 		u16 cmd_addr = OP_READ << edev->addrlen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 		size_t nbytes = count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 		int bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 		if (edev->addrlen == 7) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 			cmd_addr |= off & 0x7f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 			bits = 10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 			if (has_quirk_single_word_read(edev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 				nbytes = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 		} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 			cmd_addr |= (off >> 1) & 0x3f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 			bits = 9;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 			if (has_quirk_single_word_read(edev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 				nbytes = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 		dev_dbg(&edev->spi->dev, "read cmd 0x%x, %d Hz\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 			cmd_addr, edev->spi->max_speed_hz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 		if (has_quirk_extra_read_cycle(edev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 			cmd_addr <<= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 			bits += 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 		spi_message_init(&m);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 		t[0].tx_buf = (char *)&cmd_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 		t[0].len = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 		t[0].bits_per_word = bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 		spi_message_add_tail(&t[0], &m);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 		t[1].rx_buf = buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 		t[1].len = count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 		t[1].bits_per_word = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 		spi_message_add_tail(&t[1], &m);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 		err = spi_sync(edev->spi, &m);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 		/* have to wait at least Tcsl ns */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 		ndelay(250);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 		if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 			dev_err(&edev->spi->dev, "read %zu bytes at %d: err. %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 				nbytes, (int)off, err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 		buf += nbytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 		off += nbytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 		count -= nbytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	if (edev->pdata->finish)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 		edev->pdata->finish(edev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	mutex_unlock(&edev->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) static int eeprom_93xx46_ew(struct eeprom_93xx46_dev *edev, int is_on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	struct spi_message m;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	struct spi_transfer t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	int bits, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	u16 cmd_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	cmd_addr = OP_START << edev->addrlen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	if (edev->addrlen == 7) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 		cmd_addr |= (is_on ? ADDR_EWEN : ADDR_EWDS) << 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 		bits = 10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 		cmd_addr |= (is_on ? ADDR_EWEN : ADDR_EWDS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 		bits = 9;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	if (has_quirk_instruction_length(edev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 		cmd_addr <<= 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 		bits += 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	dev_dbg(&edev->spi->dev, "ew%s cmd 0x%04x, %d bits\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 			is_on ? "en" : "ds", cmd_addr, bits);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	spi_message_init(&m);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	memset(&t, 0, sizeof(t));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	t.tx_buf = &cmd_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	t.len = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	t.bits_per_word = bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	spi_message_add_tail(&t, &m);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	mutex_lock(&edev->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	if (edev->pdata->prepare)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 		edev->pdata->prepare(edev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	ret = spi_sync(edev->spi, &m);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	/* have to wait at least Tcsl ns */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	ndelay(250);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 		dev_err(&edev->spi->dev, "erase/write %sable error %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 			is_on ? "en" : "dis", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	if (edev->pdata->finish)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 		edev->pdata->finish(edev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	mutex_unlock(&edev->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) static ssize_t
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) eeprom_93xx46_write_word(struct eeprom_93xx46_dev *edev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 			 const char *buf, unsigned off)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 	struct spi_message m;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	struct spi_transfer t[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	int bits, data_len, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 	u16 cmd_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 	cmd_addr = OP_WRITE << edev->addrlen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	if (edev->addrlen == 7) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 		cmd_addr |= off & 0x7f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 		bits = 10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 		data_len = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 		cmd_addr |= (off >> 1) & 0x3f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 		bits = 9;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 		data_len = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	dev_dbg(&edev->spi->dev, "write cmd 0x%x\n", cmd_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 	spi_message_init(&m);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 	memset(t, 0, sizeof(t));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 	t[0].tx_buf = (char *)&cmd_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 	t[0].len = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 	t[0].bits_per_word = bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 	spi_message_add_tail(&t[0], &m);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 	t[1].tx_buf = buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 	t[1].len = data_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 	t[1].bits_per_word = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 	spi_message_add_tail(&t[1], &m);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 	ret = spi_sync(edev->spi, &m);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 	/* have to wait program cycle time Twc ms */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 	mdelay(6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) static int eeprom_93xx46_write(void *priv, unsigned int off,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 				   void *val, size_t count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 	struct eeprom_93xx46_dev *edev = priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 	char *buf = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 	int i, ret, step = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 	if (unlikely(off >= edev->size))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 		return -EFBIG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 	if ((off + count) > edev->size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 		count = edev->size - off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 	if (unlikely(!count))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 		return count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 	/* only write even number of bytes on 16-bit devices */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 	if (edev->addrlen == 6) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 		step = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 		count &= ~1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 	/* erase/write enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 	ret = eeprom_93xx46_ew(edev, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 	mutex_lock(&edev->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 	if (edev->pdata->prepare)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 		edev->pdata->prepare(edev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 	for (i = 0; i < count; i += step) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 		ret = eeprom_93xx46_write_word(edev, &buf[i], off + i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 		if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 			dev_err(&edev->spi->dev, "write failed at %d: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 				(int)off + i, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 	if (edev->pdata->finish)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 		edev->pdata->finish(edev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 	mutex_unlock(&edev->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 	/* erase/write disable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 	eeprom_93xx46_ew(edev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) static int eeprom_93xx46_eral(struct eeprom_93xx46_dev *edev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 	struct eeprom_93xx46_platform_data *pd = edev->pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 	struct spi_message m;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 	struct spi_transfer t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 	int bits, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 	u16 cmd_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 	cmd_addr = OP_START << edev->addrlen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 	if (edev->addrlen == 7) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 		cmd_addr |= ADDR_ERAL << 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 		bits = 10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 		cmd_addr |= ADDR_ERAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 		bits = 9;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 	if (has_quirk_instruction_length(edev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 		cmd_addr <<= 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 		bits += 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 	dev_dbg(&edev->spi->dev, "eral cmd 0x%04x, %d bits\n", cmd_addr, bits);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 	spi_message_init(&m);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 	memset(&t, 0, sizeof(t));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 	t.tx_buf = &cmd_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 	t.len = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 	t.bits_per_word = bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 	spi_message_add_tail(&t, &m);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 	mutex_lock(&edev->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 	if (edev->pdata->prepare)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 		edev->pdata->prepare(edev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 	ret = spi_sync(edev->spi, &m);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 		dev_err(&edev->spi->dev, "erase error %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 	/* have to wait erase cycle time Tec ms */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 	mdelay(6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 	if (pd->finish)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 		pd->finish(edev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 	mutex_unlock(&edev->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) static ssize_t eeprom_93xx46_store_erase(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 					 struct device_attribute *attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 					 const char *buf, size_t count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 	struct eeprom_93xx46_dev *edev = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 	int erase = 0, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 	sscanf(buf, "%d", &erase);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 	if (erase) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 		ret = eeprom_93xx46_ew(edev, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 		if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 			return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 		ret = eeprom_93xx46_eral(edev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 		if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) 			return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 		ret = eeprom_93xx46_ew(edev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 		if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 			return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) 	return count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) static DEVICE_ATTR(erase, S_IWUSR, NULL, eeprom_93xx46_store_erase);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) static void select_assert(void *context)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) 	struct eeprom_93xx46_dev *edev = context;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) 	gpiod_set_value_cansleep(edev->pdata->select, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) static void select_deassert(void *context)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) 	struct eeprom_93xx46_dev *edev = context;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) 	gpiod_set_value_cansleep(edev->pdata->select, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) static const struct of_device_id eeprom_93xx46_of_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) 	{ .compatible = "eeprom-93xx46", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) 	{ .compatible = "atmel,at93c46d", .data = &atmel_at93c46d_data, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) 	{ .compatible = "microchip,93lc46b", .data = &microchip_93lc46b_data, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) 	{}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) MODULE_DEVICE_TABLE(of, eeprom_93xx46_of_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) static int eeprom_93xx46_probe_dt(struct spi_device *spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) 	const struct of_device_id *of_id =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) 		of_match_device(eeprom_93xx46_of_table, &spi->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) 	struct device_node *np = spi->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) 	struct eeprom_93xx46_platform_data *pd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) 	u32 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) 	pd = devm_kzalloc(&spi->dev, sizeof(*pd), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) 	if (!pd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) 	ret = of_property_read_u32(np, "data-size", &tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) 	if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) 		dev_err(&spi->dev, "data-size property not found\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) 	if (tmp == 8) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) 		pd->flags |= EE_ADDR8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) 	} else if (tmp == 16) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) 		pd->flags |= EE_ADDR16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) 		dev_err(&spi->dev, "invalid data-size (%d)\n", tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) 	if (of_property_read_bool(np, "read-only"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) 		pd->flags |= EE_READONLY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) 	pd->select = devm_gpiod_get_optional(&spi->dev, "select",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) 					     GPIOD_OUT_LOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) 	if (IS_ERR(pd->select))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) 		return PTR_ERR(pd->select);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) 	pd->prepare = select_assert;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) 	pd->finish = select_deassert;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) 	gpiod_direction_output(pd->select, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) 	if (of_id->data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) 		const struct eeprom_93xx46_devtype_data *data = of_id->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) 		pd->quirks = data->quirks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) 	spi->dev.platform_data = pd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) static int eeprom_93xx46_probe(struct spi_device *spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) 	struct eeprom_93xx46_platform_data *pd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) 	struct eeprom_93xx46_dev *edev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) 	int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) 	if (spi->dev.of_node) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) 		err = eeprom_93xx46_probe_dt(spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) 		if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) 			return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) 	pd = spi->dev.platform_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) 	if (!pd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) 		dev_err(&spi->dev, "missing platform data\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) 		return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) 	edev = devm_kzalloc(&spi->dev, sizeof(*edev), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) 	if (!edev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) 	if (pd->flags & EE_ADDR8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) 		edev->addrlen = 7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) 	else if (pd->flags & EE_ADDR16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) 		edev->addrlen = 6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) 	else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) 		dev_err(&spi->dev, "unspecified address type\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) 	mutex_init(&edev->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) 	edev->spi = spi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) 	edev->pdata = pd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) 	edev->size = 128;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) 	edev->nvmem_config.type = NVMEM_TYPE_EEPROM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) 	edev->nvmem_config.name = dev_name(&spi->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) 	edev->nvmem_config.dev = &spi->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) 	edev->nvmem_config.read_only = pd->flags & EE_READONLY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) 	edev->nvmem_config.root_only = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) 	edev->nvmem_config.owner = THIS_MODULE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) 	edev->nvmem_config.compat = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) 	edev->nvmem_config.base_dev = &spi->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) 	edev->nvmem_config.reg_read = eeprom_93xx46_read;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) 	edev->nvmem_config.reg_write = eeprom_93xx46_write;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) 	edev->nvmem_config.priv = edev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) 	edev->nvmem_config.stride = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) 	edev->nvmem_config.word_size = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) 	edev->nvmem_config.size = edev->size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) 	edev->nvmem = devm_nvmem_register(&spi->dev, &edev->nvmem_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) 	if (IS_ERR(edev->nvmem))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) 		return PTR_ERR(edev->nvmem);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) 	dev_info(&spi->dev, "%d-bit eeprom %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) 		(pd->flags & EE_ADDR8) ? 8 : 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) 		(pd->flags & EE_READONLY) ? "(readonly)" : "");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) 	if (!(pd->flags & EE_READONLY)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) 		if (device_create_file(&spi->dev, &dev_attr_erase))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) 			dev_err(&spi->dev, "can't create erase interface\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) 	spi_set_drvdata(spi, edev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) static int eeprom_93xx46_remove(struct spi_device *spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) 	struct eeprom_93xx46_dev *edev = spi_get_drvdata(spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) 	if (!(edev->pdata->flags & EE_READONLY))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) 		device_remove_file(&spi->dev, &dev_attr_erase);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) static struct spi_driver eeprom_93xx46_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) 	.driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) 		.name	= "93xx46",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) 		.of_match_table = of_match_ptr(eeprom_93xx46_of_table),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) 	.probe		= eeprom_93xx46_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) 	.remove		= eeprom_93xx46_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) module_spi_driver(eeprom_93xx46_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) MODULE_DESCRIPTION("Driver for 93xx46 EEPROMs");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) MODULE_AUTHOR("Anatolij Gustschin <agust@denx.de>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) MODULE_ALIAS("spi:93xx46");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) MODULE_ALIAS("spi:eeprom-93xx46");