^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * at25.c -- support most SPI EEPROMs, such as Atmel AT25 models
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2006 David Brownell
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/sched.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/nvmem-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/spi/spi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/spi/eeprom.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/property.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) * NOTE: this is an *EEPROM* driver. The vagaries of product naming
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * mean that some AT25 products are EEPROMs, and others are FLASH.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) * Handle FLASH chips with the drivers/mtd/devices/m25p80.c driver,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) * not this one!
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) struct at25_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) struct spi_device *spi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) struct mutex lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) struct spi_eeprom chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) unsigned addrlen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) struct nvmem_config nvmem_config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) struct nvmem_device *nvmem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define AT25_WREN 0x06 /* latch the write enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define AT25_WRDI 0x04 /* reset the write enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define AT25_RDSR 0x05 /* read status register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define AT25_WRSR 0x01 /* write status register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define AT25_READ 0x03 /* read byte(s) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define AT25_WRITE 0x02 /* write byte(s)/sector */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define AT25_SR_nRDY 0x01 /* nRDY = write-in-progress */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define AT25_SR_WEN 0x02 /* write enable (latched) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define AT25_SR_BP0 0x04 /* BP for software writeprotect */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define AT25_SR_BP1 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define AT25_SR_WPEN 0x80 /* writeprotect enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define AT25_INSTR_BIT3 0x08 /* Additional address bit in instr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define EE_MAXADDRLEN 3 /* 24 bit addresses, up to 2 MBytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) /* Specs often allow 5 msec for a page write, sometimes 20 msec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) * it's important to recover from write timeouts.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define EE_TIMEOUT 25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) /*-------------------------------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define io_limit PAGE_SIZE /* bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) static int at25_ee_read(void *priv, unsigned int offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) void *val, size_t count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) struct at25_data *at25 = priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) char *buf = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) u8 command[EE_MAXADDRLEN + 1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) u8 *cp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) ssize_t status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) struct spi_transfer t[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) struct spi_message m;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) u8 instr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) if (unlikely(offset >= at25->chip.byte_len))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) if ((offset + count) > at25->chip.byte_len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) count = at25->chip.byte_len - offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) if (unlikely(!count))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) cp = command;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) instr = AT25_READ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) if (at25->chip.flags & EE_INSTR_BIT3_IS_ADDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) if (offset >= (1U << (at25->addrlen * 8)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) instr |= AT25_INSTR_BIT3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) *cp++ = instr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) /* 8/16/24-bit address is written MSB first */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) switch (at25->addrlen) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) default: /* case 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) *cp++ = offset >> 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) *cp++ = offset >> 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) case 0: /* can't happen: for better codegen */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) *cp++ = offset >> 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) spi_message_init(&m);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) memset(t, 0, sizeof(t));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) t[0].tx_buf = command;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) t[0].len = at25->addrlen + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) spi_message_add_tail(&t[0], &m);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) t[1].rx_buf = buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) t[1].len = count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) spi_message_add_tail(&t[1], &m);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) mutex_lock(&at25->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) /* Read it all at once.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) * REVISIT that's potentially a problem with large chips, if
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) * other devices on the bus need to be accessed regularly or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) * this chip is clocked very slowly
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) status = spi_sync(at25->spi, &m);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) dev_dbg(&at25->spi->dev, "read %zu bytes at %d --> %zd\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) count, offset, status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) mutex_unlock(&at25->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) static int at25_ee_write(void *priv, unsigned int off, void *val, size_t count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) struct at25_data *at25 = priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) const char *buf = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) int status = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) unsigned buf_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) u8 *bounce;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) if (unlikely(off >= at25->chip.byte_len))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) return -EFBIG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) if ((off + count) > at25->chip.byte_len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) count = at25->chip.byte_len - off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) if (unlikely(!count))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) /* Temp buffer starts with command and address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) buf_size = at25->chip.page_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) if (buf_size > io_limit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) buf_size = io_limit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) bounce = kmalloc(buf_size + at25->addrlen + 1, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) if (!bounce)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) /* For write, rollover is within the page ... so we write at
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) * most one page, then manually roll over to the next page.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) mutex_lock(&at25->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) unsigned long timeout, retries;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) unsigned segment;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) unsigned offset = (unsigned) off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) u8 *cp = bounce;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) int sr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) u8 instr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) *cp = AT25_WREN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) status = spi_write(at25->spi, cp, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) if (status < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) dev_dbg(&at25->spi->dev, "WREN --> %d\n", status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) instr = AT25_WRITE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) if (at25->chip.flags & EE_INSTR_BIT3_IS_ADDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) if (offset >= (1U << (at25->addrlen * 8)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) instr |= AT25_INSTR_BIT3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) *cp++ = instr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) /* 8/16/24-bit address is written MSB first */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) switch (at25->addrlen) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) default: /* case 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) *cp++ = offset >> 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) *cp++ = offset >> 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) case 0: /* can't happen: for better codegen */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) *cp++ = offset >> 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) /* Write as much of a page as we can */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) segment = buf_size - (offset % buf_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) if (segment > count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) segment = count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) memcpy(cp, buf, segment);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) status = spi_write(at25->spi, bounce,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) segment + at25->addrlen + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) dev_dbg(&at25->spi->dev, "write %u bytes at %u --> %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) segment, offset, status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) if (status < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) /* REVISIT this should detect (or prevent) failed writes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) * to readonly sections of the EEPROM...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) /* Wait for non-busy status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) timeout = jiffies + msecs_to_jiffies(EE_TIMEOUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) retries = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) sr = spi_w8r8(at25->spi, AT25_RDSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) if (sr < 0 || (sr & AT25_SR_nRDY)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) dev_dbg(&at25->spi->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) "rdsr --> %d (%02x)\n", sr, sr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) /* at HZ=100, this is sloooow */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) msleep(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) if (!(sr & AT25_SR_nRDY))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) } while (retries++ < 3 || time_before_eq(jiffies, timeout));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) if ((sr < 0) || (sr & AT25_SR_nRDY)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) dev_err(&at25->spi->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) "write %u bytes offset %u, timeout after %u msecs\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) segment, offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) jiffies_to_msecs(jiffies -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) (timeout - EE_TIMEOUT)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) status = -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) off += segment;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) buf += segment;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) count -= segment;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) } while (count > 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) mutex_unlock(&at25->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) kfree(bounce);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) /*-------------------------------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) static int at25_fw_to_chip(struct device *dev, struct spi_eeprom *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) memset(chip, 0, sizeof(*chip));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) strncpy(chip->name, "at25", sizeof(chip->name));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) if (device_property_read_u32(dev, "size", &val) == 0 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) device_property_read_u32(dev, "at25,byte-len", &val) == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) chip->byte_len = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) dev_err(dev, "Error: missing \"size\" property\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) if (device_property_read_u32(dev, "pagesize", &val) == 0 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) device_property_read_u32(dev, "at25,page-size", &val) == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) chip->page_size = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) dev_err(dev, "Error: missing \"pagesize\" property\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) if (device_property_read_u32(dev, "at25,addr-mode", &val) == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) chip->flags = (u16)val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) if (device_property_read_u32(dev, "address-width", &val)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) dev_err(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) "Error: missing \"address-width\" property\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) switch (val) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) case 9:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) chip->flags |= EE_INSTR_BIT3_IS_ADDR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) case 8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) chip->flags |= EE_ADDR1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) case 16:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) chip->flags |= EE_ADDR2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) case 24:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) chip->flags |= EE_ADDR3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) dev_err(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) "Error: bad \"address-width\" property: %u\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) if (device_property_present(dev, "read-only"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) chip->flags |= EE_READONLY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) static int at25_probe(struct spi_device *spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) struct at25_data *at25 = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) struct spi_eeprom chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) int sr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) int addrlen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) /* Chip description */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) if (!spi->dev.platform_data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) err = at25_fw_to_chip(&spi->dev, &chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) chip = *(struct spi_eeprom *)spi->dev.platform_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) /* For now we only support 8/16/24 bit addressing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) if (chip.flags & EE_ADDR1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) addrlen = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) else if (chip.flags & EE_ADDR2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) addrlen = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) else if (chip.flags & EE_ADDR3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) addrlen = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) dev_dbg(&spi->dev, "unsupported address type\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) /* Ping the chip ... the status register is pretty portable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) * unlike probing manufacturer IDs. We do expect that system
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) * firmware didn't write it in the past few milliseconds!
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) sr = spi_w8r8(spi, AT25_RDSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) if (sr < 0 || sr & AT25_SR_nRDY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) dev_dbg(&spi->dev, "rdsr --> %d (%02x)\n", sr, sr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) return -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) at25 = devm_kzalloc(&spi->dev, sizeof(struct at25_data), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) if (!at25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) mutex_init(&at25->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) at25->chip = chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) at25->spi = spi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) spi_set_drvdata(spi, at25);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) at25->addrlen = addrlen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) at25->nvmem_config.type = NVMEM_TYPE_EEPROM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) at25->nvmem_config.name = dev_name(&spi->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) at25->nvmem_config.dev = &spi->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) at25->nvmem_config.read_only = chip.flags & EE_READONLY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) at25->nvmem_config.root_only = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) at25->nvmem_config.owner = THIS_MODULE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) at25->nvmem_config.compat = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) at25->nvmem_config.base_dev = &spi->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) at25->nvmem_config.reg_read = at25_ee_read;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) at25->nvmem_config.reg_write = at25_ee_write;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) at25->nvmem_config.priv = at25;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) at25->nvmem_config.stride = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) at25->nvmem_config.word_size = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) at25->nvmem_config.size = chip.byte_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) at25->nvmem = devm_nvmem_register(&spi->dev, &at25->nvmem_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) if (IS_ERR(at25->nvmem))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) return PTR_ERR(at25->nvmem);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) dev_info(&spi->dev, "%d %s %s eeprom%s, pagesize %u\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) (chip.byte_len < 1024) ? chip.byte_len : (chip.byte_len / 1024),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) (chip.byte_len < 1024) ? "Byte" : "KByte",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) at25->chip.name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) (chip.flags & EE_READONLY) ? " (readonly)" : "",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) at25->chip.page_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) /*-------------------------------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) static const struct of_device_id at25_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) { .compatible = "atmel,at25", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) MODULE_DEVICE_TABLE(of, at25_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) static struct spi_driver at25_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) .name = "at25",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) .of_match_table = at25_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) .probe = at25_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) module_spi_driver(at25_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) MODULE_DESCRIPTION("Driver for most SPI EEPROMs");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) MODULE_AUTHOR("David Brownell");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) MODULE_ALIAS("spi:at25");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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