^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * at24.c - handle most I2C EEPROMs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2005-2007 David Brownell
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) 2008 Wolfram Sang, Pengutronix
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/acpi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/bitops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/capability.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/jiffies.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/mod_devicetable.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/mutex.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/nvmem-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/pm_runtime.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/property.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/regulator/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) /* Address pointer is 16 bit. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define AT24_FLAG_ADDR16 BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) /* sysfs-entry will be read-only. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define AT24_FLAG_READONLY BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) /* sysfs-entry will be world-readable. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define AT24_FLAG_IRUGO BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) /* Take always 8 addresses (24c00). */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define AT24_FLAG_TAKE8ADDR BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) /* Factory-programmed serial number. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define AT24_FLAG_SERIAL BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) /* Factory-programmed mac address. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define AT24_FLAG_MAC BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) /* Does not auto-rollover reads to the next slave address. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define AT24_FLAG_NO_RDROL BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) * I2C EEPROMs from most vendors are inexpensive and mostly interchangeable.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) * Differences between different vendor product lines (like Atmel AT24C or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) * MicroChip 24LC, etc) won't much matter for typical read/write access.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) * There are also I2C RAM chips, likewise interchangeable. One example
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) * would be the PCF8570, which acts like a 24c02 EEPROM (256 bytes).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) * However, misconfiguration can lose data. "Set 16-bit memory address"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) * to a part with 8-bit addressing will overwrite data. Writing with too
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) * big a page size also loses data. And it's not safe to assume that the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) * conventional addresses 0x50..0x57 only hold eeproms; a PCF8563 RTC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) * uses 0x51, for just one example.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) * Accordingly, explicit board-specific configuration data should be used
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) * in almost all cases. (One partial exception is an SMBus used to access
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) * "SPD" data for DRAM sticks. Those only use 24c02 EEPROMs.)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) * So this driver uses "new style" I2C driver binding, expecting to be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) * told what devices exist. That may be in arch/X/mach-Y/board-Z.c or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) * similar kernel-resident tables; or, configuration data coming from
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) * a bootloader.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) * Other than binding model, current differences from "eeprom" driver are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) * that this one handles write access and isn't restricted to 24c02 devices.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) * It also handles larger devices (32 kbit and up) with two-byte addresses,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) * which won't work on pure SMBus systems.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) struct at24_client {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) struct i2c_client *client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) struct at24_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) * Lock protects against activities from other Linux tasks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) * but not from changes by other I2C masters.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) struct mutex lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) unsigned int write_max;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) unsigned int num_addresses;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) unsigned int offset_adj;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) u32 byte_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) u16 page_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) u8 flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) struct nvmem_device *nvmem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) struct regulator *vcc_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) void (*read_post)(unsigned int off, char *buf, size_t count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) * Some chips tie up multiple I2C addresses; dummy devices reserve
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) * them for us, and we'll use them with SMBus calls.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) struct at24_client client[];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) * This parameter is to help this driver avoid blocking other drivers out
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) * of I2C for potentially troublesome amounts of time. With a 100 kHz I2C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) * clock, one 256 byte read takes about 1/43 second which is excessive;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) * but the 1/170 second it takes at 400 kHz may be quite reasonable; and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) * at 1 MHz (Fm+) a 1/430 second delay could easily be invisible.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) * This value is forced to be a power of two so that writes align on pages.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) static unsigned int at24_io_limit = 128;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) module_param_named(io_limit, at24_io_limit, uint, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) MODULE_PARM_DESC(at24_io_limit, "Maximum bytes per I/O (default 128)");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) * Specs often allow 5 msec for a page write, sometimes 20 msec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) * it's important to recover from write timeouts.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) static unsigned int at24_write_timeout = 25;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) module_param_named(write_timeout, at24_write_timeout, uint, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) MODULE_PARM_DESC(at24_write_timeout, "Time (in ms) to try writes (default 25)");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) struct at24_chip_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) u32 byte_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) u8 flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) void (*read_post)(unsigned int off, char *buf, size_t count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define AT24_CHIP_DATA(_name, _len, _flags) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) static const struct at24_chip_data _name = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) .byte_len = _len, .flags = _flags, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define AT24_CHIP_DATA_CB(_name, _len, _flags, _read_post) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) static const struct at24_chip_data _name = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) .byte_len = _len, .flags = _flags, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) .read_post = _read_post, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) static void at24_read_post_vaio(unsigned int off, char *buf, size_t count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) if (capable(CAP_SYS_ADMIN))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) * Hide VAIO private settings to regular users:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) * - BIOS passwords: bytes 0x00 to 0x0f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) * - UUID: bytes 0x10 to 0x1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) * - Serial number: 0xc0 to 0xdf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) for (i = 0; i < count; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) if ((off + i <= 0x1f) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) (off + i >= 0xc0 && off + i <= 0xdf))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) buf[i] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) /* needs 8 addresses as A0-A2 are ignored */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) AT24_CHIP_DATA(at24_data_24c00, 128 / 8, AT24_FLAG_TAKE8ADDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) /* old variants can't be handled with this generic entry! */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) AT24_CHIP_DATA(at24_data_24c01, 1024 / 8, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) AT24_CHIP_DATA(at24_data_24cs01, 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) AT24_FLAG_SERIAL | AT24_FLAG_READONLY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) AT24_CHIP_DATA(at24_data_24c02, 2048 / 8, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) AT24_CHIP_DATA(at24_data_24cs02, 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) AT24_FLAG_SERIAL | AT24_FLAG_READONLY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) AT24_CHIP_DATA(at24_data_24mac402, 48 / 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) AT24_FLAG_MAC | AT24_FLAG_READONLY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) AT24_CHIP_DATA(at24_data_24mac602, 64 / 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) AT24_FLAG_MAC | AT24_FLAG_READONLY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) /* spd is a 24c02 in memory DIMMs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) AT24_CHIP_DATA(at24_data_spd, 2048 / 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) AT24_FLAG_READONLY | AT24_FLAG_IRUGO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) /* 24c02_vaio is a 24c02 on some Sony laptops */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) AT24_CHIP_DATA_CB(at24_data_24c02_vaio, 2048 / 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) AT24_FLAG_READONLY | AT24_FLAG_IRUGO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) at24_read_post_vaio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) AT24_CHIP_DATA(at24_data_24c04, 4096 / 8, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) AT24_CHIP_DATA(at24_data_24cs04, 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) AT24_FLAG_SERIAL | AT24_FLAG_READONLY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) /* 24rf08 quirk is handled at i2c-core */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) AT24_CHIP_DATA(at24_data_24c08, 8192 / 8, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) AT24_CHIP_DATA(at24_data_24cs08, 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) AT24_FLAG_SERIAL | AT24_FLAG_READONLY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) AT24_CHIP_DATA(at24_data_24c16, 16384 / 8, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) AT24_CHIP_DATA(at24_data_24cs16, 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) AT24_FLAG_SERIAL | AT24_FLAG_READONLY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) AT24_CHIP_DATA(at24_data_24c32, 32768 / 8, AT24_FLAG_ADDR16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) AT24_CHIP_DATA(at24_data_24cs32, 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) AT24_FLAG_ADDR16 | AT24_FLAG_SERIAL | AT24_FLAG_READONLY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) AT24_CHIP_DATA(at24_data_24c64, 65536 / 8, AT24_FLAG_ADDR16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) AT24_CHIP_DATA(at24_data_24cs64, 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) AT24_FLAG_ADDR16 | AT24_FLAG_SERIAL | AT24_FLAG_READONLY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) AT24_CHIP_DATA(at24_data_24c128, 131072 / 8, AT24_FLAG_ADDR16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) AT24_CHIP_DATA(at24_data_24c256, 262144 / 8, AT24_FLAG_ADDR16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) AT24_CHIP_DATA(at24_data_24c512, 524288 / 8, AT24_FLAG_ADDR16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) AT24_CHIP_DATA(at24_data_24c1024, 1048576 / 8, AT24_FLAG_ADDR16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) AT24_CHIP_DATA(at24_data_24c2048, 2097152 / 8, AT24_FLAG_ADDR16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) /* identical to 24c08 ? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) AT24_CHIP_DATA(at24_data_INT3499, 8192 / 8, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) static const struct i2c_device_id at24_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) { "24c00", (kernel_ulong_t)&at24_data_24c00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) { "24c01", (kernel_ulong_t)&at24_data_24c01 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) { "24cs01", (kernel_ulong_t)&at24_data_24cs01 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) { "24c02", (kernel_ulong_t)&at24_data_24c02 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) { "24cs02", (kernel_ulong_t)&at24_data_24cs02 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) { "24mac402", (kernel_ulong_t)&at24_data_24mac402 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) { "24mac602", (kernel_ulong_t)&at24_data_24mac602 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) { "spd", (kernel_ulong_t)&at24_data_spd },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) { "24c02-vaio", (kernel_ulong_t)&at24_data_24c02_vaio },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) { "24c04", (kernel_ulong_t)&at24_data_24c04 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) { "24cs04", (kernel_ulong_t)&at24_data_24cs04 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) { "24c08", (kernel_ulong_t)&at24_data_24c08 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) { "24cs08", (kernel_ulong_t)&at24_data_24cs08 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) { "24c16", (kernel_ulong_t)&at24_data_24c16 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) { "24cs16", (kernel_ulong_t)&at24_data_24cs16 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) { "24c32", (kernel_ulong_t)&at24_data_24c32 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) { "24cs32", (kernel_ulong_t)&at24_data_24cs32 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) { "24c64", (kernel_ulong_t)&at24_data_24c64 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) { "24cs64", (kernel_ulong_t)&at24_data_24cs64 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) { "24c128", (kernel_ulong_t)&at24_data_24c128 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) { "24c256", (kernel_ulong_t)&at24_data_24c256 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) { "24c512", (kernel_ulong_t)&at24_data_24c512 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) { "24c1024", (kernel_ulong_t)&at24_data_24c1024 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) { "24c2048", (kernel_ulong_t)&at24_data_24c2048 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) { "at24", 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) { /* END OF LIST */ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) MODULE_DEVICE_TABLE(i2c, at24_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) static const struct of_device_id at24_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) { .compatible = "atmel,24c00", .data = &at24_data_24c00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) { .compatible = "atmel,24c01", .data = &at24_data_24c01 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) { .compatible = "atmel,24cs01", .data = &at24_data_24cs01 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) { .compatible = "atmel,24c02", .data = &at24_data_24c02 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) { .compatible = "atmel,24cs02", .data = &at24_data_24cs02 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) { .compatible = "atmel,24mac402", .data = &at24_data_24mac402 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) { .compatible = "atmel,24mac602", .data = &at24_data_24mac602 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) { .compatible = "atmel,spd", .data = &at24_data_spd },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) { .compatible = "atmel,24c04", .data = &at24_data_24c04 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) { .compatible = "atmel,24cs04", .data = &at24_data_24cs04 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) { .compatible = "atmel,24c08", .data = &at24_data_24c08 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) { .compatible = "atmel,24cs08", .data = &at24_data_24cs08 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) { .compatible = "atmel,24c16", .data = &at24_data_24c16 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) { .compatible = "atmel,24cs16", .data = &at24_data_24cs16 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) { .compatible = "atmel,24c32", .data = &at24_data_24c32 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) { .compatible = "atmel,24cs32", .data = &at24_data_24cs32 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) { .compatible = "atmel,24c64", .data = &at24_data_24c64 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) { .compatible = "atmel,24cs64", .data = &at24_data_24cs64 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) { .compatible = "atmel,24c128", .data = &at24_data_24c128 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) { .compatible = "atmel,24c256", .data = &at24_data_24c256 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) { .compatible = "atmel,24c512", .data = &at24_data_24c512 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) { .compatible = "atmel,24c1024", .data = &at24_data_24c1024 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) { .compatible = "atmel,24c2048", .data = &at24_data_24c2048 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) { /* END OF LIST */ },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) MODULE_DEVICE_TABLE(of, at24_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) static const struct acpi_device_id __maybe_unused at24_acpi_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) { "INT3499", (kernel_ulong_t)&at24_data_INT3499 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) { "TPF0001", (kernel_ulong_t)&at24_data_24c1024 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) { /* END OF LIST */ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) MODULE_DEVICE_TABLE(acpi, at24_acpi_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) * This routine supports chips which consume multiple I2C addresses. It
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) * computes the addressing information to be used for a given r/w request.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) * Assumes that sanity checks for offset happened at sysfs-layer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) * Slave address and byte offset derive from the offset. Always
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) * set the byte address; on a multi-master board, another master
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) * may have changed the chip's "current" address pointer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) static struct at24_client *at24_translate_offset(struct at24_data *at24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) unsigned int *offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) if (at24->flags & AT24_FLAG_ADDR16) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) i = *offset >> 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) *offset &= 0xffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) i = *offset >> 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) *offset &= 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) return &at24->client[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) static struct device *at24_base_client_dev(struct at24_data *at24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) return &at24->client[0].client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) static size_t at24_adjust_read_count(struct at24_data *at24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) unsigned int offset, size_t count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) unsigned int bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) size_t remainder;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) * In case of multi-address chips that don't rollover reads to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) * the next slave address: truncate the count to the slave boundary,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) * so that the read never straddles slaves.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) if (at24->flags & AT24_FLAG_NO_RDROL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) bits = (at24->flags & AT24_FLAG_ADDR16) ? 16 : 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) remainder = BIT(bits) - offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) if (count > remainder)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) count = remainder;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) if (count > at24_io_limit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) count = at24_io_limit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) return count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) static ssize_t at24_regmap_read(struct at24_data *at24, char *buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) unsigned int offset, size_t count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) unsigned long timeout, read_time;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) struct at24_client *at24_client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) struct i2c_client *client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) at24_client = at24_translate_offset(at24, &offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) regmap = at24_client->regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) client = at24_client->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) count = at24_adjust_read_count(at24, offset, count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) /* adjust offset for mac and serial read ops */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) offset += at24->offset_adj;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) timeout = jiffies + msecs_to_jiffies(at24_write_timeout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) * The timestamp shall be taken before the actual operation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) * to avoid a premature timeout in case of high CPU load.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) read_time = jiffies;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) ret = regmap_bulk_read(regmap, offset, buf, count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) dev_dbg(&client->dev, "read %zu@%d --> %d (%ld)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) count, offset, ret, jiffies);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) return count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) usleep_range(1000, 1500);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) } while (time_before(read_time, timeout));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) * Note that if the hardware write-protect pin is pulled high, the whole
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) * chip is normally write protected. But there are plenty of product
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) * variants here, including OTP fuses and partial chip protect.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) * We only use page mode writes; the alternative is sloooow. These routines
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) * write at most one page.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) static size_t at24_adjust_write_count(struct at24_data *at24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) unsigned int offset, size_t count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) unsigned int next_page;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) /* write_max is at most a page */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) if (count > at24->write_max)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) count = at24->write_max;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) /* Never roll over backwards, to the start of this page */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) next_page = roundup(offset + 1, at24->page_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) if (offset + count > next_page)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) count = next_page - offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) return count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) static ssize_t at24_regmap_write(struct at24_data *at24, const char *buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) unsigned int offset, size_t count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) unsigned long timeout, write_time;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) struct at24_client *at24_client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) struct i2c_client *client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) at24_client = at24_translate_offset(at24, &offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) regmap = at24_client->regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) client = at24_client->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) count = at24_adjust_write_count(at24, offset, count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) timeout = jiffies + msecs_to_jiffies(at24_write_timeout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) * The timestamp shall be taken before the actual operation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) * to avoid a premature timeout in case of high CPU load.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) write_time = jiffies;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) ret = regmap_bulk_write(regmap, offset, buf, count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) dev_dbg(&client->dev, "write %zu@%d --> %d (%ld)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) count, offset, ret, jiffies);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) return count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) usleep_range(1000, 1500);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) } while (time_before(write_time, timeout));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) static int at24_read(void *priv, unsigned int off, void *val, size_t count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) struct at24_data *at24;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) char *buf = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) int i, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) at24 = priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) dev = at24_base_client_dev(at24);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) if (unlikely(!count))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) return count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) if (off + count > at24->byte_len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) ret = pm_runtime_get_sync(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) pm_runtime_put_noidle(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) * Read data from chip, protecting against concurrent updates
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) * from this host, but not from other I2C masters.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) mutex_lock(&at24->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) for (i = 0; count; i += ret, count -= ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) ret = at24_regmap_read(at24, buf + i, off + i, count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) mutex_unlock(&at24->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) pm_runtime_put(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) mutex_unlock(&at24->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) pm_runtime_put(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) if (unlikely(at24->read_post))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) at24->read_post(off, buf, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) static int at24_write(void *priv, unsigned int off, void *val, size_t count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) struct at24_data *at24;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) char *buf = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) at24 = priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) dev = at24_base_client_dev(at24);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) if (unlikely(!count))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) if (off + count > at24->byte_len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) ret = pm_runtime_get_sync(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) pm_runtime_put_noidle(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) * Write data to chip, protecting against concurrent updates
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) * from this host, but not from other I2C masters.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) mutex_lock(&at24->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) while (count) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) ret = at24_regmap_write(at24, buf, off, count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) mutex_unlock(&at24->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) pm_runtime_put(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) buf += ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) off += ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) count -= ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) mutex_unlock(&at24->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) pm_runtime_put(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) static const struct at24_chip_data *at24_get_chip_data(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) struct device_node *of_node = dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) const struct at24_chip_data *cdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) const struct i2c_device_id *id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) id = i2c_match_id(at24_ids, to_i2c_client(dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) * The I2C core allows OF nodes compatibles to match against the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) * I2C device ID table as a fallback, so check not only if an OF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) * node is present but also if it matches an OF device ID entry.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) if (of_node && of_match_device(at24_of_match, dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) cdata = of_device_get_match_data(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) else if (id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) cdata = (void *)id->driver_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) cdata = acpi_device_get_match_data(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) if (!cdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) return ERR_PTR(-ENODEV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) return cdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) static int at24_make_dummy_client(struct at24_data *at24, unsigned int index,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) struct regmap_config *regmap_config)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) struct i2c_client *base_client, *dummy_client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) base_client = at24->client[0].client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) dev = &base_client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) dummy_client = devm_i2c_new_dummy_device(dev, base_client->adapter,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) base_client->addr + index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) if (IS_ERR(dummy_client))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) return PTR_ERR(dummy_client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) regmap = devm_regmap_init_i2c(dummy_client, regmap_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) if (IS_ERR(regmap))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) return PTR_ERR(regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) at24->client[index].client = dummy_client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) at24->client[index].regmap = regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) static unsigned int at24_get_offset_adj(u8 flags, unsigned int byte_len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) if (flags & AT24_FLAG_MAC) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) /* EUI-48 starts from 0x9a, EUI-64 from 0x98 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) return 0xa0 - byte_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) } else if (flags & AT24_FLAG_SERIAL && flags & AT24_FLAG_ADDR16) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) * For 16 bit address pointers, the word address must contain
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) * a '10' sequence in bits 11 and 10 regardless of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) * intended position of the address pointer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) return 0x0800;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) } else if (flags & AT24_FLAG_SERIAL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) * Otherwise the word address must begin with a '10' sequence,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) * regardless of the intended address.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) return 0x0080;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) static int at24_probe(struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) struct regmap_config regmap_config = { };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) struct nvmem_config nvmem_config = { };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) u32 byte_len, page_size, flags, addrw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) const struct at24_chip_data *cdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) struct device *dev = &client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) bool i2c_fn_i2c, i2c_fn_block;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) unsigned int i, num_addresses;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) struct at24_data *at24;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) bool writable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) u8 test_byte;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) i2c_fn_i2c = i2c_check_functionality(client->adapter, I2C_FUNC_I2C);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) i2c_fn_block = i2c_check_functionality(client->adapter,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) I2C_FUNC_SMBUS_WRITE_I2C_BLOCK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) cdata = at24_get_chip_data(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) if (IS_ERR(cdata))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) return PTR_ERR(cdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) err = device_property_read_u32(dev, "pagesize", &page_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) * This is slow, but we can't know all eeproms, so we better
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) * play safe. Specifying custom eeprom-types via device tree
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) * or properties is recommended anyhow.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) page_size = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) flags = cdata->flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) if (device_property_present(dev, "read-only"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) flags |= AT24_FLAG_READONLY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) if (device_property_present(dev, "no-read-rollover"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) flags |= AT24_FLAG_NO_RDROL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) err = device_property_read_u32(dev, "address-width", &addrw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) if (!err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) switch (addrw) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) case 8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) if (flags & AT24_FLAG_ADDR16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) dev_warn(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) "Override address width to be 8, while default is 16\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) flags &= ~AT24_FLAG_ADDR16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) case 16:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) flags |= AT24_FLAG_ADDR16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) dev_warn(dev, "Bad \"address-width\" property: %u\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) addrw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) err = device_property_read_u32(dev, "size", &byte_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) byte_len = cdata->byte_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) if (!i2c_fn_i2c && !i2c_fn_block)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) page_size = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) if (!page_size) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) dev_err(dev, "page_size must not be 0!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) if (!is_power_of_2(page_size))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) dev_warn(dev, "page_size looks suspicious (no power of 2)!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) err = device_property_read_u32(dev, "num-addresses", &num_addresses);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) if (flags & AT24_FLAG_TAKE8ADDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) num_addresses = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) num_addresses = DIV_ROUND_UP(byte_len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) (flags & AT24_FLAG_ADDR16) ? 65536 : 256);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) if ((flags & AT24_FLAG_SERIAL) && (flags & AT24_FLAG_MAC)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) dev_err(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) "invalid device data - cannot have both AT24_FLAG_SERIAL & AT24_FLAG_MAC.");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) regmap_config.val_bits = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) regmap_config.reg_bits = (flags & AT24_FLAG_ADDR16) ? 16 : 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) regmap_config.disable_locking = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) regmap = devm_regmap_init_i2c(client, ®map_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) if (IS_ERR(regmap))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) return PTR_ERR(regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) at24 = devm_kzalloc(dev, struct_size(at24, client, num_addresses),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) if (!at24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) mutex_init(&at24->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) at24->byte_len = byte_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) at24->page_size = page_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) at24->flags = flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) at24->read_post = cdata->read_post;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) at24->num_addresses = num_addresses;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) at24->offset_adj = at24_get_offset_adj(flags, byte_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) at24->client[0].client = client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) at24->client[0].regmap = regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) at24->vcc_reg = devm_regulator_get(dev, "vcc");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) if (IS_ERR(at24->vcc_reg))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) return PTR_ERR(at24->vcc_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) writable = !(flags & AT24_FLAG_READONLY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) if (writable) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) at24->write_max = min_t(unsigned int,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) page_size, at24_io_limit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) if (!i2c_fn_i2c && at24->write_max > I2C_SMBUS_BLOCK_MAX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) at24->write_max = I2C_SMBUS_BLOCK_MAX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) /* use dummy devices for multiple-address chips */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) for (i = 1; i < num_addresses; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) err = at24_make_dummy_client(at24, i, ®map_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) * We initialize nvmem_config.id to NVMEM_DEVID_AUTO even if the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) * label property is set as some platform can have multiple eeproms
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) * with same label and we can not register each of those with same
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) * label. Failing to register those eeproms trigger cascade failure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) * on such platform.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) nvmem_config.id = NVMEM_DEVID_AUTO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) if (device_property_present(dev, "label")) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) err = device_property_read_string(dev, "label",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) &nvmem_config.name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) nvmem_config.name = dev_name(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) nvmem_config.type = NVMEM_TYPE_EEPROM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) nvmem_config.dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) nvmem_config.read_only = !writable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) nvmem_config.root_only = !(flags & AT24_FLAG_IRUGO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) nvmem_config.owner = THIS_MODULE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) nvmem_config.compat = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) nvmem_config.base_dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) nvmem_config.reg_read = at24_read;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) nvmem_config.reg_write = at24_write;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) nvmem_config.priv = at24;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) nvmem_config.stride = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) nvmem_config.word_size = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) nvmem_config.size = byte_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) i2c_set_clientdata(client, at24);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) err = regulator_enable(at24->vcc_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) dev_err(dev, "Failed to enable vcc regulator\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) /* enable runtime pm */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) pm_runtime_set_active(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) pm_runtime_enable(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) at24->nvmem = devm_nvmem_register(dev, &nvmem_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) if (IS_ERR(at24->nvmem)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) pm_runtime_disable(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) if (!pm_runtime_status_suspended(dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) regulator_disable(at24->vcc_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) return PTR_ERR(at24->nvmem);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) * Perform a one-byte test read to verify that the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) * chip is functional.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) err = at24_read(at24, 0, &test_byte, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) pm_runtime_disable(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) if (!pm_runtime_status_suspended(dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) regulator_disable(at24->vcc_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) pm_runtime_idle(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) if (writable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) dev_info(dev, "%u byte %s EEPROM, writable, %u bytes/write\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) byte_len, client->name, at24->write_max);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) dev_info(dev, "%u byte %s EEPROM, read-only\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) byte_len, client->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) static int at24_remove(struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) struct at24_data *at24 = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) pm_runtime_disable(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) if (!pm_runtime_status_suspended(&client->dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) regulator_disable(at24->vcc_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) pm_runtime_set_suspended(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) static int __maybe_unused at24_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) struct i2c_client *client = to_i2c_client(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) struct at24_data *at24 = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) return regulator_disable(at24->vcc_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) static int __maybe_unused at24_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) struct i2c_client *client = to_i2c_client(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) struct at24_data *at24 = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) return regulator_enable(at24->vcc_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) static const struct dev_pm_ops at24_pm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) pm_runtime_force_resume)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) SET_RUNTIME_PM_OPS(at24_suspend, at24_resume, NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) static struct i2c_driver at24_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) .name = "at24",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) .pm = &at24_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) .of_match_table = at24_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) .acpi_match_table = ACPI_PTR(at24_acpi_ids),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) .probe_new = at24_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) .remove = at24_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) .id_table = at24_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) static int __init at24_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) if (!at24_io_limit) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) pr_err("at24: at24_io_limit must not be 0!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) at24_io_limit = rounddown_pow_of_two(at24_io_limit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) return i2c_add_driver(&at24_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) module_init(at24_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) static void __exit at24_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) i2c_del_driver(&at24_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) module_exit(at24_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) MODULE_DESCRIPTION("Driver for most I2C EEPROMs");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) MODULE_AUTHOR("David Brownell and Wolfram Sang");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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