^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright 2014 IBM Corp.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <linux/pci_regs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/pci_ids.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/sort.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <asm/opal.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <asm/msi_bitmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <asm/pnv-pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <asm/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <asm/reg.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include "cxl.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <misc/cxl.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define CXL_PCI_VSEC_ID 0x1280
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define CXL_VSEC_MIN_SIZE 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define CXL_READ_VSEC_LENGTH(dev, vsec, dest) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) pci_read_config_word(dev, vsec + 0x6, dest); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) *dest >>= 4; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define CXL_READ_VSEC_NAFUS(dev, vsec, dest) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) pci_read_config_byte(dev, vsec + 0x8, dest)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define CXL_READ_VSEC_STATUS(dev, vsec, dest) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) pci_read_config_byte(dev, vsec + 0x9, dest)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define CXL_STATUS_SECOND_PORT 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define CXL_STATUS_MSI_X_FULL 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define CXL_STATUS_MSI_X_SINGLE 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define CXL_STATUS_FLASH_RW 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define CXL_STATUS_FLASH_RO 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define CXL_STATUS_LOADABLE_AFU 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define CXL_STATUS_LOADABLE_PSL 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) /* If we see these features we won't try to use the card */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define CXL_UNSUPPORTED_FEATURES \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) (CXL_STATUS_MSI_X_FULL | CXL_STATUS_MSI_X_SINGLE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define CXL_READ_VSEC_MODE_CONTROL(dev, vsec, dest) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) pci_read_config_byte(dev, vsec + 0xa, dest)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define CXL_WRITE_VSEC_MODE_CONTROL(dev, vsec, val) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) pci_write_config_byte(dev, vsec + 0xa, val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define CXL_VSEC_PROTOCOL_MASK 0xe0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define CXL_VSEC_PROTOCOL_1024TB 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define CXL_VSEC_PROTOCOL_512TB 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define CXL_VSEC_PROTOCOL_256TB 0x20 /* Power 8/9 uses this */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define CXL_VSEC_PROTOCOL_ENABLE 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define CXL_READ_VSEC_PSL_REVISION(dev, vsec, dest) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) pci_read_config_word(dev, vsec + 0xc, dest)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define CXL_READ_VSEC_CAIA_MINOR(dev, vsec, dest) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) pci_read_config_byte(dev, vsec + 0xe, dest)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define CXL_READ_VSEC_CAIA_MAJOR(dev, vsec, dest) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) pci_read_config_byte(dev, vsec + 0xf, dest)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define CXL_READ_VSEC_BASE_IMAGE(dev, vsec, dest) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) pci_read_config_word(dev, vsec + 0x10, dest)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define CXL_READ_VSEC_IMAGE_STATE(dev, vsec, dest) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) pci_read_config_byte(dev, vsec + 0x13, dest)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define CXL_WRITE_VSEC_IMAGE_STATE(dev, vsec, val) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) pci_write_config_byte(dev, vsec + 0x13, val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define CXL_VSEC_USER_IMAGE_LOADED 0x80 /* RO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define CXL_VSEC_PERST_LOADS_IMAGE 0x20 /* RW */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define CXL_VSEC_PERST_SELECT_USER 0x10 /* RW */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define CXL_READ_VSEC_AFU_DESC_OFF(dev, vsec, dest) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) pci_read_config_dword(dev, vsec + 0x20, dest)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define CXL_READ_VSEC_AFU_DESC_SIZE(dev, vsec, dest) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) pci_read_config_dword(dev, vsec + 0x24, dest)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define CXL_READ_VSEC_PS_OFF(dev, vsec, dest) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) pci_read_config_dword(dev, vsec + 0x28, dest)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define CXL_READ_VSEC_PS_SIZE(dev, vsec, dest) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) pci_read_config_dword(dev, vsec + 0x2c, dest)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) /* This works a little different than the p1/p2 register accesses to make it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) * easier to pull out individual fields */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define AFUD_READ(afu, off) in_be64(afu->native->afu_desc_mmio + off)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define AFUD_READ_LE(afu, off) in_le64(afu->native->afu_desc_mmio + off)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define EXTRACT_PPC_BIT(val, bit) (!!(val & PPC_BIT(bit)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define EXTRACT_PPC_BITS(val, bs, be) ((val & PPC_BITMASK(bs, be)) >> PPC_BITLSHIFT(be))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define AFUD_READ_INFO(afu) AFUD_READ(afu, 0x0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define AFUD_NUM_INTS_PER_PROC(val) EXTRACT_PPC_BITS(val, 0, 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define AFUD_NUM_PROCS(val) EXTRACT_PPC_BITS(val, 16, 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define AFUD_NUM_CRS(val) EXTRACT_PPC_BITS(val, 32, 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define AFUD_MULTIMODE(val) EXTRACT_PPC_BIT(val, 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define AFUD_PUSH_BLOCK_TRANSFER(val) EXTRACT_PPC_BIT(val, 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define AFUD_DEDICATED_PROCESS(val) EXTRACT_PPC_BIT(val, 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define AFUD_AFU_DIRECTED(val) EXTRACT_PPC_BIT(val, 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define AFUD_TIME_SLICED(val) EXTRACT_PPC_BIT(val, 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define AFUD_READ_CR(afu) AFUD_READ(afu, 0x20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define AFUD_CR_LEN(val) EXTRACT_PPC_BITS(val, 8, 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define AFUD_READ_CR_OFF(afu) AFUD_READ(afu, 0x28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define AFUD_READ_PPPSA(afu) AFUD_READ(afu, 0x30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define AFUD_PPPSA_PP(val) EXTRACT_PPC_BIT(val, 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define AFUD_PPPSA_PSA(val) EXTRACT_PPC_BIT(val, 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define AFUD_PPPSA_LEN(val) EXTRACT_PPC_BITS(val, 8, 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define AFUD_READ_PPPSA_OFF(afu) AFUD_READ(afu, 0x38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define AFUD_READ_EB(afu) AFUD_READ(afu, 0x40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define AFUD_EB_LEN(val) EXTRACT_PPC_BITS(val, 8, 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define AFUD_READ_EB_OFF(afu) AFUD_READ(afu, 0x48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) static const struct pci_device_id cxl_pci_tbl[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) { PCI_DEVICE(PCI_VENDOR_ID_IBM, 0x0477), },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) { PCI_DEVICE(PCI_VENDOR_ID_IBM, 0x044b), },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) { PCI_DEVICE(PCI_VENDOR_ID_IBM, 0x04cf), },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) { PCI_DEVICE(PCI_VENDOR_ID_IBM, 0x0601), },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) { PCI_DEVICE(PCI_VENDOR_ID_IBM, 0x0623), },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) { PCI_DEVICE(PCI_VENDOR_ID_IBM, 0x0628), },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) MODULE_DEVICE_TABLE(pci, cxl_pci_tbl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) * Mostly using these wrappers to avoid confusion:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) * priv 1 is BAR2, while priv 2 is BAR0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) static inline resource_size_t p1_base(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) return pci_resource_start(dev, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) static inline resource_size_t p1_size(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) return pci_resource_len(dev, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) static inline resource_size_t p2_base(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) return pci_resource_start(dev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) static inline resource_size_t p2_size(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) return pci_resource_len(dev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) static int find_cxl_vsec(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) int vsec = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) u16 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) while ((vsec = pci_find_next_ext_capability(dev, vsec, PCI_EXT_CAP_ID_VNDR))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) pci_read_config_word(dev, vsec + 0x4, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) if (val == CXL_PCI_VSEC_ID)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) return vsec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) static void dump_cxl_config_space(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) int vsec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) dev_info(&dev->dev, "dump_cxl_config_space\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) pci_read_config_dword(dev, PCI_BASE_ADDRESS_0, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) dev_info(&dev->dev, "BAR0: %#.8x\n", val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) pci_read_config_dword(dev, PCI_BASE_ADDRESS_1, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) dev_info(&dev->dev, "BAR1: %#.8x\n", val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) pci_read_config_dword(dev, PCI_BASE_ADDRESS_2, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) dev_info(&dev->dev, "BAR2: %#.8x\n", val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) pci_read_config_dword(dev, PCI_BASE_ADDRESS_3, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) dev_info(&dev->dev, "BAR3: %#.8x\n", val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) pci_read_config_dword(dev, PCI_BASE_ADDRESS_4, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) dev_info(&dev->dev, "BAR4: %#.8x\n", val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) pci_read_config_dword(dev, PCI_BASE_ADDRESS_5, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) dev_info(&dev->dev, "BAR5: %#.8x\n", val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) dev_info(&dev->dev, "p1 regs: %#llx, len: %#llx\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) p1_base(dev), p1_size(dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) dev_info(&dev->dev, "p2 regs: %#llx, len: %#llx\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) p2_base(dev), p2_size(dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) dev_info(&dev->dev, "BAR 4/5: %#llx, len: %#llx\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) pci_resource_start(dev, 4), pci_resource_len(dev, 4));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) if (!(vsec = find_cxl_vsec(dev)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define show_reg(name, what) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) dev_info(&dev->dev, "cxl vsec: %30s: %#x\n", name, what)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) pci_read_config_dword(dev, vsec + 0x0, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) show_reg("Cap ID", (val >> 0) & 0xffff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) show_reg("Cap Ver", (val >> 16) & 0xf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) show_reg("Next Cap Ptr", (val >> 20) & 0xfff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) pci_read_config_dword(dev, vsec + 0x4, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) show_reg("VSEC ID", (val >> 0) & 0xffff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) show_reg("VSEC Rev", (val >> 16) & 0xf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) show_reg("VSEC Length", (val >> 20) & 0xfff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) pci_read_config_dword(dev, vsec + 0x8, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) show_reg("Num AFUs", (val >> 0) & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) show_reg("Status", (val >> 8) & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) show_reg("Mode Control", (val >> 16) & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) show_reg("Reserved", (val >> 24) & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) pci_read_config_dword(dev, vsec + 0xc, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) show_reg("PSL Rev", (val >> 0) & 0xffff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) show_reg("CAIA Ver", (val >> 16) & 0xffff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) pci_read_config_dword(dev, vsec + 0x10, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) show_reg("Base Image Rev", (val >> 0) & 0xffff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) show_reg("Reserved", (val >> 16) & 0x0fff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) show_reg("Image Control", (val >> 28) & 0x3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) show_reg("Reserved", (val >> 30) & 0x1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) show_reg("Image Loaded", (val >> 31) & 0x1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) pci_read_config_dword(dev, vsec + 0x14, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) show_reg("Reserved", val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) pci_read_config_dword(dev, vsec + 0x18, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) show_reg("Reserved", val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) pci_read_config_dword(dev, vsec + 0x1c, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) show_reg("Reserved", val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) pci_read_config_dword(dev, vsec + 0x20, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) show_reg("AFU Descriptor Offset", val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) pci_read_config_dword(dev, vsec + 0x24, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) show_reg("AFU Descriptor Size", val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) pci_read_config_dword(dev, vsec + 0x28, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) show_reg("Problem State Offset", val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) pci_read_config_dword(dev, vsec + 0x2c, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) show_reg("Problem State Size", val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) pci_read_config_dword(dev, vsec + 0x30, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) show_reg("Reserved", val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) pci_read_config_dword(dev, vsec + 0x34, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) show_reg("Reserved", val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) pci_read_config_dword(dev, vsec + 0x38, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) show_reg("Reserved", val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) pci_read_config_dword(dev, vsec + 0x3c, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) show_reg("Reserved", val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) pci_read_config_dword(dev, vsec + 0x40, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) show_reg("PSL Programming Port", val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) pci_read_config_dword(dev, vsec + 0x44, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) show_reg("PSL Programming Control", val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) pci_read_config_dword(dev, vsec + 0x48, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) show_reg("Reserved", val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) pci_read_config_dword(dev, vsec + 0x4c, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) show_reg("Reserved", val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) pci_read_config_dword(dev, vsec + 0x50, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) show_reg("Flash Address Register", val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) pci_read_config_dword(dev, vsec + 0x54, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) show_reg("Flash Size Register", val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) pci_read_config_dword(dev, vsec + 0x58, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) show_reg("Flash Status/Control Register", val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) pci_read_config_dword(dev, vsec + 0x58, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) show_reg("Flash Data Port", val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) #undef show_reg
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) static void dump_afu_descriptor(struct cxl_afu *afu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) u64 val, afu_cr_num, afu_cr_off, afu_cr_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) #define show_reg(name, what) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) dev_info(&afu->dev, "afu desc: %30s: %#llx\n", name, what)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) val = AFUD_READ_INFO(afu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) show_reg("num_ints_per_process", AFUD_NUM_INTS_PER_PROC(val));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) show_reg("num_of_processes", AFUD_NUM_PROCS(val));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) show_reg("num_of_afu_CRs", AFUD_NUM_CRS(val));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) show_reg("req_prog_mode", val & 0xffffULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) afu_cr_num = AFUD_NUM_CRS(val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) val = AFUD_READ(afu, 0x8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) show_reg("Reserved", val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) val = AFUD_READ(afu, 0x10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) show_reg("Reserved", val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) val = AFUD_READ(afu, 0x18);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) show_reg("Reserved", val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) val = AFUD_READ_CR(afu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) show_reg("Reserved", (val >> (63-7)) & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) show_reg("AFU_CR_len", AFUD_CR_LEN(val));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) afu_cr_len = AFUD_CR_LEN(val) * 256;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) val = AFUD_READ_CR_OFF(afu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) afu_cr_off = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) show_reg("AFU_CR_offset", val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) val = AFUD_READ_PPPSA(afu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) show_reg("PerProcessPSA_control", (val >> (63-7)) & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) show_reg("PerProcessPSA Length", AFUD_PPPSA_LEN(val));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) val = AFUD_READ_PPPSA_OFF(afu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) show_reg("PerProcessPSA_offset", val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) val = AFUD_READ_EB(afu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) show_reg("Reserved", (val >> (63-7)) & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) show_reg("AFU_EB_len", AFUD_EB_LEN(val));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) val = AFUD_READ_EB_OFF(afu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) show_reg("AFU_EB_offset", val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) for (i = 0; i < afu_cr_num; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) val = AFUD_READ_LE(afu, afu_cr_off + i * afu_cr_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) show_reg("CR Vendor", val & 0xffff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) show_reg("CR Device", (val >> 16) & 0xffff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) #undef show_reg
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) #define P8_CAPP_UNIT0_ID 0xBA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) #define P8_CAPP_UNIT1_ID 0XBE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) #define P9_CAPP_UNIT0_ID 0xC0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) #define P9_CAPP_UNIT1_ID 0xE0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) static int get_phb_index(struct device_node *np, u32 *phb_index)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) if (of_property_read_u32(np, "ibm,phb-index", phb_index))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) static u64 get_capp_unit_id(struct device_node *np, u32 phb_index)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) * POWER 8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) * - For chips other than POWER8NVL, we only have CAPP 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) * irrespective of which PHB is used.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) * - For POWER8NVL, assume CAPP 0 is attached to PHB0 and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) * CAPP 1 is attached to PHB1.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) if (cxl_is_power8()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) if (!pvr_version_is(PVR_POWER8NVL))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) return P8_CAPP_UNIT0_ID;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) if (phb_index == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) return P8_CAPP_UNIT0_ID;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) if (phb_index == 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) return P8_CAPP_UNIT1_ID;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) * POWER 9:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) * PEC0 (PHB0). Capp ID = CAPP0 (0b1100_0000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) * PEC1 (PHB1 - PHB2). No capi mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) * PEC2 (PHB3 - PHB4 - PHB5): Capi mode on PHB3 only. Capp ID = CAPP1 (0b1110_0000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) if (cxl_is_power9()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) if (phb_index == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) return P9_CAPP_UNIT0_ID;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) if (phb_index == 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) return P9_CAPP_UNIT1_ID;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) int cxl_calc_capp_routing(struct pci_dev *dev, u64 *chipid,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) u32 *phb_index, u64 *capp_unit_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) struct device_node *np;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) const __be32 *prop;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) if (!(np = pnv_pci_get_phb_node(dev)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) while (np && !(prop = of_get_property(np, "ibm,chip-id", NULL)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) np = of_get_next_parent(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) if (!np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) *chipid = be32_to_cpup(prop);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) rc = get_phb_index(np, phb_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) if (rc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) pr_err("cxl: invalid phb index\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) *capp_unit_id = get_capp_unit_id(np, *phb_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) of_node_put(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) if (!*capp_unit_id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) pr_err("cxl: No capp unit found for PHB[%lld,%d]. Make sure the adapter is on a capi-compatible slot\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) *chipid, *phb_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) static DEFINE_MUTEX(indications_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) static int get_phb_indications(struct pci_dev *dev, u64 *capiind, u64 *asnind,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) u64 *nbwind)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) static u64 nbw, asn, capi = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) struct device_node *np;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) const __be32 *prop;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) mutex_lock(&indications_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) if (!capi) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) if (!(np = pnv_pci_get_phb_node(dev))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) mutex_unlock(&indications_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) prop = of_get_property(np, "ibm,phb-indications", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) if (!prop) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) nbw = 0x0300UL; /* legacy values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) asn = 0x0400UL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) capi = 0x0200UL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) nbw = (u64)be32_to_cpu(prop[2]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) asn = (u64)be32_to_cpu(prop[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) capi = (u64)be32_to_cpu(prop[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) of_node_put(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) *capiind = capi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) *asnind = asn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) *nbwind = nbw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) mutex_unlock(&indications_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) int cxl_get_xsl9_dsnctl(struct pci_dev *dev, u64 capp_unit_id, u64 *reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) u64 xsl_dsnctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) u64 capiind, asnind, nbwind;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) * CAPI Identifier bits [0:7]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) * bit 61:60 MSI bits --> 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) * bit 59 TVT selector --> 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) if (get_phb_indications(dev, &capiind, &asnind, &nbwind))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) * Tell XSL where to route data to.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) * The field chipid should match the PHB CAPI_CMPM register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) xsl_dsnctl = (capiind << (63-15)); /* Bit 57 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) xsl_dsnctl |= (capp_unit_id << (63-15));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) /* nMMU_ID Defaults to: b’000001001’*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) xsl_dsnctl |= ((u64)0x09 << (63-28));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) * Used to identify CAPI packets which should be sorted into
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) * the Non-Blocking queues by the PHB. This field should match
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) * the PHB PBL_NBW_CMPM register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) * nbwind=0x03, bits [57:58], must include capi indicator.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) * Not supported on P9 DD1.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) xsl_dsnctl |= (nbwind << (63-55));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) * Upper 16b address bits of ASB_Notify messages sent to the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) * system. Need to match the PHB’s ASN Compare/Mask Register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) * Not supported on P9 DD1.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) xsl_dsnctl |= asnind;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) *reg = xsl_dsnctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) static int init_implementation_adapter_regs_psl9(struct cxl *adapter,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) u64 xsl_dsnctl, psl_fircntl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) u64 chipid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) u32 phb_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) u64 capp_unit_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) u64 psl_debug;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) rc = cxl_calc_capp_routing(dev, &chipid, &phb_index, &capp_unit_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) rc = cxl_get_xsl9_dsnctl(dev, capp_unit_id, &xsl_dsnctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) cxl_p1_write(adapter, CXL_XSL9_DSNCTL, xsl_dsnctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) /* Set fir_cntl to recommended value for production env */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) psl_fircntl = (0x2ULL << (63-3)); /* ce_report */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) psl_fircntl |= (0x1ULL << (63-6)); /* FIR_report */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) psl_fircntl |= 0x1ULL; /* ce_thresh */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) cxl_p1_write(adapter, CXL_PSL9_FIR_CNTL, psl_fircntl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) /* Setup the PSL to transmit packets on the PCIe before the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) * CAPP is enabled. Make sure that CAPP virtual machines are disabled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) cxl_p1_write(adapter, CXL_PSL9_DSNDCTL, 0x0001001000012A10ULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) * A response to an ASB_Notify request is returned by the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) * system as an MMIO write to the address defined in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) * the PSL_TNR_ADDR register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) * keep the Reset Value: 0x00020000E0000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) /* Enable XSL rty limit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) cxl_p1_write(adapter, CXL_XSL9_DEF, 0x51F8000000000005ULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) /* Change XSL_INV dummy read threshold */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) cxl_p1_write(adapter, CXL_XSL9_INV, 0x0000040007FFC200ULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) if (phb_index == 3) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) /* disable machines 31-47 and 20-27 for DMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) cxl_p1_write(adapter, CXL_PSL9_APCDEDTYPE, 0x40000FF3FFFF0000ULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) /* Snoop machines */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) cxl_p1_write(adapter, CXL_PSL9_APCDEDALLOC, 0x800F000200000000ULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) /* Enable NORST and DD2 features */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) cxl_p1_write(adapter, CXL_PSL9_DEBUG, 0xC000000000000000ULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) * Check if PSL has data-cache. We need to flush adapter datacache
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) * when as its about to be removed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) psl_debug = cxl_p1_read(adapter, CXL_PSL9_DEBUG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) if (psl_debug & CXL_PSL_DEBUG_CDC) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) dev_dbg(&dev->dev, "No data-cache present\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) adapter->native->no_data_cache = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) static int init_implementation_adapter_regs_psl8(struct cxl *adapter, struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) u64 psl_dsnctl, psl_fircntl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) u64 chipid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) u32 phb_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) u64 capp_unit_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) rc = cxl_calc_capp_routing(dev, &chipid, &phb_index, &capp_unit_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) psl_dsnctl = 0x0000900000000000ULL; /* pteupd ttype, scdone */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) psl_dsnctl |= (0x2ULL << (63-38)); /* MMIO hang pulse: 256 us */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) /* Tell PSL where to route data to */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) psl_dsnctl |= (chipid << (63-5));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) psl_dsnctl |= (capp_unit_id << (63-13));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) cxl_p1_write(adapter, CXL_PSL_DSNDCTL, psl_dsnctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) cxl_p1_write(adapter, CXL_PSL_RESLCKTO, 0x20000000200ULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) /* snoop write mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) cxl_p1_write(adapter, CXL_PSL_SNWRALLOC, 0x00000000FFFFFFFFULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) /* set fir_cntl to recommended value for production env */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) psl_fircntl = (0x2ULL << (63-3)); /* ce_report */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) psl_fircntl |= (0x1ULL << (63-6)); /* FIR_report */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) psl_fircntl |= 0x1ULL; /* ce_thresh */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) cxl_p1_write(adapter, CXL_PSL_FIR_CNTL, psl_fircntl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) /* for debugging with trace arrays */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) cxl_p1_write(adapter, CXL_PSL_TRACE, 0x0000FF7C00000000ULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) /* PSL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) #define TBSYNC_CAL(n) (((u64)n & 0x7) << (63-3))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) #define TBSYNC_CNT(n) (((u64)n & 0x7) << (63-6))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) /* For the PSL this is a multiple for 0 < n <= 7: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) #define PSL_2048_250MHZ_CYCLES 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) static void write_timebase_ctrl_psl8(struct cxl *adapter)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) cxl_p1_write(adapter, CXL_PSL_TB_CTLSTAT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) TBSYNC_CNT(2 * PSL_2048_250MHZ_CYCLES));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) static u64 timebase_read_psl9(struct cxl *adapter)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) return cxl_p1_read(adapter, CXL_PSL9_Timebase);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) static u64 timebase_read_psl8(struct cxl *adapter)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) return cxl_p1_read(adapter, CXL_PSL_Timebase);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) static void cxl_setup_psl_timebase(struct cxl *adapter, struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) struct device_node *np;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) adapter->psl_timebase_synced = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) if (!(np = pnv_pci_get_phb_node(dev)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) /* Do not fail when CAPP timebase sync is not supported by OPAL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) of_node_get(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) if (! of_get_property(np, "ibm,capp-timebase-sync", NULL)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) of_node_put(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) dev_info(&dev->dev, "PSL timebase inactive: OPAL support missing\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) of_node_put(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) * Setup PSL Timebase Control and Status register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) * with the recommended Timebase Sync Count value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) if (adapter->native->sl_ops->write_timebase_ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) adapter->native->sl_ops->write_timebase_ctrl(adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) /* Enable PSL Timebase */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) cxl_p1_write(adapter, CXL_PSL_Control, 0x0000000000000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) cxl_p1_write(adapter, CXL_PSL_Control, CXL_PSL_Control_tb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) static int init_implementation_afu_regs_psl9(struct cxl_afu *afu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) static int init_implementation_afu_regs_psl8(struct cxl_afu *afu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) /* read/write masks for this slice */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) cxl_p1n_write(afu, CXL_PSL_APCALLOC_A, 0xFFFFFFFEFEFEFEFEULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) /* APC read/write masks for this slice */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) cxl_p1n_write(afu, CXL_PSL_COALLOC_A, 0xFF000000FEFEFEFEULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) /* for debugging with trace arrays */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) cxl_p1n_write(afu, CXL_PSL_SLICE_TRACE, 0x0000FFFF00000000ULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) cxl_p1n_write(afu, CXL_PSL_RXCTL_A, CXL_PSL_RXCTL_AFUHP_4S);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) int cxl_pci_setup_irq(struct cxl *adapter, unsigned int hwirq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) unsigned int virq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) struct pci_dev *dev = to_pci_dev(adapter->dev.parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) return pnv_cxl_ioda_msi_setup(dev, hwirq, virq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) int cxl_update_image_control(struct cxl *adapter)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) struct pci_dev *dev = to_pci_dev(adapter->dev.parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) int vsec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) u8 image_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) if (!(vsec = find_cxl_vsec(dev))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) dev_err(&dev->dev, "ABORTING: CXL VSEC not found!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) if ((rc = CXL_READ_VSEC_IMAGE_STATE(dev, vsec, &image_state))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) dev_err(&dev->dev, "failed to read image state: %i\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) if (adapter->perst_loads_image)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) image_state |= CXL_VSEC_PERST_LOADS_IMAGE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) image_state &= ~CXL_VSEC_PERST_LOADS_IMAGE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) if (adapter->perst_select_user)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) image_state |= CXL_VSEC_PERST_SELECT_USER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) image_state &= ~CXL_VSEC_PERST_SELECT_USER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) if ((rc = CXL_WRITE_VSEC_IMAGE_STATE(dev, vsec, image_state))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) dev_err(&dev->dev, "failed to update image control: %i\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) int cxl_pci_alloc_one_irq(struct cxl *adapter)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) struct pci_dev *dev = to_pci_dev(adapter->dev.parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) return pnv_cxl_alloc_hwirqs(dev, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) void cxl_pci_release_one_irq(struct cxl *adapter, int hwirq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) struct pci_dev *dev = to_pci_dev(adapter->dev.parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) return pnv_cxl_release_hwirqs(dev, hwirq, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) int cxl_pci_alloc_irq_ranges(struct cxl_irq_ranges *irqs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) struct cxl *adapter, unsigned int num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) struct pci_dev *dev = to_pci_dev(adapter->dev.parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) return pnv_cxl_alloc_hwirq_ranges(irqs, dev, num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) void cxl_pci_release_irq_ranges(struct cxl_irq_ranges *irqs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) struct cxl *adapter)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) struct pci_dev *dev = to_pci_dev(adapter->dev.parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) pnv_cxl_release_hwirq_ranges(irqs, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) static int setup_cxl_bars(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) /* Safety check in case we get backported to < 3.17 without M64 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) if ((p1_base(dev) < 0x100000000ULL) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) (p2_base(dev) < 0x100000000ULL)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) dev_err(&dev->dev, "ABORTING: M32 BAR assignment incompatible with CXL\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) * BAR 4/5 has a special meaning for CXL and must be programmed with a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) * special value corresponding to the CXL protocol address range.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) * For POWER 8/9 that means bits 48:49 must be set to 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) pci_write_config_dword(dev, PCI_BASE_ADDRESS_4, 0x00000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) pci_write_config_dword(dev, PCI_BASE_ADDRESS_5, 0x00020000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) /* pciex node: ibm,opal-m64-window = <0x3d058 0x0 0x3d058 0x0 0x8 0x0>; */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) static int switch_card_to_cxl(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) int vsec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) dev_info(&dev->dev, "switch card to CXL\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) if (!(vsec = find_cxl_vsec(dev))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) dev_err(&dev->dev, "ABORTING: CXL VSEC not found!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) if ((rc = CXL_READ_VSEC_MODE_CONTROL(dev, vsec, &val))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) dev_err(&dev->dev, "failed to read current mode control: %i", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) val &= ~CXL_VSEC_PROTOCOL_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) val |= CXL_VSEC_PROTOCOL_256TB | CXL_VSEC_PROTOCOL_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) if ((rc = CXL_WRITE_VSEC_MODE_CONTROL(dev, vsec, val))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) dev_err(&dev->dev, "failed to enable CXL protocol: %i", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) * The CAIA spec (v0.12 11.6 Bi-modal Device Support) states
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) * we must wait 100ms after this mode switch before touching
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) * PCIe config space.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) msleep(100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) static int pci_map_slice_regs(struct cxl_afu *afu, struct cxl *adapter, struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) u64 p1n_base, p2n_base, afu_desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) const u64 p1n_size = 0x100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) const u64 p2n_size = 0x1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) p1n_base = p1_base(dev) + 0x10000 + (afu->slice * p1n_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) p2n_base = p2_base(dev) + (afu->slice * p2n_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) afu->psn_phys = p2_base(dev) + (adapter->native->ps_off + (afu->slice * adapter->ps_size));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) afu_desc = p2_base(dev) + adapter->native->afu_desc_off + (afu->slice * adapter->native->afu_desc_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) if (!(afu->native->p1n_mmio = ioremap(p1n_base, p1n_size)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) if (!(afu->p2n_mmio = ioremap(p2n_base, p2n_size)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) goto err1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) if (afu_desc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) if (!(afu->native->afu_desc_mmio = ioremap(afu_desc, adapter->native->afu_desc_size)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) goto err2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) err2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) iounmap(afu->p2n_mmio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) err1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) iounmap(afu->native->p1n_mmio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) dev_err(&afu->dev, "Error mapping AFU MMIO regions\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) static void pci_unmap_slice_regs(struct cxl_afu *afu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) if (afu->p2n_mmio) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) iounmap(afu->p2n_mmio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) afu->p2n_mmio = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) if (afu->native->p1n_mmio) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) iounmap(afu->native->p1n_mmio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) afu->native->p1n_mmio = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) if (afu->native->afu_desc_mmio) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) iounmap(afu->native->afu_desc_mmio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) afu->native->afu_desc_mmio = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) void cxl_pci_release_afu(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) struct cxl_afu *afu = to_cxl_afu(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) pr_devel("%s\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) idr_destroy(&afu->contexts_idr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) cxl_release_spa(afu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) kfree(afu->native);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) kfree(afu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) /* Expects AFU struct to have recently been zeroed out */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) static int cxl_read_afu_descriptor(struct cxl_afu *afu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) u64 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) val = AFUD_READ_INFO(afu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) afu->pp_irqs = AFUD_NUM_INTS_PER_PROC(val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) afu->max_procs_virtualised = AFUD_NUM_PROCS(val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) afu->crs_num = AFUD_NUM_CRS(val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) if (AFUD_AFU_DIRECTED(val))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) afu->modes_supported |= CXL_MODE_DIRECTED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) if (AFUD_DEDICATED_PROCESS(val))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) afu->modes_supported |= CXL_MODE_DEDICATED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) if (AFUD_TIME_SLICED(val))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) afu->modes_supported |= CXL_MODE_TIME_SLICED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) val = AFUD_READ_PPPSA(afu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) afu->pp_size = AFUD_PPPSA_LEN(val) * 4096;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) afu->psa = AFUD_PPPSA_PSA(val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) if ((afu->pp_psa = AFUD_PPPSA_PP(val)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) afu->native->pp_offset = AFUD_READ_PPPSA_OFF(afu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) val = AFUD_READ_CR(afu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) afu->crs_len = AFUD_CR_LEN(val) * 256;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) afu->crs_offset = AFUD_READ_CR_OFF(afu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) /* eb_len is in multiple of 4K */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) afu->eb_len = AFUD_EB_LEN(AFUD_READ_EB(afu)) * 4096;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) afu->eb_offset = AFUD_READ_EB_OFF(afu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) /* eb_off is 4K aligned so lower 12 bits are always zero */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) if (EXTRACT_PPC_BITS(afu->eb_offset, 0, 11) != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) dev_warn(&afu->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) "Invalid AFU error buffer offset %Lx\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) afu->eb_offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) dev_info(&afu->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) "Ignoring AFU error buffer in the descriptor\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) /* indicate that no afu buffer exists */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) afu->eb_len = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) static int cxl_afu_descriptor_looks_ok(struct cxl_afu *afu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) int i, rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) if (afu->psa && afu->adapter->ps_size <
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) (afu->native->pp_offset + afu->pp_size*afu->max_procs_virtualised)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) dev_err(&afu->dev, "per-process PSA can't fit inside the PSA!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) if (afu->pp_psa && (afu->pp_size < PAGE_SIZE))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) dev_warn(&afu->dev, "AFU uses pp_size(%#016llx) < PAGE_SIZE per-process PSA!\n", afu->pp_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) for (i = 0; i < afu->crs_num; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) rc = cxl_ops->afu_cr_read32(afu, i, 0, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) if (rc || val == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) dev_err(&afu->dev, "ABORTING: AFU configuration record %i is invalid\n", i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) if ((afu->modes_supported & ~CXL_MODE_DEDICATED) && afu->max_procs_virtualised == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) * We could also check this for the dedicated process model
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) * since the architecture indicates it should be set to 1, but
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) * in that case we ignore the value and I'd rather not risk
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) * breaking any existing dedicated process AFUs that left it as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) * 0 (not that I'm aware of any). It is clearly an error for an
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) * AFU directed AFU to set this to 0, and would have previously
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) * triggered a bug resulting in the maximum not being enforced
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) * at all since idr_alloc treats 0 as no maximum.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) dev_err(&afu->dev, "AFU does not support any processes\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) static int sanitise_afu_regs_psl9(struct cxl_afu *afu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) u64 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) * Clear out any regs that contain either an IVTE or address or may be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) * waiting on an acknowledgment to try to be a bit safer as we bring
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) * it online
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) reg = cxl_p2n_read(afu, CXL_AFU_Cntl_An);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) if ((reg & CXL_AFU_Cntl_An_ES_MASK) != CXL_AFU_Cntl_An_ES_Disabled) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) dev_warn(&afu->dev, "WARNING: AFU was not disabled: %#016llx\n", reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) if (cxl_ops->afu_reset(afu))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) if (cxl_afu_disable(afu))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) if (cxl_psl_purge(afu))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) cxl_p1n_write(afu, CXL_PSL_SPAP_An, 0x0000000000000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) cxl_p1n_write(afu, CXL_PSL_AMBAR_An, 0x0000000000000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) reg = cxl_p2n_read(afu, CXL_PSL_DSISR_An);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) if (reg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) dev_warn(&afu->dev, "AFU had pending DSISR: %#016llx\n", reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) if (reg & CXL_PSL9_DSISR_An_TF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) cxl_p2n_write(afu, CXL_PSL_TFC_An, CXL_PSL_TFC_An_AE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) cxl_p2n_write(afu, CXL_PSL_TFC_An, CXL_PSL_TFC_An_A);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) if (afu->adapter->native->sl_ops->register_serr_irq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) reg = cxl_p1n_read(afu, CXL_PSL_SERR_An);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) if (reg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) if (reg & ~0x000000007fffffff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) dev_warn(&afu->dev, "AFU had pending SERR: %#016llx\n", reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) cxl_p1n_write(afu, CXL_PSL_SERR_An, reg & ~0xffff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) reg = cxl_p2n_read(afu, CXL_PSL_ErrStat_An);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) if (reg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) dev_warn(&afu->dev, "AFU had pending error status: %#016llx\n", reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) cxl_p2n_write(afu, CXL_PSL_ErrStat_An, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) static int sanitise_afu_regs_psl8(struct cxl_afu *afu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) u64 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) * Clear out any regs that contain either an IVTE or address or may be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) * waiting on an acknowledgement to try to be a bit safer as we bring
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) * it online
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) reg = cxl_p2n_read(afu, CXL_AFU_Cntl_An);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) if ((reg & CXL_AFU_Cntl_An_ES_MASK) != CXL_AFU_Cntl_An_ES_Disabled) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) dev_warn(&afu->dev, "WARNING: AFU was not disabled: %#016llx\n", reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) if (cxl_ops->afu_reset(afu))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) if (cxl_afu_disable(afu))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) if (cxl_psl_purge(afu))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) cxl_p1n_write(afu, CXL_PSL_SPAP_An, 0x0000000000000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) cxl_p1n_write(afu, CXL_PSL_IVTE_Limit_An, 0x0000000000000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) cxl_p1n_write(afu, CXL_PSL_IVTE_Offset_An, 0x0000000000000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) cxl_p1n_write(afu, CXL_PSL_AMBAR_An, 0x0000000000000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) cxl_p1n_write(afu, CXL_PSL_SPOffset_An, 0x0000000000000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) cxl_p1n_write(afu, CXL_HAURP_An, 0x0000000000000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) cxl_p2n_write(afu, CXL_CSRP_An, 0x0000000000000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) cxl_p2n_write(afu, CXL_AURP1_An, 0x0000000000000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) cxl_p2n_write(afu, CXL_AURP0_An, 0x0000000000000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) cxl_p2n_write(afu, CXL_SSTP1_An, 0x0000000000000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) cxl_p2n_write(afu, CXL_SSTP0_An, 0x0000000000000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) reg = cxl_p2n_read(afu, CXL_PSL_DSISR_An);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) if (reg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) dev_warn(&afu->dev, "AFU had pending DSISR: %#016llx\n", reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) if (reg & CXL_PSL_DSISR_TRANS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) cxl_p2n_write(afu, CXL_PSL_TFC_An, CXL_PSL_TFC_An_AE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) cxl_p2n_write(afu, CXL_PSL_TFC_An, CXL_PSL_TFC_An_A);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) if (afu->adapter->native->sl_ops->register_serr_irq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) reg = cxl_p1n_read(afu, CXL_PSL_SERR_An);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) if (reg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) if (reg & ~0xffff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) dev_warn(&afu->dev, "AFU had pending SERR: %#016llx\n", reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) cxl_p1n_write(afu, CXL_PSL_SERR_An, reg & ~0xffff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) reg = cxl_p2n_read(afu, CXL_PSL_ErrStat_An);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) if (reg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) dev_warn(&afu->dev, "AFU had pending error status: %#016llx\n", reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) cxl_p2n_write(afu, CXL_PSL_ErrStat_An, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) #define ERR_BUFF_MAX_COPY_SIZE PAGE_SIZE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) * afu_eb_read:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) * Called from sysfs and reads the afu error info buffer. The h/w only supports
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) * 4/8 bytes aligned access. So in case the requested offset/count arent 8 byte
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) * aligned the function uses a bounce buffer which can be max PAGE_SIZE.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) ssize_t cxl_pci_afu_read_err_buffer(struct cxl_afu *afu, char *buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) loff_t off, size_t count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) loff_t aligned_start, aligned_end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) size_t aligned_length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) void *tbuf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) const void __iomem *ebuf = afu->native->afu_desc_mmio + afu->eb_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) if (count == 0 || off < 0 || (size_t)off >= afu->eb_len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) /* calculate aligned read window */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) count = min((size_t)(afu->eb_len - off), count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) aligned_start = round_down(off, 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) aligned_end = round_up(off + count, 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) aligned_length = aligned_end - aligned_start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) /* max we can copy in one read is PAGE_SIZE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) if (aligned_length > ERR_BUFF_MAX_COPY_SIZE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) aligned_length = ERR_BUFF_MAX_COPY_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) count = ERR_BUFF_MAX_COPY_SIZE - (off & 0x7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) /* use bounce buffer for copy */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) tbuf = (void *)__get_free_page(GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) if (!tbuf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) /* perform aligned read from the mmio region */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) memcpy_fromio(tbuf, ebuf + aligned_start, aligned_length);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) memcpy(buf, tbuf + (off & 0x7), count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) free_page((unsigned long)tbuf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) return count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) static int pci_configure_afu(struct cxl_afu *afu, struct cxl *adapter, struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) if ((rc = pci_map_slice_regs(afu, adapter, dev)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) if (adapter->native->sl_ops->sanitise_afu_regs) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) rc = adapter->native->sl_ops->sanitise_afu_regs(afu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) goto err1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) /* We need to reset the AFU before we can read the AFU descriptor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) if ((rc = cxl_ops->afu_reset(afu)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) goto err1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) if (cxl_verbose)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) dump_afu_descriptor(afu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) if ((rc = cxl_read_afu_descriptor(afu)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) goto err1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) if ((rc = cxl_afu_descriptor_looks_ok(afu)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) goto err1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) if (adapter->native->sl_ops->afu_regs_init)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) if ((rc = adapter->native->sl_ops->afu_regs_init(afu)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) goto err1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) if (adapter->native->sl_ops->register_serr_irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) if ((rc = adapter->native->sl_ops->register_serr_irq(afu)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) goto err1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) if ((rc = cxl_native_register_psl_irq(afu)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) goto err2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) atomic_set(&afu->configured_state, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) err2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) if (adapter->native->sl_ops->release_serr_irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) adapter->native->sl_ops->release_serr_irq(afu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) err1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) pci_unmap_slice_regs(afu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) static void pci_deconfigure_afu(struct cxl_afu *afu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) * It's okay to deconfigure when AFU is already locked, otherwise wait
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) * until there are no readers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) if (atomic_read(&afu->configured_state) != -1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) while (atomic_cmpxchg(&afu->configured_state, 0, -1) != -1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) schedule();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) cxl_native_release_psl_irq(afu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) if (afu->adapter->native->sl_ops->release_serr_irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) afu->adapter->native->sl_ops->release_serr_irq(afu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) pci_unmap_slice_regs(afu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) static int pci_init_afu(struct cxl *adapter, int slice, struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) struct cxl_afu *afu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) int rc = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) afu = cxl_alloc_afu(adapter, slice);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) if (!afu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) afu->native = kzalloc(sizeof(struct cxl_afu_native), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) if (!afu->native)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) goto err_free_afu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) mutex_init(&afu->native->spa_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) rc = dev_set_name(&afu->dev, "afu%i.%i", adapter->adapter_num, slice);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) goto err_free_native;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) rc = pci_configure_afu(afu, adapter, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) goto err_free_native;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) /* Don't care if this fails */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) cxl_debugfs_afu_add(afu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) * After we call this function we must not free the afu directly, even
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) * if it returns an error!
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) if ((rc = cxl_register_afu(afu)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) goto err_put1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) if ((rc = cxl_sysfs_afu_add(afu)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) goto err_put1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) adapter->afu[afu->slice] = afu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) if ((rc = cxl_pci_vphb_add(afu)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) dev_info(&afu->dev, "Can't register vPHB\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) err_put1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) pci_deconfigure_afu(afu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) cxl_debugfs_afu_remove(afu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) device_unregister(&afu->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) err_free_native:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) kfree(afu->native);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) err_free_afu:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) kfree(afu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) static void cxl_pci_remove_afu(struct cxl_afu *afu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) pr_devel("%s\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) if (!afu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) cxl_pci_vphb_remove(afu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) cxl_sysfs_afu_remove(afu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) cxl_debugfs_afu_remove(afu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) spin_lock(&afu->adapter->afu_list_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) afu->adapter->afu[afu->slice] = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) spin_unlock(&afu->adapter->afu_list_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) cxl_context_detach_all(afu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) cxl_ops->afu_deactivate_mode(afu, afu->current_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) pci_deconfigure_afu(afu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) device_unregister(&afu->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) int cxl_pci_reset(struct cxl *adapter)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) struct pci_dev *dev = to_pci_dev(adapter->dev.parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) if (adapter->perst_same_image) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) dev_warn(&dev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) "cxl: refusing to reset/reflash when perst_reloads_same_image is set.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) dev_info(&dev->dev, "CXL reset\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) * The adapter is about to be reset, so ignore errors.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) cxl_data_cache_flush(adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) /* pcie_warm_reset requests a fundamental pci reset which includes a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) * PERST assert/deassert. PERST triggers a loading of the image
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) * if "user" or "factory" is selected in sysfs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) if ((rc = pci_set_pcie_reset_state(dev, pcie_warm_reset))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) dev_err(&dev->dev, "cxl: pcie_warm_reset failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) static int cxl_map_adapter_regs(struct cxl *adapter, struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) if (pci_request_region(dev, 2, "priv 2 regs"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) goto err1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) if (pci_request_region(dev, 0, "priv 1 regs"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) goto err2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) pr_devel("cxl_map_adapter_regs: p1: %#016llx %#llx, p2: %#016llx %#llx",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) p1_base(dev), p1_size(dev), p2_base(dev), p2_size(dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) if (!(adapter->native->p1_mmio = ioremap(p1_base(dev), p1_size(dev))))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) goto err3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) if (!(adapter->native->p2_mmio = ioremap(p2_base(dev), p2_size(dev))))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) goto err4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) err4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) iounmap(adapter->native->p1_mmio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) adapter->native->p1_mmio = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) err3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) pci_release_region(dev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) err2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) pci_release_region(dev, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) err1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) static void cxl_unmap_adapter_regs(struct cxl *adapter)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) if (adapter->native->p1_mmio) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) iounmap(adapter->native->p1_mmio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) adapter->native->p1_mmio = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) pci_release_region(to_pci_dev(adapter->dev.parent), 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) if (adapter->native->p2_mmio) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) iounmap(adapter->native->p2_mmio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) adapter->native->p2_mmio = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) pci_release_region(to_pci_dev(adapter->dev.parent), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) static int cxl_read_vsec(struct cxl *adapter, struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) int vsec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) u32 afu_desc_off, afu_desc_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) u32 ps_off, ps_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) u16 vseclen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) u8 image_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) if (!(vsec = find_cxl_vsec(dev))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) dev_err(&dev->dev, "ABORTING: CXL VSEC not found!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) CXL_READ_VSEC_LENGTH(dev, vsec, &vseclen);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) if (vseclen < CXL_VSEC_MIN_SIZE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) dev_err(&dev->dev, "ABORTING: CXL VSEC too short\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) CXL_READ_VSEC_STATUS(dev, vsec, &adapter->vsec_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) CXL_READ_VSEC_PSL_REVISION(dev, vsec, &adapter->psl_rev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) CXL_READ_VSEC_CAIA_MAJOR(dev, vsec, &adapter->caia_major);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) CXL_READ_VSEC_CAIA_MINOR(dev, vsec, &adapter->caia_minor);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) CXL_READ_VSEC_BASE_IMAGE(dev, vsec, &adapter->base_image);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) CXL_READ_VSEC_IMAGE_STATE(dev, vsec, &image_state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) adapter->user_image_loaded = !!(image_state & CXL_VSEC_USER_IMAGE_LOADED);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) adapter->perst_select_user = !!(image_state & CXL_VSEC_USER_IMAGE_LOADED);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) adapter->perst_loads_image = !!(image_state & CXL_VSEC_PERST_LOADS_IMAGE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) CXL_READ_VSEC_NAFUS(dev, vsec, &adapter->slices);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) CXL_READ_VSEC_AFU_DESC_OFF(dev, vsec, &afu_desc_off);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) CXL_READ_VSEC_AFU_DESC_SIZE(dev, vsec, &afu_desc_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) CXL_READ_VSEC_PS_OFF(dev, vsec, &ps_off);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) CXL_READ_VSEC_PS_SIZE(dev, vsec, &ps_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) /* Convert everything to bytes, because there is NO WAY I'd look at the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) * code a month later and forget what units these are in ;-) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) adapter->native->ps_off = ps_off * 64 * 1024;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) adapter->ps_size = ps_size * 64 * 1024;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) adapter->native->afu_desc_off = afu_desc_off * 64 * 1024;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) adapter->native->afu_desc_size = afu_desc_size * 64 * 1024;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) /* Total IRQs - 1 PSL ERROR - #AFU*(1 slice error + 1 DSI) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) adapter->user_irqs = pnv_cxl_get_irq_count(dev) - 1 - 2*adapter->slices;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) * Workaround a PCIe Host Bridge defect on some cards, that can cause
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) * malformed Transaction Layer Packet (TLP) errors to be erroneously
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) * reported. Mask this error in the Uncorrectable Error Mask Register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) * The upper nibble of the PSL revision is used to distinguish between
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) * different cards. The affected ones have it set to 0.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) static void cxl_fixup_malformed_tlp(struct cxl *adapter, struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) int aer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) u32 data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) if (adapter->psl_rev & 0xf000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) if (!(aer = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ERR)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) pci_read_config_dword(dev, aer + PCI_ERR_UNCOR_MASK, &data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) if (data & PCI_ERR_UNC_MALF_TLP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) if (data & PCI_ERR_UNC_INTN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) data |= PCI_ERR_UNC_MALF_TLP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) data |= PCI_ERR_UNC_INTN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) pci_write_config_dword(dev, aer + PCI_ERR_UNCOR_MASK, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) static bool cxl_compatible_caia_version(struct cxl *adapter)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) if (cxl_is_power8() && (adapter->caia_major == 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) if (cxl_is_power9() && (adapter->caia_major == 2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) static int cxl_vsec_looks_ok(struct cxl *adapter, struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) if (adapter->vsec_status & CXL_STATUS_SECOND_PORT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) if (adapter->vsec_status & CXL_UNSUPPORTED_FEATURES) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) dev_err(&dev->dev, "ABORTING: CXL requires unsupported features\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) if (!cxl_compatible_caia_version(adapter)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) dev_info(&dev->dev, "Ignoring card. PSL type is not supported (caia version: %d)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) adapter->caia_major);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) if (!adapter->slices) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) /* Once we support dynamic reprogramming we can use the card if
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) * it supports loadable AFUs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) dev_err(&dev->dev, "ABORTING: Device has no AFUs\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) if (!adapter->native->afu_desc_off || !adapter->native->afu_desc_size) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) dev_err(&dev->dev, "ABORTING: VSEC shows no AFU descriptors\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) if (adapter->ps_size > p2_size(dev) - adapter->native->ps_off) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) dev_err(&dev->dev, "ABORTING: Problem state size larger than "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) "available in BAR2: 0x%llx > 0x%llx\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) adapter->ps_size, p2_size(dev) - adapter->native->ps_off);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) ssize_t cxl_pci_read_adapter_vpd(struct cxl *adapter, void *buf, size_t len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) return pci_read_vpd(to_pci_dev(adapter->dev.parent), 0, len, buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) static void cxl_release_adapter(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) struct cxl *adapter = to_cxl_adapter(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) pr_devel("cxl_release_adapter\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) cxl_remove_adapter_nr(adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) kfree(adapter->native);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) kfree(adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) #define CXL_PSL_ErrIVTE_tberror (0x1ull << (63-31))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) static int sanitise_adapter_regs(struct cxl *adapter)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) int rc = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) /* Clear PSL tberror bit by writing 1 to it */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) cxl_p1_write(adapter, CXL_PSL_ErrIVTE, CXL_PSL_ErrIVTE_tberror);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) if (adapter->native->sl_ops->invalidate_all) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) /* do not invalidate ERAT entries when not reloading on PERST */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) if (cxl_is_power9() && (adapter->perst_loads_image))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) rc = adapter->native->sl_ops->invalidate_all(adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) /* This should contain *only* operations that can safely be done in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) * both creation and recovery.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) static int cxl_configure_adapter(struct cxl *adapter, struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) adapter->dev.parent = &dev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) adapter->dev.release = cxl_release_adapter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) pci_set_drvdata(dev, adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) rc = pci_enable_device(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) if (rc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) dev_err(&dev->dev, "pci_enable_device failed: %i\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) if ((rc = cxl_read_vsec(adapter, dev)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) if ((rc = cxl_vsec_looks_ok(adapter, dev)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) cxl_fixup_malformed_tlp(adapter, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) if ((rc = setup_cxl_bars(dev)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) if ((rc = switch_card_to_cxl(dev)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) if ((rc = cxl_update_image_control(adapter)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) if ((rc = cxl_map_adapter_regs(adapter, dev)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) if ((rc = sanitise_adapter_regs(adapter)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) if ((rc = adapter->native->sl_ops->adapter_regs_init(adapter, dev)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) /* Required for devices using CAPP DMA mode, harmless for others */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) pci_set_master(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) adapter->tunneled_ops_supported = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) if (cxl_is_power9()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) if (pnv_pci_set_tunnel_bar(dev, 0x00020000E0000000ull, 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) dev_info(&dev->dev, "Tunneled operations unsupported\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) adapter->tunneled_ops_supported = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) if ((rc = pnv_phb_to_cxl_mode(dev, adapter->native->sl_ops->capi_mode)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) /* If recovery happened, the last step is to turn on snooping.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) * In the non-recovery case this has no effect */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) if ((rc = pnv_phb_to_cxl_mode(dev, OPAL_PHB_CAPI_MODE_SNOOP_ON)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) /* Ignore error, adapter init is not dependant on timebase sync */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) cxl_setup_psl_timebase(adapter, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) if ((rc = cxl_native_register_psl_err_irq(adapter)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) cxl_unmap_adapter_regs(adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) static void cxl_deconfigure_adapter(struct cxl *adapter)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) struct pci_dev *pdev = to_pci_dev(adapter->dev.parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) if (cxl_is_power9())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) pnv_pci_set_tunnel_bar(pdev, 0x00020000E0000000ull, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) cxl_native_release_psl_err_irq(adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) cxl_unmap_adapter_regs(adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533) pci_disable_device(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) static void cxl_stop_trace_psl9(struct cxl *adapter)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) int traceid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) u64 trace_state, trace_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) struct pci_dev *dev = to_pci_dev(adapter->dev.parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) /* read each tracearray state and issue mmio to stop them is needed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) for (traceid = 0; traceid <= CXL_PSL9_TRACEID_MAX; ++traceid) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) trace_state = cxl_p1_read(adapter, CXL_PSL9_CTCCFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) trace_mask = (0x3ULL << (62 - traceid * 2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) trace_state = (trace_state & trace_mask) >> (62 - traceid * 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) dev_dbg(&dev->dev, "cxl: Traceid-%d trace_state=0x%0llX\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) traceid, trace_state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) /* issue mmio if the trace array isn't in FIN state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) if (trace_state != CXL_PSL9_TRACESTATE_FIN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) cxl_p1_write(adapter, CXL_PSL9_TRACECFG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) 0x8400000000000000ULL | traceid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557) static void cxl_stop_trace_psl8(struct cxl *adapter)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) int slice;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) /* Stop the trace */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) cxl_p1_write(adapter, CXL_PSL_TRACE, 0x8000000000000017LL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) /* Stop the slice traces */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) spin_lock(&adapter->afu_list_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) for (slice = 0; slice < adapter->slices; slice++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) if (adapter->afu[slice])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) cxl_p1n_write(adapter->afu[slice], CXL_PSL_SLICE_TRACE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569) 0x8000000000000000LL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) spin_unlock(&adapter->afu_list_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574) static const struct cxl_service_layer_ops psl9_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) .adapter_regs_init = init_implementation_adapter_regs_psl9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) .invalidate_all = cxl_invalidate_all_psl9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) .afu_regs_init = init_implementation_afu_regs_psl9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) .sanitise_afu_regs = sanitise_afu_regs_psl9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) .register_serr_irq = cxl_native_register_serr_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580) .release_serr_irq = cxl_native_release_serr_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581) .handle_interrupt = cxl_irq_psl9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582) .fail_irq = cxl_fail_irq_psl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) .activate_dedicated_process = cxl_activate_dedicated_process_psl9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584) .attach_afu_directed = cxl_attach_afu_directed_psl9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585) .attach_dedicated_process = cxl_attach_dedicated_process_psl9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) .update_dedicated_ivtes = cxl_update_dedicated_ivtes_psl9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) .debugfs_add_adapter_regs = cxl_debugfs_add_adapter_regs_psl9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) .debugfs_add_afu_regs = cxl_debugfs_add_afu_regs_psl9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589) .psl_irq_dump_registers = cxl_native_irq_dump_regs_psl9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590) .err_irq_dump_registers = cxl_native_err_irq_dump_regs_psl9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591) .debugfs_stop_trace = cxl_stop_trace_psl9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) .timebase_read = timebase_read_psl9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593) .capi_mode = OPAL_PHB_CAPI_MODE_CAPI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594) .needs_reset_before_disable = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597) static const struct cxl_service_layer_ops psl8_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598) .adapter_regs_init = init_implementation_adapter_regs_psl8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599) .invalidate_all = cxl_invalidate_all_psl8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) .afu_regs_init = init_implementation_afu_regs_psl8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601) .sanitise_afu_regs = sanitise_afu_regs_psl8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602) .register_serr_irq = cxl_native_register_serr_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603) .release_serr_irq = cxl_native_release_serr_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604) .handle_interrupt = cxl_irq_psl8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605) .fail_irq = cxl_fail_irq_psl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606) .activate_dedicated_process = cxl_activate_dedicated_process_psl8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607) .attach_afu_directed = cxl_attach_afu_directed_psl8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608) .attach_dedicated_process = cxl_attach_dedicated_process_psl8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609) .update_dedicated_ivtes = cxl_update_dedicated_ivtes_psl8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610) .debugfs_add_adapter_regs = cxl_debugfs_add_adapter_regs_psl8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) .debugfs_add_afu_regs = cxl_debugfs_add_afu_regs_psl8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612) .psl_irq_dump_registers = cxl_native_irq_dump_regs_psl8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613) .err_irq_dump_registers = cxl_native_err_irq_dump_regs_psl8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614) .debugfs_stop_trace = cxl_stop_trace_psl8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615) .write_timebase_ctrl = write_timebase_ctrl_psl8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616) .timebase_read = timebase_read_psl8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617) .capi_mode = OPAL_PHB_CAPI_MODE_CAPI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618) .needs_reset_before_disable = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621) static void set_sl_ops(struct cxl *adapter, struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623) if (cxl_is_power8()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) dev_info(&dev->dev, "Device uses a PSL8\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625) adapter->native->sl_ops = &psl8_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627) dev_info(&dev->dev, "Device uses a PSL9\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628) adapter->native->sl_ops = &psl9_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633) static struct cxl *cxl_pci_init_adapter(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635) struct cxl *adapter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638) adapter = cxl_alloc_adapter();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639) if (!adapter)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640) return ERR_PTR(-ENOMEM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642) adapter->native = kzalloc(sizeof(struct cxl_native), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643) if (!adapter->native) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644) rc = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645) goto err_release;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648) set_sl_ops(adapter, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650) /* Set defaults for parameters which need to persist over
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651) * configure/reconfigure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653) adapter->perst_loads_image = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654) adapter->perst_same_image = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656) rc = cxl_configure_adapter(adapter, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657) if (rc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658) pci_disable_device(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659) goto err_release;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662) /* Don't care if this one fails: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663) cxl_debugfs_adapter_add(adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666) * After we call this function we must not free the adapter directly,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667) * even if it returns an error!
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669) if ((rc = cxl_register_adapter(adapter)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670) goto err_put1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672) if ((rc = cxl_sysfs_adapter_add(adapter)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673) goto err_put1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675) /* Release the context lock as adapter is configured */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676) cxl_adapter_context_unlock(adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678) return adapter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680) err_put1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681) /* This should mirror cxl_remove_adapter, except without the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682) * sysfs parts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684) cxl_debugfs_adapter_remove(adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685) cxl_deconfigure_adapter(adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686) device_unregister(&adapter->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687) return ERR_PTR(rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689) err_release:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690) cxl_release_adapter(&adapter->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691) return ERR_PTR(rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694) static void cxl_pci_remove_adapter(struct cxl *adapter)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696) pr_devel("cxl_remove_adapter\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698) cxl_sysfs_adapter_remove(adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699) cxl_debugfs_adapter_remove(adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702) * Flush adapter datacache as its about to be removed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704) cxl_data_cache_flush(adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706) cxl_deconfigure_adapter(adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1707)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1708) device_unregister(&adapter->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1709) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1710)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1711) #define CXL_MAX_PCIEX_PARENT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1712)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1713) int cxl_slot_is_switched(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1714) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1715) struct device_node *np;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1716) int depth = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1717)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1718) if (!(np = pci_device_to_OF_node(dev))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1719) pr_err("cxl: np = NULL\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1720) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1721) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1722) of_node_get(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1723) while (np) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1724) np = of_get_next_parent(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1725) if (!of_node_is_type(np, "pciex"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1726) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1727) depth++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1728) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1729) of_node_put(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1730) return (depth > CXL_MAX_PCIEX_PARENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1731) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1732)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1733) static int cxl_probe(struct pci_dev *dev, const struct pci_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1734) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1735) struct cxl *adapter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1736) int slice;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1737) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1738)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1739) if (cxl_pci_is_vphb_device(dev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1740) dev_dbg(&dev->dev, "cxl_init_adapter: Ignoring cxl vphb device\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1741) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1742) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1743)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1744) if (cxl_slot_is_switched(dev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1745) dev_info(&dev->dev, "Ignoring card on incompatible PCI slot\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1746) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1747) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1748)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1749) if (cxl_is_power9() && !radix_enabled()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1750) dev_info(&dev->dev, "Only Radix mode supported\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1751) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1752) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1753)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1754) if (cxl_verbose)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1755) dump_cxl_config_space(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1756)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1757) adapter = cxl_pci_init_adapter(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1758) if (IS_ERR(adapter)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1759) dev_err(&dev->dev, "cxl_init_adapter failed: %li\n", PTR_ERR(adapter));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1760) return PTR_ERR(adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1761) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1762)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1763) for (slice = 0; slice < adapter->slices; slice++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1764) if ((rc = pci_init_afu(adapter, slice, dev))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1765) dev_err(&dev->dev, "AFU %i failed to initialise: %i\n", slice, rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1766) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1767) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1768)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1769) rc = cxl_afu_select_best_mode(adapter->afu[slice]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1770) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1771) dev_err(&dev->dev, "AFU %i failed to start: %i\n", slice, rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1772) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1773)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1774) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1775) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1776)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1777) static void cxl_remove(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1778) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1779) struct cxl *adapter = pci_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1780) struct cxl_afu *afu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1781) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1782)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1783) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1784) * Lock to prevent someone grabbing a ref through the adapter list as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1785) * we are removing it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1786) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1787) for (i = 0; i < adapter->slices; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1788) afu = adapter->afu[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1789) cxl_pci_remove_afu(afu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1790) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1791) cxl_pci_remove_adapter(adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1792) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1793)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1794) static pci_ers_result_t cxl_vphb_error_detected(struct cxl_afu *afu,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1795) pci_channel_state_t state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1796) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1797) struct pci_dev *afu_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1798) pci_ers_result_t result = PCI_ERS_RESULT_NEED_RESET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1799) pci_ers_result_t afu_result = PCI_ERS_RESULT_NEED_RESET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1800)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1801) /* There should only be one entry, but go through the list
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1802) * anyway
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1803) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1804) if (afu == NULL || afu->phb == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1805) return result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1806)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1807) list_for_each_entry(afu_dev, &afu->phb->bus->devices, bus_list) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1808) if (!afu_dev->driver)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1809) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1810)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1811) afu_dev->error_state = state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1812)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1813) if (afu_dev->driver->err_handler)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1814) afu_result = afu_dev->driver->err_handler->error_detected(afu_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1815) state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1816) /* Disconnect trumps all, NONE trumps NEED_RESET */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1817) if (afu_result == PCI_ERS_RESULT_DISCONNECT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1818) result = PCI_ERS_RESULT_DISCONNECT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1819) else if ((afu_result == PCI_ERS_RESULT_NONE) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1820) (result == PCI_ERS_RESULT_NEED_RESET))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1821) result = PCI_ERS_RESULT_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1822) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1823) return result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1824) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1825)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1826) static pci_ers_result_t cxl_pci_error_detected(struct pci_dev *pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1827) pci_channel_state_t state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1828) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1829) struct cxl *adapter = pci_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1830) struct cxl_afu *afu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1831) pci_ers_result_t result = PCI_ERS_RESULT_NEED_RESET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1832) pci_ers_result_t afu_result = PCI_ERS_RESULT_NEED_RESET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1833) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1834)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1835) /* At this point, we could still have an interrupt pending.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1836) * Let's try to get them out of the way before they do
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1837) * anything we don't like.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1838) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1839) schedule();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1840)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1841) /* If we're permanently dead, give up. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1842) if (state == pci_channel_io_perm_failure) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1843) spin_lock(&adapter->afu_list_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1844) for (i = 0; i < adapter->slices; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1845) afu = adapter->afu[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1846) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1847) * Tell the AFU drivers; but we don't care what they
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1848) * say, we're going away.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1849) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1850) cxl_vphb_error_detected(afu, state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1851) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1852) spin_unlock(&adapter->afu_list_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1853) return PCI_ERS_RESULT_DISCONNECT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1854) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1855)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1856) /* Are we reflashing?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1857) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1858) * If we reflash, we could come back as something entirely
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1859) * different, including a non-CAPI card. As such, by default
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1860) * we don't participate in the process. We'll be unbound and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1861) * the slot re-probed. (TODO: check EEH doesn't blindly rebind
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1862) * us!)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1863) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1864) * However, this isn't the entire story: for reliablity
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1865) * reasons, we usually want to reflash the FPGA on PERST in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1866) * order to get back to a more reliable known-good state.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1867) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1868) * This causes us a bit of a problem: if we reflash we can't
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1869) * trust that we'll come back the same - we could have a new
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1870) * image and been PERSTed in order to load that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1871) * image. However, most of the time we actually *will* come
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1872) * back the same - for example a regular EEH event.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1873) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1874) * Therefore, we allow the user to assert that the image is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1875) * indeed the same and that we should continue on into EEH
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1876) * anyway.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1877) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1878) if (adapter->perst_loads_image && !adapter->perst_same_image) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1879) /* TODO take the PHB out of CXL mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1880) dev_info(&pdev->dev, "reflashing, so opting out of EEH!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1881) return PCI_ERS_RESULT_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1882) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1883)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1884) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1885) * At this point, we want to try to recover. We'll always
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1886) * need a complete slot reset: we don't trust any other reset.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1887) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1888) * Now, we go through each AFU:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1889) * - We send the driver, if bound, an error_detected callback.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1890) * We expect it to clean up, but it can also tell us to give
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1891) * up and permanently detach the card. To simplify things, if
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1892) * any bound AFU driver doesn't support EEH, we give up on EEH.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1893) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1894) * - We detach all contexts associated with the AFU. This
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1895) * does not free them, but puts them into a CLOSED state
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1896) * which causes any the associated files to return useful
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1897) * errors to userland. It also unmaps, but does not free,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1898) * any IRQs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1899) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1900) * - We clean up our side: releasing and unmapping resources we hold
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1901) * so we can wire them up again when the hardware comes back up.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1902) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1903) * Driver authors should note:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1904) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1905) * - Any contexts you create in your kernel driver (except
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1906) * those associated with anonymous file descriptors) are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1907) * your responsibility to free and recreate. Likewise with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1908) * any attached resources.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1909) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1910) * - We will take responsibility for re-initialising the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1911) * device context (the one set up for you in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1912) * cxl_pci_enable_device_hook and accessed through
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1913) * cxl_get_context). If you've attached IRQs or other
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1914) * resources to it, they remains yours to free.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1915) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1916) * You can call the same functions to release resources as you
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1917) * normally would: we make sure that these functions continue
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1918) * to work when the hardware is down.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1919) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1920) * Two examples:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1921) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1922) * 1) If you normally free all your resources at the end of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1923) * each request, or if you use anonymous FDs, your
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1924) * error_detected callback can simply set a flag to tell
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1925) * your driver not to start any new calls. You can then
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1926) * clear the flag in the resume callback.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1927) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1928) * 2) If you normally allocate your resources on startup:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1929) * * Set a flag in error_detected as above.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1930) * * Let CXL detach your contexts.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1931) * * In slot_reset, free the old resources and allocate new ones.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1932) * * In resume, clear the flag to allow things to start.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1933) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1934)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1935) /* Make sure no one else changes the afu list */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1936) spin_lock(&adapter->afu_list_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1937)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1938) for (i = 0; i < adapter->slices; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1939) afu = adapter->afu[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1940)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1941) if (afu == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1942) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1943)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1944) afu_result = cxl_vphb_error_detected(afu, state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1945) cxl_context_detach_all(afu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1946) cxl_ops->afu_deactivate_mode(afu, afu->current_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1947) pci_deconfigure_afu(afu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1948)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1949) /* Disconnect trumps all, NONE trumps NEED_RESET */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1950) if (afu_result == PCI_ERS_RESULT_DISCONNECT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1951) result = PCI_ERS_RESULT_DISCONNECT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1952) else if ((afu_result == PCI_ERS_RESULT_NONE) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1953) (result == PCI_ERS_RESULT_NEED_RESET))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1954) result = PCI_ERS_RESULT_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1955) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1956) spin_unlock(&adapter->afu_list_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1957)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1958) /* should take the context lock here */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1959) if (cxl_adapter_context_lock(adapter) != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1960) dev_warn(&adapter->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1961) "Couldn't take context lock with %d active-contexts\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1962) atomic_read(&adapter->contexts_num));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1963)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1964) cxl_deconfigure_adapter(adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1965)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1966) return result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1967) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1968)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1969) static pci_ers_result_t cxl_pci_slot_reset(struct pci_dev *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1970) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1971) struct cxl *adapter = pci_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1972) struct cxl_afu *afu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1973) struct cxl_context *ctx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1974) struct pci_dev *afu_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1975) pci_ers_result_t afu_result = PCI_ERS_RESULT_RECOVERED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1976) pci_ers_result_t result = PCI_ERS_RESULT_RECOVERED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1977) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1978)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1979) if (cxl_configure_adapter(adapter, pdev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1980) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1981)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1982) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1983) * Unlock context activation for the adapter. Ideally this should be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1984) * done in cxl_pci_resume but cxlflash module tries to activate the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1985) * master context as part of slot_reset callback.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1986) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1987) cxl_adapter_context_unlock(adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1988)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1989) spin_lock(&adapter->afu_list_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1990) for (i = 0; i < adapter->slices; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1991) afu = adapter->afu[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1992)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1993) if (afu == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1994) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1995)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1996) if (pci_configure_afu(afu, adapter, pdev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1997) goto err_unlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1998)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1999) if (cxl_afu_select_best_mode(afu))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2000) goto err_unlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2002) if (afu->phb == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2003) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2005) list_for_each_entry(afu_dev, &afu->phb->bus->devices, bus_list) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2006) /* Reset the device context.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2007) * TODO: make this less disruptive
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2008) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2009) ctx = cxl_get_context(afu_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2010)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2011) if (ctx && cxl_release_context(ctx))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2012) goto err_unlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2013)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2014) ctx = cxl_dev_context_init(afu_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2015) if (IS_ERR(ctx))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2016) goto err_unlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2017)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2018) afu_dev->dev.archdata.cxl_ctx = ctx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2019)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2020) if (cxl_ops->afu_check_and_enable(afu))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2021) goto err_unlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2022)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2023) afu_dev->error_state = pci_channel_io_normal;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2025) /* If there's a driver attached, allow it to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2026) * chime in on recovery. Drivers should check
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2027) * if everything has come back OK, but
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2028) * shouldn't start new work until we call
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2029) * their resume function.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2030) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2031) if (!afu_dev->driver)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2032) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2033)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2034) if (afu_dev->driver->err_handler &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2035) afu_dev->driver->err_handler->slot_reset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2036) afu_result = afu_dev->driver->err_handler->slot_reset(afu_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2037)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2038) if (afu_result == PCI_ERS_RESULT_DISCONNECT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2039) result = PCI_ERS_RESULT_DISCONNECT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2040) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2041) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2042)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2043) spin_unlock(&adapter->afu_list_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2044) return result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2045)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2046) err_unlock:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2047) spin_unlock(&adapter->afu_list_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2048)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2049) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2050) /* All the bits that happen in both error_detected and cxl_remove
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2051) * should be idempotent, so we don't need to worry about leaving a mix
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2052) * of unconfigured and reconfigured resources.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2053) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2054) dev_err(&pdev->dev, "EEH recovery failed. Asking to be disconnected.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2055) return PCI_ERS_RESULT_DISCONNECT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2056) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2057)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2058) static void cxl_pci_resume(struct pci_dev *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2059) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2060) struct cxl *adapter = pci_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2061) struct cxl_afu *afu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2062) struct pci_dev *afu_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2063) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2064)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2065) /* Everything is back now. Drivers should restart work now.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2066) * This is not the place to be checking if everything came back up
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2067) * properly, because there's no return value: do that in slot_reset.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2068) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2069) spin_lock(&adapter->afu_list_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2070) for (i = 0; i < adapter->slices; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2071) afu = adapter->afu[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2072)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2073) if (afu == NULL || afu->phb == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2074) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2075)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2076) list_for_each_entry(afu_dev, &afu->phb->bus->devices, bus_list) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2077) if (afu_dev->driver && afu_dev->driver->err_handler &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2078) afu_dev->driver->err_handler->resume)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2079) afu_dev->driver->err_handler->resume(afu_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2080) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2081) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2082) spin_unlock(&adapter->afu_list_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2083) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2084)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2085) static const struct pci_error_handlers cxl_err_handler = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2086) .error_detected = cxl_pci_error_detected,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2087) .slot_reset = cxl_pci_slot_reset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2088) .resume = cxl_pci_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2089) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2090)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2091) struct pci_driver cxl_pci_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2092) .name = "cxl-pci",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2093) .id_table = cxl_pci_tbl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2094) .probe = cxl_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2095) .remove = cxl_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2096) .shutdown = cxl_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2097) .err_handler = &cxl_err_handler,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2098) };
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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