Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Copyright 2014 IBM Corp.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) #include <linux/spinlock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/mutex.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/list.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/mm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/idr.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include <linux/sched/task.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #include <asm/cputable.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #include <asm/mmu.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #include <misc/cxl-base.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #include "cxl.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #include "trace.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) static DEFINE_SPINLOCK(adapter_idr_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) static DEFINE_IDR(cxl_adapter_idr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) uint cxl_verbose;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) module_param_named(verbose, cxl_verbose, uint, 0600);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) MODULE_PARM_DESC(verbose, "Enable verbose dmesg output");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) const struct cxl_backend_ops *cxl_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) int cxl_afu_slbia(struct cxl_afu *afu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 	unsigned long timeout = jiffies + (HZ * CXL_TIMEOUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 	pr_devel("cxl_afu_slbia issuing SLBIA command\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 	cxl_p2n_write(afu, CXL_SLBIA_An, CXL_TLB_SLB_IQ_ALL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 	while (cxl_p2n_read(afu, CXL_SLBIA_An) & CXL_TLB_SLB_P) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 		if (time_after_eq(jiffies, timeout)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 			dev_warn(&afu->dev, "WARNING: CXL AFU SLBIA timed out!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 			return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 		/* If the adapter has gone down, we can assume that we
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 		 * will PERST it and that will invalidate everything.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 		 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 		if (!cxl_ops->link_ok(afu->adapter, afu))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 			return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 		cpu_relax();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) static inline void _cxl_slbia(struct cxl_context *ctx, struct mm_struct *mm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 	if (ctx->mm != mm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	pr_devel("%s matched mm - card: %i afu: %i pe: %i\n", __func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 		 ctx->afu->adapter->adapter_num, ctx->afu->slice, ctx->pe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 	spin_lock_irqsave(&ctx->sste_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	trace_cxl_slbia(ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	memset(ctx->sstp, 0, ctx->sst_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	spin_unlock_irqrestore(&ctx->sste_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	mb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	cxl_afu_slbia(ctx->afu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) static inline void cxl_slbia_core(struct mm_struct *mm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	struct cxl *adapter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	struct cxl_afu *afu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	struct cxl_context *ctx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	int card, slice, id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	pr_devel("%s called\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	spin_lock(&adapter_idr_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	idr_for_each_entry(&cxl_adapter_idr, adapter, card) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 		/* XXX: Make this lookup faster with link from mm to ctx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 		spin_lock(&adapter->afu_list_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 		for (slice = 0; slice < adapter->slices; slice++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 			afu = adapter->afu[slice];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 			if (!afu || !afu->enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 				continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 			rcu_read_lock();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 			idr_for_each_entry(&afu->contexts_idr, ctx, id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 				_cxl_slbia(ctx, mm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 			rcu_read_unlock();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 		spin_unlock(&adapter->afu_list_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	spin_unlock(&adapter_idr_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) static struct cxl_calls cxl_calls = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	.cxl_slbia = cxl_slbia_core,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	.owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) int cxl_alloc_sst(struct cxl_context *ctx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	unsigned long vsid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	u64 ea_mask, size, sstp0, sstp1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	sstp0 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	sstp1 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	ctx->sst_size = PAGE_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	ctx->sst_lru = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	ctx->sstp = (struct cxl_sste *)get_zeroed_page(GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	if (!ctx->sstp) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 		pr_err("cxl_alloc_sst: Unable to allocate segment table\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	pr_devel("SSTP allocated at 0x%p\n", ctx->sstp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	vsid  = get_kernel_vsid((u64)ctx->sstp, mmu_kernel_ssize) << 12;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	sstp0 |= (u64)mmu_kernel_ssize << CXL_SSTP0_An_B_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	sstp0 |= (SLB_VSID_KERNEL | mmu_psize_defs[mmu_linear_psize].sllp) << 50;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	size = (((u64)ctx->sst_size >> 8) - 1) << CXL_SSTP0_An_SegTableSize_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	if (unlikely(size & ~CXL_SSTP0_An_SegTableSize_MASK)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 		WARN(1, "Impossible segment table size\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	sstp0 |= size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	if (mmu_kernel_ssize == MMU_SEGSIZE_256M)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 		ea_mask = 0xfffff00ULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 		ea_mask = 0xffffffff00ULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	sstp0 |=  vsid >>     (50-14);  /*   Top 14 bits of VSID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	sstp1 |= (vsid << (64-(50-14))) & ~ea_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	sstp1 |= (u64)ctx->sstp & ea_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	sstp1 |= CXL_SSTP1_An_V;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	pr_devel("Looked up %#llx: slbfee. %#llx (ssize: %x, vsid: %#lx), copied to SSTP0: %#llx, SSTP1: %#llx\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 			(u64)ctx->sstp, (u64)ctx->sstp & ESID_MASK, mmu_kernel_ssize, vsid, sstp0, sstp1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	/* Store calculated sstp hardware points for use later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	ctx->sstp0 = sstp0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	ctx->sstp1 = sstp1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) /* print buffer content as integers when debugging */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) void cxl_dump_debug_buffer(void *buf, size_t buf_len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #ifdef DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	int i, *ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	 * We want to regroup up to 4 integers per line, which means they
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	 * need to be in the same pr_devel() statement
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	ptr = (int *) buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	for (i = 0; i * 4 < buf_len; i += 4) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 		if ((i + 3) * 4 < buf_len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 			pr_devel("%.8x %.8x %.8x %.8x\n", ptr[i], ptr[i + 1],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 				ptr[i + 2], ptr[i + 3]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 		else if ((i + 2) * 4 < buf_len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 			pr_devel("%.8x %.8x %.8x\n", ptr[i], ptr[i + 1],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 				ptr[i + 2]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 		else if ((i + 1) * 4 < buf_len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 			pr_devel("%.8x %.8x\n", ptr[i], ptr[i + 1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 		else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 			pr_devel("%.8x\n", ptr[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #endif /* DEBUG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) /* Find a CXL adapter by it's number and increase it's refcount */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) struct cxl *get_cxl_adapter(int num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	struct cxl *adapter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	spin_lock(&adapter_idr_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	if ((adapter = idr_find(&cxl_adapter_idr, num)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 		get_device(&adapter->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	spin_unlock(&adapter_idr_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	return adapter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) static int cxl_alloc_adapter_nr(struct cxl *adapter)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	idr_preload(GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	spin_lock(&adapter_idr_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	i = idr_alloc(&cxl_adapter_idr, adapter, 0, 0, GFP_NOWAIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	spin_unlock(&adapter_idr_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 	idr_preload_end();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	if (i < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 		return i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	adapter->adapter_num = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) void cxl_remove_adapter_nr(struct cxl *adapter)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 	idr_remove(&cxl_adapter_idr, adapter->adapter_num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) struct cxl *cxl_alloc_adapter(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	struct cxl *adapter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	if (!(adapter = kzalloc(sizeof(struct cxl), GFP_KERNEL)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 		return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 	spin_lock_init(&adapter->afu_list_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 	if (cxl_alloc_adapter_nr(adapter))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 		goto err1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	if (dev_set_name(&adapter->dev, "card%i", adapter->adapter_num))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 		goto err2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 	/* start with context lock taken */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 	atomic_set(&adapter->contexts_num, -1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 	return adapter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) err2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 	cxl_remove_adapter_nr(adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) err1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 	kfree(adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 	return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) struct cxl_afu *cxl_alloc_afu(struct cxl *adapter, int slice)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 	struct cxl_afu *afu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 	if (!(afu = kzalloc(sizeof(struct cxl_afu), GFP_KERNEL)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 		return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 	afu->adapter = adapter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 	afu->dev.parent = &adapter->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 	afu->dev.release = cxl_ops->release_afu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 	afu->slice = slice;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 	idr_init(&afu->contexts_idr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 	mutex_init(&afu->contexts_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 	spin_lock_init(&afu->afu_cntl_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 	atomic_set(&afu->configured_state, -1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 	afu->prefault_mode = CXL_PREFAULT_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 	afu->irqs_max = afu->adapter->user_irqs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 	return afu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) int cxl_afu_select_best_mode(struct cxl_afu *afu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 	if (afu->modes_supported & CXL_MODE_DIRECTED)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 		return cxl_ops->afu_activate_mode(afu, CXL_MODE_DIRECTED);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 	if (afu->modes_supported & CXL_MODE_DEDICATED)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 		return cxl_ops->afu_activate_mode(afu, CXL_MODE_DEDICATED);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 	dev_warn(&afu->dev, "No supported programming modes available\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 	/* We don't fail this so the user can inspect sysfs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) int cxl_adapter_context_get(struct cxl *adapter)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 	int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 	rc = atomic_inc_unless_negative(&adapter->contexts_num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 	return rc ? 0 : -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) void cxl_adapter_context_put(struct cxl *adapter)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 	atomic_dec_if_positive(&adapter->contexts_num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) int cxl_adapter_context_lock(struct cxl *adapter)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 	int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 	/* no active contexts -> contexts_num == 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 	rc = atomic_cmpxchg(&adapter->contexts_num, 0, -1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 	return rc ? -EBUSY : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) void cxl_adapter_context_unlock(struct cxl *adapter)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 	int val = atomic_cmpxchg(&adapter->contexts_num, -1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 	 * contexts lock taken -> contexts_num == -1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 	 * If not true then show a warning and force reset the lock.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 	 * This will happen when context_unlock was requested without
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 	 * doing a context_lock.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 	if (val != -1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 		atomic_set(&adapter->contexts_num, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 		WARN(1, "Adapter context unlocked with %d active contexts",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 		     val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) static int __init init_cxl(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 	int rc = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 	if (!tlbie_capable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 	if ((rc = cxl_file_init()))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 		return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 	cxl_debugfs_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 	 * we don't register the callback on P9. slb callack is only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 	 * used for the PSL8 MMU and CX4.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 	if (cxl_is_power8()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 		rc = register_cxl_calls(&cxl_calls);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 		if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 			goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 	if (cpu_has_feature(CPU_FTR_HVMODE)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 		cxl_ops = &cxl_native_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 		rc = pci_register_driver(&cxl_pci_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) #ifdef CONFIG_PPC_PSERIES
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 	else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 		cxl_ops = &cxl_guest_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 		rc = platform_driver_register(&cxl_of_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 	if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 		goto err1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) err1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 	if (cxl_is_power8())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 		unregister_cxl_calls(&cxl_calls);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 	cxl_debugfs_exit();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 	cxl_file_exit();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) 	return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) static void exit_cxl(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) 	if (cpu_has_feature(CPU_FTR_HVMODE))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) 		pci_unregister_driver(&cxl_pci_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) #ifdef CONFIG_PPC_PSERIES
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) 		platform_driver_unregister(&cxl_of_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) 	cxl_debugfs_exit();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) 	cxl_file_exit();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) 	if (cxl_is_power8())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) 		unregister_cxl_calls(&cxl_calls);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) 	idr_destroy(&cxl_adapter_idr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) module_init(init_cxl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) module_exit(exit_cxl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) MODULE_DESCRIPTION("IBM Coherent Accelerator");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) MODULE_AUTHOR("Ian Munsie <imunsie@au1.ibm.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) MODULE_LICENSE("GPL");