^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright 2015 IBM Corp.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <linux/spinlock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/uaccess.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include "cxl.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include "hcalls.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include "trace.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define CXL_ERROR_DETECTED_EVENT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define CXL_SLOT_RESET_EVENT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define CXL_RESUME_EVENT 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) static void pci_error_handlers(struct cxl_afu *afu,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) int bus_error_event,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) pci_channel_state_t state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) struct pci_dev *afu_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) if (afu->phb == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) list_for_each_entry(afu_dev, &afu->phb->bus->devices, bus_list) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) if (!afu_dev->driver)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) switch (bus_error_event) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) case CXL_ERROR_DETECTED_EVENT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) afu_dev->error_state = state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) if (afu_dev->driver->err_handler &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) afu_dev->driver->err_handler->error_detected)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) afu_dev->driver->err_handler->error_detected(afu_dev, state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) case CXL_SLOT_RESET_EVENT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) afu_dev->error_state = state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) if (afu_dev->driver->err_handler &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) afu_dev->driver->err_handler->slot_reset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) afu_dev->driver->err_handler->slot_reset(afu_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) case CXL_RESUME_EVENT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) if (afu_dev->driver->err_handler &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) afu_dev->driver->err_handler->resume)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) afu_dev->driver->err_handler->resume(afu_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) static irqreturn_t guest_handle_psl_slice_error(struct cxl_context *ctx, u64 dsisr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) u64 errstat)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) pr_devel("in %s\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) dev_crit(&ctx->afu->dev, "PSL ERROR STATUS: 0x%.16llx\n", errstat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) return cxl_ops->ack_irq(ctx, 0, errstat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) static ssize_t guest_collect_vpd(struct cxl *adapter, struct cxl_afu *afu,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) void *buf, size_t len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) unsigned int entries, mod;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) unsigned long **vpd_buf = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) struct sg_list *le;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) int rc = 0, i, tocopy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) u64 out = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) if (buf == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) /* number of entries in the list */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) entries = len / SG_BUFFER_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) mod = len % SG_BUFFER_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) if (mod)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) entries++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) if (entries > SG_MAX_ENTRIES) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) entries = SG_MAX_ENTRIES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) len = SG_MAX_ENTRIES * SG_BUFFER_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) mod = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) vpd_buf = kcalloc(entries, sizeof(unsigned long *), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) if (!vpd_buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) le = (struct sg_list *)get_zeroed_page(GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) if (!le) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) rc = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) goto err1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) for (i = 0; i < entries; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) vpd_buf[i] = (unsigned long *)get_zeroed_page(GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) if (!vpd_buf[i]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) rc = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) goto err2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) le[i].phys_addr = cpu_to_be64(virt_to_phys(vpd_buf[i]));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) le[i].len = cpu_to_be64(SG_BUFFER_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) if ((i == (entries - 1)) && mod)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) le[i].len = cpu_to_be64(mod);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) if (adapter)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) rc = cxl_h_collect_vpd_adapter(adapter->guest->handle,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) virt_to_phys(le), entries, &out);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) rc = cxl_h_collect_vpd(afu->guest->handle, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) virt_to_phys(le), entries, &out);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) pr_devel("length of available (entries: %i), vpd: %#llx\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) entries, out);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) if (!rc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) * hcall returns in 'out' the size of available VPDs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) * It fills the buffer with as much data as possible.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) if (out < len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) len = out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) rc = len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) if (out) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) for (i = 0; i < entries; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) if (len < SG_BUFFER_SIZE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) tocopy = len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) tocopy = SG_BUFFER_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) memcpy(buf, vpd_buf[i], tocopy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) buf += tocopy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) len -= tocopy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) err2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) for (i = 0; i < entries; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) if (vpd_buf[i])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) free_page((unsigned long) vpd_buf[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) free_page((unsigned long) le);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) err1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) kfree(vpd_buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) static int guest_get_irq_info(struct cxl_context *ctx, struct cxl_irq_info *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) return cxl_h_collect_int_info(ctx->afu->guest->handle, ctx->process_token, info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) static irqreturn_t guest_psl_irq(int irq, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) struct cxl_context *ctx = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) struct cxl_irq_info irq_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) pr_devel("%d: received PSL interrupt %i\n", ctx->pe, irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) rc = guest_get_irq_info(ctx, &irq_info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) if (rc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) WARN(1, "Unable to get IRQ info: %i\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) rc = cxl_irq_psl8(irq, ctx, &irq_info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) static int afu_read_error_state(struct cxl_afu *afu, int *state_out)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) u64 state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) int rc = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) if (!afu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) rc = cxl_h_read_error_state(afu->guest->handle, &state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) if (!rc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) WARN_ON(state != H_STATE_NORMAL &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) state != H_STATE_DISABLE &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) state != H_STATE_TEMP_UNAVAILABLE &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) state != H_STATE_PERM_UNAVAILABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) *state_out = state & 0xffffffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) static irqreturn_t guest_slice_irq_err(int irq, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) struct cxl_afu *afu = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) u64 serr, afu_error, dsisr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) rc = cxl_h_get_fn_error_interrupt(afu->guest->handle, &serr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) if (rc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) dev_crit(&afu->dev, "Couldn't read PSL_SERR_An: %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) afu_error = cxl_p2n_read(afu, CXL_AFU_ERR_An);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) dsisr = cxl_p2n_read(afu, CXL_PSL_DSISR_An);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) cxl_afu_decode_psl_serr(afu, serr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) dev_crit(&afu->dev, "AFU_ERR_An: 0x%.16llx\n", afu_error);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) dev_crit(&afu->dev, "PSL_DSISR_An: 0x%.16llx\n", dsisr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) rc = cxl_h_ack_fn_error_interrupt(afu->guest->handle, serr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) dev_crit(&afu->dev, "Couldn't ack slice error interrupt: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) static int irq_alloc_range(struct cxl *adapter, int len, int *irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) int i, n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) struct irq_avail *cur;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) for (i = 0; i < adapter->guest->irq_nranges; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) cur = &adapter->guest->irq_avail[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) n = bitmap_find_next_zero_area(cur->bitmap, cur->range,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 0, len, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) if (n < cur->range) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) bitmap_set(cur->bitmap, n, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) *irq = cur->offset + n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) pr_devel("guest: allocate IRQs %#x->%#x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) *irq, *irq + len - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) return -ENOSPC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) static int irq_free_range(struct cxl *adapter, int irq, int len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) int i, n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) struct irq_avail *cur;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) if (len == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) return -ENOENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) for (i = 0; i < adapter->guest->irq_nranges; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) cur = &adapter->guest->irq_avail[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) if (irq >= cur->offset &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) (irq + len) <= (cur->offset + cur->range)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) n = irq - cur->offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) bitmap_clear(cur->bitmap, n, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) pr_devel("guest: release IRQs %#x->%#x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) irq, irq + len - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) return -ENOENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) static int guest_reset(struct cxl *adapter)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) struct cxl_afu *afu = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) int i, rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) pr_devel("Adapter reset request\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) spin_lock(&adapter->afu_list_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) for (i = 0; i < adapter->slices; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) if ((afu = adapter->afu[i])) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) pci_error_handlers(afu, CXL_ERROR_DETECTED_EVENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) pci_channel_io_frozen);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) cxl_context_detach_all(afu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) rc = cxl_h_reset_adapter(adapter->guest->handle);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) for (i = 0; i < adapter->slices; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) if (!rc && (afu = adapter->afu[i])) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) pci_error_handlers(afu, CXL_SLOT_RESET_EVENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) pci_channel_io_normal);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) pci_error_handlers(afu, CXL_RESUME_EVENT, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) spin_unlock(&adapter->afu_list_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) static int guest_alloc_one_irq(struct cxl *adapter)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) spin_lock(&adapter->guest->irq_alloc_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) if (irq_alloc_range(adapter, 1, &irq))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) irq = -ENOSPC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) spin_unlock(&adapter->guest->irq_alloc_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) return irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) static void guest_release_one_irq(struct cxl *adapter, int irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) spin_lock(&adapter->guest->irq_alloc_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) irq_free_range(adapter, irq, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) spin_unlock(&adapter->guest->irq_alloc_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) static int guest_alloc_irq_ranges(struct cxl_irq_ranges *irqs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) struct cxl *adapter, unsigned int num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) int i, try, irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) memset(irqs, 0, sizeof(struct cxl_irq_ranges));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) spin_lock(&adapter->guest->irq_alloc_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) for (i = 0; i < CXL_IRQ_RANGES && num; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) try = num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) while (try) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) if (irq_alloc_range(adapter, try, &irq) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) try /= 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) if (!try)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) irqs->offset[i] = irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) irqs->range[i] = try;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) num -= try;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) if (num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) spin_unlock(&adapter->guest->irq_alloc_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) error:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) for (i = 0; i < CXL_IRQ_RANGES; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) irq_free_range(adapter, irqs->offset[i], irqs->range[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) spin_unlock(&adapter->guest->irq_alloc_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) return -ENOSPC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) static void guest_release_irq_ranges(struct cxl_irq_ranges *irqs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) struct cxl *adapter)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) spin_lock(&adapter->guest->irq_alloc_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) for (i = 0; i < CXL_IRQ_RANGES; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) irq_free_range(adapter, irqs->offset[i], irqs->range[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) spin_unlock(&adapter->guest->irq_alloc_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) static int guest_register_serr_irq(struct cxl_afu *afu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) afu->err_irq_name = kasprintf(GFP_KERNEL, "cxl-%s-err",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) dev_name(&afu->dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) if (!afu->err_irq_name)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) if (!(afu->serr_virq = cxl_map_irq(afu->adapter, afu->serr_hwirq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) guest_slice_irq_err, afu, afu->err_irq_name))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) kfree(afu->err_irq_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) afu->err_irq_name = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) static void guest_release_serr_irq(struct cxl_afu *afu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) cxl_unmap_irq(afu->serr_virq, afu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) cxl_ops->release_one_irq(afu->adapter, afu->serr_hwirq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) kfree(afu->err_irq_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) static int guest_ack_irq(struct cxl_context *ctx, u64 tfc, u64 psl_reset_mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) return cxl_h_control_faults(ctx->afu->guest->handle, ctx->process_token,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) tfc >> 32, (psl_reset_mask != 0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) static void disable_afu_irqs(struct cxl_context *ctx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) irq_hw_number_t hwirq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) unsigned int virq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) int r, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) pr_devel("Disabling AFU(%d) interrupts\n", ctx->afu->slice);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) for (r = 0; r < CXL_IRQ_RANGES; r++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) hwirq = ctx->irqs.offset[r];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) for (i = 0; i < ctx->irqs.range[r]; hwirq++, i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) virq = irq_find_mapping(NULL, hwirq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) disable_irq(virq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) static void enable_afu_irqs(struct cxl_context *ctx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) irq_hw_number_t hwirq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) unsigned int virq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) int r, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) pr_devel("Enabling AFU(%d) interrupts\n", ctx->afu->slice);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) for (r = 0; r < CXL_IRQ_RANGES; r++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) hwirq = ctx->irqs.offset[r];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) for (i = 0; i < ctx->irqs.range[r]; hwirq++, i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) virq = irq_find_mapping(NULL, hwirq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) enable_irq(virq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) static int _guest_afu_cr_readXX(int sz, struct cxl_afu *afu, int cr_idx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) u64 offset, u64 *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) unsigned long cr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) char c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) int rc = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) if (afu->crs_len < sz)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) return -ENOENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) if (unlikely(offset >= afu->crs_len))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) return -ERANGE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) cr = get_zeroed_page(GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) if (!cr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) rc = cxl_h_get_config(afu->guest->handle, cr_idx, offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) virt_to_phys((void *)cr), sz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) switch (sz) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) c = *((char *) cr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) *val = c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) *val = in_le16((u16 *)cr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) case 4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) *val = in_le32((unsigned *)cr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) case 8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) *val = in_le64((u64 *)cr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) WARN_ON(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) free_page(cr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) static int guest_afu_cr_read32(struct cxl_afu *afu, int cr_idx, u64 offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) u32 *out)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) u64 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) rc = _guest_afu_cr_readXX(4, afu, cr_idx, offset, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) if (!rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) *out = (u32) val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) static int guest_afu_cr_read16(struct cxl_afu *afu, int cr_idx, u64 offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) u16 *out)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) u64 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) rc = _guest_afu_cr_readXX(2, afu, cr_idx, offset, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) if (!rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) *out = (u16) val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) static int guest_afu_cr_read8(struct cxl_afu *afu, int cr_idx, u64 offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) u8 *out)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) u64 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) rc = _guest_afu_cr_readXX(1, afu, cr_idx, offset, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) if (!rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) *out = (u8) val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) static int guest_afu_cr_read64(struct cxl_afu *afu, int cr_idx, u64 offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) u64 *out)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) return _guest_afu_cr_readXX(8, afu, cr_idx, offset, out);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) static int guest_afu_cr_write32(struct cxl_afu *afu, int cr, u64 off, u32 in)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) /* config record is not writable from guest */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) return -EPERM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) static int guest_afu_cr_write16(struct cxl_afu *afu, int cr, u64 off, u16 in)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) /* config record is not writable from guest */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) return -EPERM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) static int guest_afu_cr_write8(struct cxl_afu *afu, int cr, u64 off, u8 in)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) /* config record is not writable from guest */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) return -EPERM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) static int attach_afu_directed(struct cxl_context *ctx, u64 wed, u64 amr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) struct cxl_process_element_hcall *elem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) struct cxl *adapter = ctx->afu->adapter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) const struct cred *cred;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) u32 pid, idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) int rc, r, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) u64 mmio_addr, mmio_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) __be64 flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) /* Must be 8 byte aligned and cannot cross a 4096 byte boundary */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) if (!(elem = (struct cxl_process_element_hcall *)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) get_zeroed_page(GFP_KERNEL)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) elem->version = cpu_to_be64(CXL_PROCESS_ELEMENT_VERSION);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) if (ctx->kernel) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) pid = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) flags |= CXL_PE_TRANSLATION_ENABLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) flags |= CXL_PE_PRIVILEGED_PROCESS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) if (mfmsr() & MSR_SF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) flags |= CXL_PE_64_BIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) pid = current->pid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) flags |= CXL_PE_PROBLEM_STATE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) flags |= CXL_PE_TRANSLATION_ENABLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) if (!test_tsk_thread_flag(current, TIF_32BIT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) flags |= CXL_PE_64_BIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) cred = get_current_cred();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) if (uid_eq(cred->euid, GLOBAL_ROOT_UID))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) flags |= CXL_PE_PRIVILEGED_PROCESS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) put_cred(cred);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) elem->flags = cpu_to_be64(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) elem->common.tid = cpu_to_be32(0); /* Unused */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) elem->common.pid = cpu_to_be32(pid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) elem->common.csrp = cpu_to_be64(0); /* disable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) elem->common.u.psl8.aurp0 = cpu_to_be64(0); /* disable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) elem->common.u.psl8.aurp1 = cpu_to_be64(0); /* disable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) cxl_prefault(ctx, wed);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) elem->common.u.psl8.sstp0 = cpu_to_be64(ctx->sstp0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) elem->common.u.psl8.sstp1 = cpu_to_be64(ctx->sstp1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) * Ensure we have at least one interrupt allocated to take faults for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) * kernel contexts that may not have allocated any AFU IRQs at all:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) if (ctx->irqs.range[0] == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) rc = afu_register_irqs(ctx, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) goto out_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) for (r = 0; r < CXL_IRQ_RANGES; r++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) for (i = 0; i < ctx->irqs.range[r]; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) if (r == 0 && i == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) elem->pslVirtualIsn = cpu_to_be32(ctx->irqs.offset[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) idx = ctx->irqs.offset[r] + i - adapter->guest->irq_base_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) elem->applicationVirtualIsnBitmap[idx / 8] |= 0x80 >> (idx % 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) elem->common.amr = cpu_to_be64(amr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) elem->common.wed = cpu_to_be64(wed);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) disable_afu_irqs(ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) rc = cxl_h_attach_process(ctx->afu->guest->handle, elem,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) &ctx->process_token, &mmio_addr, &mmio_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) if (rc == H_SUCCESS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) if (ctx->master || !ctx->afu->pp_psa) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) ctx->psn_phys = ctx->afu->psn_phys;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) ctx->psn_size = ctx->afu->adapter->ps_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) ctx->psn_phys = mmio_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) ctx->psn_size = mmio_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) if (ctx->afu->pp_psa && mmio_size &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) ctx->afu->pp_size == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) * There's no property in the device tree to read the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) * pp_size. We only find out at the 1st attach.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) * Compared to bare-metal, it is too late and we
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) * should really lock here. However, on powerVM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) * pp_size is really only used to display in /sys.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) * Being discussed with pHyp for their next release.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) ctx->afu->pp_size = mmio_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) /* from PAPR: process element is bytes 4-7 of process token */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) ctx->external_pe = ctx->process_token & 0xFFFFFFFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) pr_devel("CXL pe=%i is known as %i for pHyp, mmio_size=%#llx",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) ctx->pe, ctx->external_pe, ctx->psn_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) ctx->pe_inserted = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) enable_afu_irqs(ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) out_free:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) free_page((u64)elem);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) static int guest_attach_process(struct cxl_context *ctx, bool kernel, u64 wed, u64 amr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) pr_devel("in %s\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) ctx->kernel = kernel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) if (ctx->afu->current_mode == CXL_MODE_DIRECTED)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) return attach_afu_directed(ctx, wed, amr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) /* dedicated mode not supported on FW840 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) static int detach_afu_directed(struct cxl_context *ctx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) if (!ctx->pe_inserted)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) if (cxl_h_detach_process(ctx->afu->guest->handle, ctx->process_token))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) static int guest_detach_process(struct cxl_context *ctx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) pr_devel("in %s\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) trace_cxl_detach(ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) if (!cxl_ops->link_ok(ctx->afu->adapter, ctx->afu))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) if (ctx->afu->current_mode == CXL_MODE_DIRECTED)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) return detach_afu_directed(ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) static void guest_release_afu(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) struct cxl_afu *afu = to_cxl_afu(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) pr_devel("%s\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) idr_destroy(&afu->contexts_idr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) kfree(afu->guest);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) kfree(afu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) ssize_t cxl_guest_read_afu_vpd(struct cxl_afu *afu, void *buf, size_t len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) return guest_collect_vpd(NULL, afu, buf, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) #define ERR_BUFF_MAX_COPY_SIZE PAGE_SIZE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) static ssize_t guest_afu_read_err_buffer(struct cxl_afu *afu, char *buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) loff_t off, size_t count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) void *tbuf = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) int rc = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) tbuf = (void *) get_zeroed_page(GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) if (!tbuf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) rc = cxl_h_get_afu_err(afu->guest->handle,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) off & 0x7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) virt_to_phys(tbuf),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) if (count > ERR_BUFF_MAX_COPY_SIZE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) count = ERR_BUFF_MAX_COPY_SIZE - (off & 0x7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) memcpy(buf, tbuf, count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) free_page((u64)tbuf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) static int guest_afu_check_and_enable(struct cxl_afu *afu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) static bool guest_support_attributes(const char *attr_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) enum cxl_attrs type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) switch (type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) case CXL_ADAPTER_ATTRS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) if ((strcmp(attr_name, "base_image") == 0) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) (strcmp(attr_name, "load_image_on_perst") == 0) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) (strcmp(attr_name, "perst_reloads_same_image") == 0) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) (strcmp(attr_name, "image_loaded") == 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) case CXL_AFU_MASTER_ATTRS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) if ((strcmp(attr_name, "pp_mmio_off") == 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) case CXL_AFU_ATTRS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) static int activate_afu_directed(struct cxl_afu *afu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) dev_info(&afu->dev, "Activating AFU(%d) directed mode\n", afu->slice);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) afu->current_mode = CXL_MODE_DIRECTED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) afu->num_procs = afu->max_procs_virtualised;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) if ((rc = cxl_chardev_m_afu_add(afu)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) if ((rc = cxl_sysfs_afu_m_add(afu)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) if ((rc = cxl_chardev_s_afu_add(afu)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) goto err1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) err1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) cxl_sysfs_afu_m_remove(afu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) cxl_chardev_afu_remove(afu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) static int guest_afu_activate_mode(struct cxl_afu *afu, int mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) if (!mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) if (!(mode & afu->modes_supported))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) if (mode == CXL_MODE_DIRECTED)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) return activate_afu_directed(afu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) if (mode == CXL_MODE_DEDICATED)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) dev_err(&afu->dev, "Dedicated mode not supported\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) static int deactivate_afu_directed(struct cxl_afu *afu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) dev_info(&afu->dev, "Deactivating AFU(%d) directed mode\n", afu->slice);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) afu->current_mode = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) afu->num_procs = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) cxl_sysfs_afu_m_remove(afu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) cxl_chardev_afu_remove(afu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) cxl_ops->afu_reset(afu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) static int guest_afu_deactivate_mode(struct cxl_afu *afu, int mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) if (!mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) if (!(mode & afu->modes_supported))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) if (mode == CXL_MODE_DIRECTED)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) return deactivate_afu_directed(afu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) static int guest_afu_reset(struct cxl_afu *afu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) pr_devel("AFU(%d) reset request\n", afu->slice);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) return cxl_h_reset_afu(afu->guest->handle);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) static int guest_map_slice_regs(struct cxl_afu *afu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) if (!(afu->p2n_mmio = ioremap(afu->guest->p2n_phys, afu->guest->p2n_size))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) dev_err(&afu->dev, "Error mapping AFU(%d) MMIO regions\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) afu->slice);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) static void guest_unmap_slice_regs(struct cxl_afu *afu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) if (afu->p2n_mmio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) iounmap(afu->p2n_mmio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) static int afu_update_state(struct cxl_afu *afu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) int rc, cur_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) rc = afu_read_error_state(afu, &cur_state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) if (afu->guest->previous_state == cur_state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) pr_devel("AFU(%d) update state to %#x\n", afu->slice, cur_state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) switch (cur_state) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) case H_STATE_NORMAL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) afu->guest->previous_state = cur_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) case H_STATE_DISABLE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) pci_error_handlers(afu, CXL_ERROR_DETECTED_EVENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) pci_channel_io_frozen);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) cxl_context_detach_all(afu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) if ((rc = cxl_ops->afu_reset(afu)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) pr_devel("reset hcall failed %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) rc = afu_read_error_state(afu, &cur_state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) if (!rc && cur_state == H_STATE_NORMAL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) pci_error_handlers(afu, CXL_SLOT_RESET_EVENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) pci_channel_io_normal);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) pci_error_handlers(afu, CXL_RESUME_EVENT, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) afu->guest->previous_state = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) case H_STATE_TEMP_UNAVAILABLE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) afu->guest->previous_state = cur_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) case H_STATE_PERM_UNAVAILABLE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) dev_err(&afu->dev, "AFU is in permanent error state\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) pci_error_handlers(afu, CXL_ERROR_DETECTED_EVENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) pci_channel_io_perm_failure);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) afu->guest->previous_state = cur_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) pr_err("Unexpected AFU(%d) error state: %#x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) afu->slice, cur_state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) static void afu_handle_errstate(struct work_struct *work)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) struct cxl_afu_guest *afu_guest =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) container_of(to_delayed_work(work), struct cxl_afu_guest, work_err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) if (!afu_update_state(afu_guest->parent) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) afu_guest->previous_state == H_STATE_PERM_UNAVAILABLE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) if (afu_guest->handle_err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) schedule_delayed_work(&afu_guest->work_err,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) msecs_to_jiffies(3000));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) static bool guest_link_ok(struct cxl *cxl, struct cxl_afu *afu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) int state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) if (afu && (!afu_read_error_state(afu, &state))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) if (state == H_STATE_NORMAL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) static int afu_properties_look_ok(struct cxl_afu *afu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) if (afu->pp_irqs < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) dev_err(&afu->dev, "Unexpected per-process minimum interrupt value\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) if (afu->max_procs_virtualised < 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) dev_err(&afu->dev, "Unexpected max number of processes virtualised value\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) int cxl_guest_init_afu(struct cxl *adapter, int slice, struct device_node *afu_np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) struct cxl_afu *afu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) bool free = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) pr_devel("in %s - AFU(%d)\n", __func__, slice);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) if (!(afu = cxl_alloc_afu(adapter, slice)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) if (!(afu->guest = kzalloc(sizeof(struct cxl_afu_guest), GFP_KERNEL))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) kfree(afu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) if ((rc = dev_set_name(&afu->dev, "afu%i.%i",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) adapter->adapter_num,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) slice)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) goto err1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) adapter->slices++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) if ((rc = cxl_of_read_afu_handle(afu, afu_np)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) goto err1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) if ((rc = cxl_ops->afu_reset(afu)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) goto err1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) if ((rc = cxl_of_read_afu_properties(afu, afu_np)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) goto err1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) if ((rc = afu_properties_look_ok(afu)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) goto err1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) if ((rc = guest_map_slice_regs(afu)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) goto err1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) if ((rc = guest_register_serr_irq(afu)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) goto err2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) * After we call this function we must not free the afu directly, even
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) * if it returns an error!
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) if ((rc = cxl_register_afu(afu)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) goto err_put1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) if ((rc = cxl_sysfs_afu_add(afu)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) goto err_put1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) * pHyp doesn't expose the programming models supported by the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) * AFU. pHyp currently only supports directed mode. If it adds
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) * dedicated mode later, this version of cxl has no way to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) * detect it. So we'll initialize the driver, but the first
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) * attach will fail.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) * Being discussed with pHyp to do better (likely new property)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) if (afu->max_procs_virtualised == 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) afu->modes_supported = CXL_MODE_DEDICATED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) afu->modes_supported = CXL_MODE_DIRECTED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) if ((rc = cxl_afu_select_best_mode(afu)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) goto err_put2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) adapter->afu[afu->slice] = afu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) afu->enabled = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) * wake up the cpu periodically to check the state
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) * of the AFU using "afu" stored in the guest structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) afu->guest->parent = afu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) afu->guest->handle_err = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) INIT_DELAYED_WORK(&afu->guest->work_err, afu_handle_errstate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) schedule_delayed_work(&afu->guest->work_err, msecs_to_jiffies(1000));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) if ((rc = cxl_pci_vphb_add(afu)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) dev_info(&afu->dev, "Can't register vPHB\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) err_put2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) cxl_sysfs_afu_remove(afu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) err_put1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) device_unregister(&afu->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) free = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) guest_release_serr_irq(afu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) err2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) guest_unmap_slice_regs(afu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) err1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) if (free) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) kfree(afu->guest);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) kfree(afu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) void cxl_guest_remove_afu(struct cxl_afu *afu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) if (!afu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) /* flush and stop pending job */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) afu->guest->handle_err = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) flush_delayed_work(&afu->guest->work_err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) cxl_pci_vphb_remove(afu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) cxl_sysfs_afu_remove(afu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) spin_lock(&afu->adapter->afu_list_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) afu->adapter->afu[afu->slice] = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) spin_unlock(&afu->adapter->afu_list_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) cxl_context_detach_all(afu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) cxl_ops->afu_deactivate_mode(afu, afu->current_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) guest_release_serr_irq(afu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) guest_unmap_slice_regs(afu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) device_unregister(&afu->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) static void free_adapter(struct cxl *adapter)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) struct irq_avail *cur;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) if (adapter->guest) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) if (adapter->guest->irq_avail) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) for (i = 0; i < adapter->guest->irq_nranges; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) cur = &adapter->guest->irq_avail[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) kfree(cur->bitmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) kfree(adapter->guest->irq_avail);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) kfree(adapter->guest->status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) kfree(adapter->guest);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) cxl_remove_adapter_nr(adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) kfree(adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) static int properties_look_ok(struct cxl *adapter)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) /* The absence of this property means that the operational
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) * status is unknown or okay
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) if (strlen(adapter->guest->status) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) strcmp(adapter->guest->status, "okay")) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) pr_err("ABORTING:Bad operational status of the device\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) ssize_t cxl_guest_read_adapter_vpd(struct cxl *adapter, void *buf, size_t len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) return guest_collect_vpd(adapter, NULL, buf, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) void cxl_guest_remove_adapter(struct cxl *adapter)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) pr_devel("in %s\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) cxl_sysfs_adapter_remove(adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) cxl_guest_remove_chardev(adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) device_unregister(&adapter->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) static void release_adapter(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) free_adapter(to_cxl_adapter(dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) struct cxl *cxl_guest_init_adapter(struct device_node *np, struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) struct cxl *adapter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) bool free = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) if (!(adapter = cxl_alloc_adapter()))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) return ERR_PTR(-ENOMEM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) if (!(adapter->guest = kzalloc(sizeof(struct cxl_guest), GFP_KERNEL))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) free_adapter(adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) return ERR_PTR(-ENOMEM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) adapter->slices = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) adapter->guest->pdev = pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) adapter->dev.parent = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) adapter->dev.release = release_adapter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) dev_set_drvdata(&pdev->dev, adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) * Hypervisor controls PSL timebase initialization (p1 register).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) * On FW840, PSL is initialized.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) adapter->psl_timebase_synced = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) if ((rc = cxl_of_read_adapter_handle(adapter, np)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) goto err1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) if ((rc = cxl_of_read_adapter_properties(adapter, np)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) goto err1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) if ((rc = properties_look_ok(adapter)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) goto err1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) if ((rc = cxl_guest_add_chardev(adapter)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) goto err1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) * After we call this function we must not free the adapter directly,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) * even if it returns an error!
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) if ((rc = cxl_register_adapter(adapter)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) goto err_put1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) if ((rc = cxl_sysfs_adapter_add(adapter)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) goto err_put1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) /* release the context lock as the adapter is configured */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) cxl_adapter_context_unlock(adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) return adapter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) err_put1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) device_unregister(&adapter->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) free = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) cxl_guest_remove_chardev(adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) err1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) if (free)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) free_adapter(adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) return ERR_PTR(rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) void cxl_guest_reload_module(struct cxl *adapter)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) struct platform_device *pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) pdev = adapter->guest->pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) cxl_guest_remove_adapter(adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) cxl_of_probe(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) const struct cxl_backend_ops cxl_guest_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) .module = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) .adapter_reset = guest_reset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) .alloc_one_irq = guest_alloc_one_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) .release_one_irq = guest_release_one_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) .alloc_irq_ranges = guest_alloc_irq_ranges,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) .release_irq_ranges = guest_release_irq_ranges,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) .setup_irq = NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) .handle_psl_slice_error = guest_handle_psl_slice_error,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) .psl_interrupt = guest_psl_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) .ack_irq = guest_ack_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) .attach_process = guest_attach_process,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) .detach_process = guest_detach_process,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) .update_ivtes = NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) .support_attributes = guest_support_attributes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) .link_ok = guest_link_ok,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) .release_afu = guest_release_afu,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) .afu_read_err_buffer = guest_afu_read_err_buffer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) .afu_check_and_enable = guest_afu_check_and_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) .afu_activate_mode = guest_afu_activate_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) .afu_deactivate_mode = guest_afu_deactivate_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) .afu_reset = guest_afu_reset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) .afu_cr_read8 = guest_afu_cr_read8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) .afu_cr_read16 = guest_afu_cr_read16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) .afu_cr_read32 = guest_afu_cr_read32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) .afu_cr_read64 = guest_afu_cr_read64,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) .afu_cr_write8 = guest_afu_cr_write8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) .afu_cr_write16 = guest_afu_cr_write16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) .afu_cr_write32 = guest_afu_cr_write32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) .read_adapter_vpd = cxl_guest_read_adapter_vpd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) };
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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