Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Copyright 2017 IBM Corp.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) #include <linux/hugetlb.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) #include <linux/sched/mm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #include <asm/pnv-pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <misc/cxllib.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include "cxl.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #define CXL_INVALID_DRA                 ~0ull
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #define CXL_DUMMY_READ_SIZE             128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #define CXL_DUMMY_READ_ALIGN            8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #define CXL_CAPI_WINDOW_START           0x2000000000000ull
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #define CXL_CAPI_WINDOW_LOG_SIZE        48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #define CXL_XSL_CONFIG_CURRENT_VERSION  CXL_XSL_CONFIG_VERSION1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) bool cxllib_slot_is_supported(struct pci_dev *dev, unsigned long flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) 	int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) 	u32 phb_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 	u64 chip_id, capp_unit_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 	/* No flags currently supported */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 	if (flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 		return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 	if (!cpu_has_feature(CPU_FTR_HVMODE))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 		return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 	if (!cxl_is_power9())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 		return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 	if (cxl_slot_is_switched(dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 		return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 	/* on p9, some pci slots are not connected to a CAPP unit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 	rc = cxl_calc_capp_routing(dev, &chip_id, &phb_index, &capp_unit_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 	if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 		return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 	return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) EXPORT_SYMBOL_GPL(cxllib_slot_is_supported);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) static DEFINE_MUTEX(dra_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) static u64 dummy_read_addr = CXL_INVALID_DRA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) static int allocate_dummy_read_buf(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 	u64 buf, vaddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 	size_t buf_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 	 * Dummy read buffer is 128-byte long, aligned on a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	 * 256-byte boundary and we need the physical address.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 	buf_size = CXL_DUMMY_READ_SIZE + (1ull << CXL_DUMMY_READ_ALIGN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	buf = (u64) kzalloc(buf_size, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 	if (!buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 	vaddr = (buf + (1ull << CXL_DUMMY_READ_ALIGN) - 1) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 					(~0ull << CXL_DUMMY_READ_ALIGN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	WARN((vaddr + CXL_DUMMY_READ_SIZE) > (buf + buf_size),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 		"Dummy read buffer alignment issue");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	dummy_read_addr = virt_to_phys((void *) vaddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) int cxllib_get_xsl_config(struct pci_dev *dev, struct cxllib_xsl_config *cfg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	u32 phb_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	u64 chip_id, capp_unit_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	if (!cpu_has_feature(CPU_FTR_HVMODE))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	mutex_lock(&dra_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	if (dummy_read_addr == CXL_INVALID_DRA) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 		rc = allocate_dummy_read_buf();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 		if (rc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 			mutex_unlock(&dra_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 			return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	mutex_unlock(&dra_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	rc = cxl_calc_capp_routing(dev, &chip_id, &phb_index, &capp_unit_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 		return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	rc = cxl_get_xsl9_dsnctl(dev, capp_unit_id, &cfg->dsnctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 		return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	cfg->version  = CXL_XSL_CONFIG_CURRENT_VERSION;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	cfg->log_bar_size = CXL_CAPI_WINDOW_LOG_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	cfg->bar_addr = CXL_CAPI_WINDOW_START;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	cfg->dra = dummy_read_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) EXPORT_SYMBOL_GPL(cxllib_get_xsl_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) int cxllib_switch_phb_mode(struct pci_dev *dev, enum cxllib_mode mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 			unsigned long flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	int rc = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	if (!cpu_has_feature(CPU_FTR_HVMODE))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	switch (mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	case CXL_MODE_PCI:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 		/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 		 * We currently don't support going back to PCI mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 		 * However, we'll turn the invalidations off, so that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 		 * the firmware doesn't have to ack them and can do
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 		 * things like reset, etc.. with no worries.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 		 * So always return EPERM (can't go back to PCI) or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 		 * EBUSY if we couldn't even turn off snooping
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 		 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 		rc = pnv_phb_to_cxl_mode(dev, OPAL_PHB_CAPI_MODE_SNOOP_OFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 		if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 			rc = -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 		else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 			rc = -EPERM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	case CXL_MODE_CXL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 		/* DMA only supported on TVT1 for the time being */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 		if (flags != CXL_MODE_DMA_TVT1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 			return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 		rc = pnv_phb_to_cxl_mode(dev, OPAL_PHB_CAPI_MODE_DMA_TVT1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 		if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 			return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 		rc = pnv_phb_to_cxl_mode(dev, OPAL_PHB_CAPI_MODE_SNOOP_ON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 		rc = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) EXPORT_SYMBOL_GPL(cxllib_switch_phb_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)  * When switching the PHB to capi mode, the TVT#1 entry for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)  * the Partitionable Endpoint is set in bypass mode, like
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)  * in PCI mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)  * Configure the device dma to use TVT#1, which is done
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)  * by calling dma_set_mask() with a mask large enough.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) int cxllib_set_device_dma(struct pci_dev *dev, unsigned long flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	if (flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	rc = dma_set_mask(&dev->dev, DMA_BIT_MASK(64));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) EXPORT_SYMBOL_GPL(cxllib_set_device_dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) int cxllib_get_PE_attributes(struct task_struct *task,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 			     unsigned long translation_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 			     struct cxllib_pe_attributes *attr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	struct mm_struct *mm = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	if (translation_mode != CXL_TRANSLATED_MODE &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 		translation_mode != CXL_REAL_MODE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	attr->sr = cxl_calculate_sr(false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 				task == NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 				translation_mode == CXL_REAL_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 				true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	attr->lpid = mfspr(SPRN_LPID);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	if (task) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 		mm = get_task_mm(task);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 		if (mm == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 			return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 		/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 		 * Caller is keeping a reference on mm_users for as long
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 		 * as XSL uses the memory context
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 		 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 		attr->pid = mm->context.id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 		mmput(mm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 		attr->tid = task->thread.tidr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 		attr->pid = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 		attr->tid = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) EXPORT_SYMBOL_GPL(cxllib_get_PE_attributes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) static int get_vma_info(struct mm_struct *mm, u64 addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 			u64 *vma_start, u64 *vma_end,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 			unsigned long *page_size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	struct vm_area_struct *vma = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 	int rc = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	mmap_read_lock(mm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	vma = find_vma(mm, addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	if (!vma) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 		rc = -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 		goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 	*page_size = vma_kernel_pagesize(vma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 	*vma_start = vma->vm_start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	*vma_end = vma->vm_end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	mmap_read_unlock(mm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 	return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) int cxllib_handle_fault(struct mm_struct *mm, u64 addr, u64 size, u64 flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 	int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 	u64 dar, vma_start, vma_end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	unsigned long page_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 	if (mm == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 		return -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 	 * The buffer we have to process can extend over several pages
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 	 * and may also cover several VMAs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 	 * We iterate over all the pages. The page size could vary
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 	 * between VMAs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 	rc = get_vma_info(mm, addr, &vma_start, &vma_end, &page_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 	if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 		return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 	for (dar = (addr & ~(page_size - 1)); dar < (addr + size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 	     dar += page_size) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 		if (dar < vma_start || dar >= vma_end) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 			/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 			 * We don't hold mm->mmap_lock while iterating, since
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 			 * the lock is required by one of the lower-level page
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 			 * fault processing functions and it could
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 			 * create a deadlock.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 			 *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 			 * It means the VMAs can be altered between 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 			 * loop iterations and we could theoretically
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 			 * miss a page (however unlikely). But that's
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 			 * not really a problem, as the driver will
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 			 * retry access, get another page fault on the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 			 * missing page and call us again.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 			 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 			rc = get_vma_info(mm, dar, &vma_start, &vma_end,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 					&page_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 			if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 				return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 		rc = cxl_handle_mm_fault(mm, flags, dar);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 		if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 			return -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) EXPORT_SYMBOL_GPL(cxllib_handle_fault);