^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-or-later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright 2014 IBM Corp.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #ifndef _CXL_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #define _CXL_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/semaphore.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/cdev.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/pid.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/fs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <asm/cputable.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <asm/mmu.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <asm/reg.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <misc/cxl-base.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <misc/cxl.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <uapi/misc/cxl.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) extern uint cxl_verbose;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define CXL_TIMEOUT 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) * Bump version each time a user API change is made, whether it is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) * backwards compatible ot not.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define CXL_API_VERSION 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define CXL_API_VERSION_COMPATIBLE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) * Opaque types to avoid accidentally passing registers for the wrong MMIO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) * At the end of the day, I'm not married to using typedef here, but it might
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) * (and has!) help avoid bugs like mixing up CXL_PSL_CtxTime and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) * CXL_PSL_CtxTime_An, or calling cxl_p1n_write instead of cxl_p1_write.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) * I'm quite happy if these are changed back to #defines before upstreaming, it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) * should be little more than a regexp search+replace operation in this file.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) typedef struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) const int x;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) } cxl_p1_reg_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) typedef struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) const int x;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) } cxl_p1n_reg_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) typedef struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) const int x;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) } cxl_p2n_reg_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define cxl_reg_off(reg) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) (reg.x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) /* Memory maps. Ref CXL Appendix A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) /* PSL Privilege 1 Memory Map */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) /* Configuration and Control area - CAIA 1&2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) static const cxl_p1_reg_t CXL_PSL_CtxTime = {0x0000};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) static const cxl_p1_reg_t CXL_PSL_ErrIVTE = {0x0008};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) static const cxl_p1_reg_t CXL_PSL_KEY1 = {0x0010};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) static const cxl_p1_reg_t CXL_PSL_KEY2 = {0x0018};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) static const cxl_p1_reg_t CXL_PSL_Control = {0x0020};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) /* Downloading */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) static const cxl_p1_reg_t CXL_PSL_DLCNTL = {0x0060};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) static const cxl_p1_reg_t CXL_PSL_DLADDR = {0x0068};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) /* PSL Lookaside Buffer Management Area - CAIA 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) static const cxl_p1_reg_t CXL_PSL_LBISEL = {0x0080};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) static const cxl_p1_reg_t CXL_PSL_SLBIE = {0x0088};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) static const cxl_p1_reg_t CXL_PSL_SLBIA = {0x0090};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) static const cxl_p1_reg_t CXL_PSL_TLBIE = {0x00A0};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) static const cxl_p1_reg_t CXL_PSL_TLBIA = {0x00A8};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) static const cxl_p1_reg_t CXL_PSL_AFUSEL = {0x00B0};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) /* 0x00C0:7EFF Implementation dependent area */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) /* PSL registers - CAIA 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) static const cxl_p1_reg_t CXL_PSL_FIR1 = {0x0100};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) static const cxl_p1_reg_t CXL_PSL_FIR2 = {0x0108};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) static const cxl_p1_reg_t CXL_PSL_Timebase = {0x0110};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) static const cxl_p1_reg_t CXL_PSL_VERSION = {0x0118};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) static const cxl_p1_reg_t CXL_PSL_RESLCKTO = {0x0128};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) static const cxl_p1_reg_t CXL_PSL_TB_CTLSTAT = {0x0140};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) static const cxl_p1_reg_t CXL_PSL_FIR_CNTL = {0x0148};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) static const cxl_p1_reg_t CXL_PSL_DSNDCTL = {0x0150};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) static const cxl_p1_reg_t CXL_PSL_SNWRALLOC = {0x0158};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) static const cxl_p1_reg_t CXL_PSL_TRACE = {0x0170};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) /* PSL registers - CAIA 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) static const cxl_p1_reg_t CXL_PSL9_CONTROL = {0x0020};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) static const cxl_p1_reg_t CXL_XSL9_INV = {0x0110};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) static const cxl_p1_reg_t CXL_XSL9_DBG = {0x0130};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) static const cxl_p1_reg_t CXL_XSL9_DEF = {0x0140};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) static const cxl_p1_reg_t CXL_XSL9_DSNCTL = {0x0168};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) static const cxl_p1_reg_t CXL_PSL9_FIR1 = {0x0300};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) static const cxl_p1_reg_t CXL_PSL9_FIR_MASK = {0x0308};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) static const cxl_p1_reg_t CXL_PSL9_Timebase = {0x0310};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) static const cxl_p1_reg_t CXL_PSL9_DEBUG = {0x0320};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) static const cxl_p1_reg_t CXL_PSL9_FIR_CNTL = {0x0348};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) static const cxl_p1_reg_t CXL_PSL9_DSNDCTL = {0x0350};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) static const cxl_p1_reg_t CXL_PSL9_TB_CTLSTAT = {0x0340};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) static const cxl_p1_reg_t CXL_PSL9_TRACECFG = {0x0368};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) static const cxl_p1_reg_t CXL_PSL9_APCDEDALLOC = {0x0378};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) static const cxl_p1_reg_t CXL_PSL9_APCDEDTYPE = {0x0380};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) static const cxl_p1_reg_t CXL_PSL9_TNR_ADDR = {0x0388};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) static const cxl_p1_reg_t CXL_PSL9_CTCCFG = {0x0390};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) static const cxl_p1_reg_t CXL_PSL9_GP_CT = {0x0398};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) static const cxl_p1_reg_t CXL_XSL9_IERAT = {0x0588};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) static const cxl_p1_reg_t CXL_XSL9_ILPP = {0x0590};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) /* 0x7F00:7FFF Reserved PCIe MSI-X Pending Bit Array area */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) /* 0x8000:FFFF Reserved PCIe MSI-X Table Area */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) /* PSL Slice Privilege 1 Memory Map */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) /* Configuration Area - CAIA 1&2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) static const cxl_p1n_reg_t CXL_PSL_SR_An = {0x00};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) static const cxl_p1n_reg_t CXL_PSL_LPID_An = {0x08};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) static const cxl_p1n_reg_t CXL_PSL_AMBAR_An = {0x10};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) static const cxl_p1n_reg_t CXL_PSL_SPOffset_An = {0x18};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) static const cxl_p1n_reg_t CXL_PSL_ID_An = {0x20};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) static const cxl_p1n_reg_t CXL_PSL_SERR_An = {0x28};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) /* Memory Management and Lookaside Buffer Management - CAIA 1*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) static const cxl_p1n_reg_t CXL_PSL_SDR_An = {0x30};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) /* Memory Management and Lookaside Buffer Management - CAIA 1&2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) static const cxl_p1n_reg_t CXL_PSL_AMOR_An = {0x38};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) /* Pointer Area - CAIA 1&2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) static const cxl_p1n_reg_t CXL_HAURP_An = {0x80};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) static const cxl_p1n_reg_t CXL_PSL_SPAP_An = {0x88};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) static const cxl_p1n_reg_t CXL_PSL_LLCMD_An = {0x90};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) /* Control Area - CAIA 1&2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) static const cxl_p1n_reg_t CXL_PSL_SCNTL_An = {0xA0};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) static const cxl_p1n_reg_t CXL_PSL_CtxTime_An = {0xA8};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) static const cxl_p1n_reg_t CXL_PSL_IVTE_Offset_An = {0xB0};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) static const cxl_p1n_reg_t CXL_PSL_IVTE_Limit_An = {0xB8};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) /* 0xC0:FF Implementation Dependent Area - CAIA 1&2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) static const cxl_p1n_reg_t CXL_PSL_FIR_SLICE_An = {0xC0};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) static const cxl_p1n_reg_t CXL_AFU_DEBUG_An = {0xC8};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) /* 0xC0:FF Implementation Dependent Area - CAIA 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) static const cxl_p1n_reg_t CXL_PSL_APCALLOC_A = {0xD0};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) static const cxl_p1n_reg_t CXL_PSL_COALLOC_A = {0xD8};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) static const cxl_p1n_reg_t CXL_PSL_RXCTL_A = {0xE0};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) static const cxl_p1n_reg_t CXL_PSL_SLICE_TRACE = {0xE8};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) /* PSL Slice Privilege 2 Memory Map */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) /* Configuration and Control Area - CAIA 1&2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) static const cxl_p2n_reg_t CXL_PSL_PID_TID_An = {0x000};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) static const cxl_p2n_reg_t CXL_CSRP_An = {0x008};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) /* Configuration and Control Area - CAIA 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) static const cxl_p2n_reg_t CXL_AURP0_An = {0x010};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) static const cxl_p2n_reg_t CXL_AURP1_An = {0x018};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) static const cxl_p2n_reg_t CXL_SSTP0_An = {0x020};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) static const cxl_p2n_reg_t CXL_SSTP1_An = {0x028};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) /* Configuration and Control Area - CAIA 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) static const cxl_p2n_reg_t CXL_PSL_AMR_An = {0x030};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) /* Segment Lookaside Buffer Management - CAIA 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) static const cxl_p2n_reg_t CXL_SLBIE_An = {0x040};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) static const cxl_p2n_reg_t CXL_SLBIA_An = {0x048};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) static const cxl_p2n_reg_t CXL_SLBI_Select_An = {0x050};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) /* Interrupt Registers - CAIA 1&2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) static const cxl_p2n_reg_t CXL_PSL_DSISR_An = {0x060};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) static const cxl_p2n_reg_t CXL_PSL_DAR_An = {0x068};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) static const cxl_p2n_reg_t CXL_PSL_DSR_An = {0x070};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) static const cxl_p2n_reg_t CXL_PSL_TFC_An = {0x078};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) static const cxl_p2n_reg_t CXL_PSL_PEHandle_An = {0x080};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) static const cxl_p2n_reg_t CXL_PSL_ErrStat_An = {0x088};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) /* AFU Registers - CAIA 1&2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) static const cxl_p2n_reg_t CXL_AFU_Cntl_An = {0x090};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) static const cxl_p2n_reg_t CXL_AFU_ERR_An = {0x098};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) /* Work Element Descriptor - CAIA 1&2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) static const cxl_p2n_reg_t CXL_PSL_WED_An = {0x0A0};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) /* 0x0C0:FFF Implementation Dependent Area */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define CXL_PSL_SPAP_Addr 0x0ffffffffffff000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define CXL_PSL_SPAP_Size 0x0000000000000ff0ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define CXL_PSL_SPAP_Size_Shift 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define CXL_PSL_SPAP_V 0x0000000000000001ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) /****** CXL_PSL_Control ****************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define CXL_PSL_Control_tb (0x1ull << (63-63))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define CXL_PSL_Control_Fr (0x1ull << (63-31))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define CXL_PSL_Control_Fs_MASK (0x3ull << (63-29))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define CXL_PSL_Control_Fs_Complete (0x3ull << (63-29))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) /****** CXL_PSL_DLCNTL *****************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define CXL_PSL_DLCNTL_D (0x1ull << (63-28))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define CXL_PSL_DLCNTL_C (0x1ull << (63-29))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define CXL_PSL_DLCNTL_E (0x1ull << (63-30))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define CXL_PSL_DLCNTL_S (0x1ull << (63-31))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define CXL_PSL_DLCNTL_CE (CXL_PSL_DLCNTL_C | CXL_PSL_DLCNTL_E)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define CXL_PSL_DLCNTL_DCES (CXL_PSL_DLCNTL_D | CXL_PSL_DLCNTL_CE | CXL_PSL_DLCNTL_S)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) /****** CXL_PSL_SR_An ******************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define CXL_PSL_SR_An_SF MSR_SF /* 64bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define CXL_PSL_SR_An_TA (1ull << (63-1)) /* Tags active, GA1: 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define CXL_PSL_SR_An_HV MSR_HV /* Hypervisor, GA1: 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define CXL_PSL_SR_An_XLAT_hpt (0ull << (63-6))/* Hashed page table (HPT) mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define CXL_PSL_SR_An_XLAT_roh (2ull << (63-6))/* Radix on HPT mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define CXL_PSL_SR_An_XLAT_ror (3ull << (63-6))/* Radix on Radix mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define CXL_PSL_SR_An_BOT (1ull << (63-10)) /* Use the in-memory segment table */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define CXL_PSL_SR_An_PR MSR_PR /* Problem state, GA1: 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define CXL_PSL_SR_An_ISL (1ull << (63-53)) /* Ignore Segment Large Page */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define CXL_PSL_SR_An_TC (1ull << (63-54)) /* Page Table secondary hash */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define CXL_PSL_SR_An_US (1ull << (63-56)) /* User state, GA1: X */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #define CXL_PSL_SR_An_SC (1ull << (63-58)) /* Segment Table secondary hash */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define CXL_PSL_SR_An_R MSR_DR /* Relocate, GA1: 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define CXL_PSL_SR_An_MP (1ull << (63-62)) /* Master Process */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define CXL_PSL_SR_An_LE (1ull << (63-63)) /* Little Endian */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) /****** CXL_PSL_ID_An ****************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #define CXL_PSL_ID_An_F (1ull << (63-31))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #define CXL_PSL_ID_An_L (1ull << (63-30))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) /****** CXL_PSL_SERR_An ****************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #define CXL_PSL_SERR_An_afuto (1ull << (63-0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) #define CXL_PSL_SERR_An_afudis (1ull << (63-1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #define CXL_PSL_SERR_An_afuov (1ull << (63-2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define CXL_PSL_SERR_An_badsrc (1ull << (63-3))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #define CXL_PSL_SERR_An_badctx (1ull << (63-4))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define CXL_PSL_SERR_An_llcmdis (1ull << (63-5))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) #define CXL_PSL_SERR_An_llcmdto (1ull << (63-6))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #define CXL_PSL_SERR_An_afupar (1ull << (63-7))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #define CXL_PSL_SERR_An_afudup (1ull << (63-8))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #define CXL_PSL_SERR_An_IRQS ( \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) CXL_PSL_SERR_An_afuto | CXL_PSL_SERR_An_afudis | CXL_PSL_SERR_An_afuov | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) CXL_PSL_SERR_An_badsrc | CXL_PSL_SERR_An_badctx | CXL_PSL_SERR_An_llcmdis | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) CXL_PSL_SERR_An_llcmdto | CXL_PSL_SERR_An_afupar | CXL_PSL_SERR_An_afudup)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) #define CXL_PSL_SERR_An_afuto_mask (1ull << (63-32))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) #define CXL_PSL_SERR_An_afudis_mask (1ull << (63-33))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) #define CXL_PSL_SERR_An_afuov_mask (1ull << (63-34))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) #define CXL_PSL_SERR_An_badsrc_mask (1ull << (63-35))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) #define CXL_PSL_SERR_An_badctx_mask (1ull << (63-36))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) #define CXL_PSL_SERR_An_llcmdis_mask (1ull << (63-37))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) #define CXL_PSL_SERR_An_llcmdto_mask (1ull << (63-38))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) #define CXL_PSL_SERR_An_afupar_mask (1ull << (63-39))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) #define CXL_PSL_SERR_An_afudup_mask (1ull << (63-40))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) #define CXL_PSL_SERR_An_IRQ_MASKS ( \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) CXL_PSL_SERR_An_afuto_mask | CXL_PSL_SERR_An_afudis_mask | CXL_PSL_SERR_An_afuov_mask | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) CXL_PSL_SERR_An_badsrc_mask | CXL_PSL_SERR_An_badctx_mask | CXL_PSL_SERR_An_llcmdis_mask | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) CXL_PSL_SERR_An_llcmdto_mask | CXL_PSL_SERR_An_afupar_mask | CXL_PSL_SERR_An_afudup_mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) #define CXL_PSL_SERR_An_AE (1ull << (63-30))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) /****** CXL_PSL_SCNTL_An ****************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) #define CXL_PSL_SCNTL_An_CR (0x1ull << (63-15))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) /* Programming Modes: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) #define CXL_PSL_SCNTL_An_PM_MASK (0xffffull << (63-31))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) #define CXL_PSL_SCNTL_An_PM_Shared (0x0000ull << (63-31))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) #define CXL_PSL_SCNTL_An_PM_OS (0x0001ull << (63-31))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) #define CXL_PSL_SCNTL_An_PM_Process (0x0002ull << (63-31))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) #define CXL_PSL_SCNTL_An_PM_AFU (0x0004ull << (63-31))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) #define CXL_PSL_SCNTL_An_PM_AFU_PBT (0x0104ull << (63-31))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) /* Purge Status (ro) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) #define CXL_PSL_SCNTL_An_Ps_MASK (0x3ull << (63-39))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) #define CXL_PSL_SCNTL_An_Ps_Pending (0x1ull << (63-39))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) #define CXL_PSL_SCNTL_An_Ps_Complete (0x3ull << (63-39))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) /* Purge */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) #define CXL_PSL_SCNTL_An_Pc (0x1ull << (63-48))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) /* Suspend Status (ro) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) #define CXL_PSL_SCNTL_An_Ss_MASK (0x3ull << (63-55))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) #define CXL_PSL_SCNTL_An_Ss_Pending (0x1ull << (63-55))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) #define CXL_PSL_SCNTL_An_Ss_Complete (0x3ull << (63-55))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) /* Suspend Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) #define CXL_PSL_SCNTL_An_Sc (0x1ull << (63-63))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) /* AFU Slice Enable Status (ro) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) #define CXL_AFU_Cntl_An_ES_MASK (0x7ull << (63-2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) #define CXL_AFU_Cntl_An_ES_Disabled (0x0ull << (63-2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) #define CXL_AFU_Cntl_An_ES_Enabled (0x4ull << (63-2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) /* AFU Slice Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) #define CXL_AFU_Cntl_An_E (0x1ull << (63-3))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) /* AFU Slice Reset status (ro) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) #define CXL_AFU_Cntl_An_RS_MASK (0x3ull << (63-5))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) #define CXL_AFU_Cntl_An_RS_Pending (0x1ull << (63-5))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) #define CXL_AFU_Cntl_An_RS_Complete (0x2ull << (63-5))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) /* AFU Slice Reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) #define CXL_AFU_Cntl_An_RA (0x1ull << (63-7))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) /****** CXL_SSTP0/1_An ******************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) /* These top bits are for the segment that CONTAINS the segment table */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) #define CXL_SSTP0_An_B_SHIFT SLB_VSID_SSIZE_SHIFT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) #define CXL_SSTP0_An_KS (1ull << (63-2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) #define CXL_SSTP0_An_KP (1ull << (63-3))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) #define CXL_SSTP0_An_N (1ull << (63-4))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) #define CXL_SSTP0_An_L (1ull << (63-5))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) #define CXL_SSTP0_An_C (1ull << (63-6))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) #define CXL_SSTP0_An_TA (1ull << (63-7))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) #define CXL_SSTP0_An_LP_SHIFT (63-9) /* 2 Bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) /* And finally, the virtual address & size of the segment table: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) #define CXL_SSTP0_An_SegTableSize_SHIFT (63-31) /* 12 Bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) #define CXL_SSTP0_An_SegTableSize_MASK \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) (((1ull << 12) - 1) << CXL_SSTP0_An_SegTableSize_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) #define CXL_SSTP0_An_STVA_U_MASK ((1ull << (63-49))-1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) #define CXL_SSTP1_An_STVA_L_MASK (~((1ull << (63-55))-1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) #define CXL_SSTP1_An_V (1ull << (63-63))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) /****** CXL_PSL_SLBIE_[An] - CAIA 1 **************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) /* write: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) #define CXL_SLBIE_C PPC_BIT(36) /* Class */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) #define CXL_SLBIE_SS PPC_BITMASK(37, 38) /* Segment Size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) #define CXL_SLBIE_SS_SHIFT PPC_BITLSHIFT(38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) #define CXL_SLBIE_TA PPC_BIT(38) /* Tags Active */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) /* read: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) #define CXL_SLBIE_MAX PPC_BITMASK(24, 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) #define CXL_SLBIE_PENDING PPC_BITMASK(56, 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) /****** Common to all CXL_TLBIA/SLBIA_[An] - CAIA 1 **********************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) #define CXL_TLB_SLB_P (1ull) /* Pending (read) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) /****** Common to all CXL_TLB/SLB_IA/IE_[An] registers - CAIA 1 **********************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) #define CXL_TLB_SLB_IQ_ALL (0ull) /* Inv qualifier */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) #define CXL_TLB_SLB_IQ_LPID (1ull) /* Inv qualifier */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) #define CXL_TLB_SLB_IQ_LPIDPID (3ull) /* Inv qualifier */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) /****** CXL_PSL_AFUSEL ******************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) #define CXL_PSL_AFUSEL_A (1ull << (63-55)) /* Adapter wide invalidates affect all AFUs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) /****** CXL_PSL_DSISR_An - CAIA 1 ****************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) #define CXL_PSL_DSISR_An_DS (1ull << (63-0)) /* Segment not found */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) #define CXL_PSL_DSISR_An_DM (1ull << (63-1)) /* PTE not found (See also: M) or protection fault */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) #define CXL_PSL_DSISR_An_ST (1ull << (63-2)) /* Segment Table PTE not found */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) #define CXL_PSL_DSISR_An_UR (1ull << (63-3)) /* AURP PTE not found */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) #define CXL_PSL_DSISR_TRANS (CXL_PSL_DSISR_An_DS | CXL_PSL_DSISR_An_DM | CXL_PSL_DSISR_An_ST | CXL_PSL_DSISR_An_UR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) #define CXL_PSL_DSISR_An_PE (1ull << (63-4)) /* PSL Error (implementation specific) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) #define CXL_PSL_DSISR_An_AE (1ull << (63-5)) /* AFU Error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) #define CXL_PSL_DSISR_An_OC (1ull << (63-6)) /* OS Context Warning */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) #define CXL_PSL_DSISR_PENDING (CXL_PSL_DSISR_TRANS | CXL_PSL_DSISR_An_PE | CXL_PSL_DSISR_An_AE | CXL_PSL_DSISR_An_OC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) /* NOTE: Bits 32:63 are undefined if DSISR[DS] = 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) #define CXL_PSL_DSISR_An_M DSISR_NOHPTE /* PTE not found */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) #define CXL_PSL_DSISR_An_P DSISR_PROTFAULT /* Storage protection violation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) #define CXL_PSL_DSISR_An_A (1ull << (63-37)) /* AFU lock access to write through or cache inhibited storage */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) #define CXL_PSL_DSISR_An_S DSISR_ISSTORE /* Access was afu_wr or afu_zero */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) #define CXL_PSL_DSISR_An_K DSISR_KEYFAULT /* Access not permitted by virtual page class key protection */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) /****** CXL_PSL_DSISR_An - CAIA 2 ****************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) #define CXL_PSL9_DSISR_An_TF (1ull << (63-3)) /* Translation fault */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) #define CXL_PSL9_DSISR_An_PE (1ull << (63-4)) /* PSL Error (implementation specific) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) #define CXL_PSL9_DSISR_An_AE (1ull << (63-5)) /* AFU Error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) #define CXL_PSL9_DSISR_An_OC (1ull << (63-6)) /* OS Context Warning */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) #define CXL_PSL9_DSISR_An_S (1ull << (63-38)) /* TF for a write operation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) #define CXL_PSL9_DSISR_PENDING (CXL_PSL9_DSISR_An_TF | CXL_PSL9_DSISR_An_PE | CXL_PSL9_DSISR_An_AE | CXL_PSL9_DSISR_An_OC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) * NOTE: Bits 56:63 (Checkout Response Status) are valid when DSISR_An[TF] = 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) * Status (0:7) Encoding
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) #define CXL_PSL9_DSISR_An_CO_MASK 0x00000000000000ffULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) #define CXL_PSL9_DSISR_An_SF 0x0000000000000080ULL /* Segment Fault 0b10000000 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) #define CXL_PSL9_DSISR_An_PF_SLR 0x0000000000000088ULL /* PTE not found (Single Level Radix) 0b10001000 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) #define CXL_PSL9_DSISR_An_PF_RGC 0x000000000000008CULL /* PTE not found (Radix Guest (child)) 0b10001100 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) #define CXL_PSL9_DSISR_An_PF_RGP 0x0000000000000090ULL /* PTE not found (Radix Guest (parent)) 0b10010000 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) #define CXL_PSL9_DSISR_An_PF_HRH 0x0000000000000094ULL /* PTE not found (HPT/Radix Host) 0b10010100 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) #define CXL_PSL9_DSISR_An_PF_STEG 0x000000000000009CULL /* PTE not found (STEG VA) 0b10011100 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) #define CXL_PSL9_DSISR_An_URTCH 0x00000000000000B4ULL /* Unsupported Radix Tree Configuration 0b10110100 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) /****** CXL_PSL_TFC_An ******************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) #define CXL_PSL_TFC_An_A (1ull << (63-28)) /* Acknowledge non-translation fault */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) #define CXL_PSL_TFC_An_C (1ull << (63-29)) /* Continue (abort transaction) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) #define CXL_PSL_TFC_An_AE (1ull << (63-30)) /* Restart PSL with address error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) #define CXL_PSL_TFC_An_R (1ull << (63-31)) /* Restart PSL transaction */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) /****** CXL_PSL_DEBUG *****************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) #define CXL_PSL_DEBUG_CDC (1ull << (63-27)) /* Coherent Data cache support */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) /****** CXL_XSL9_IERAT_ERAT - CAIA 2 **********************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) #define CXL_XSL9_IERAT_MLPID (1ull << (63-0)) /* Match LPID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) #define CXL_XSL9_IERAT_MPID (1ull << (63-1)) /* Match PID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) #define CXL_XSL9_IERAT_PRS (1ull << (63-4)) /* PRS bit for Radix invalidations */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) #define CXL_XSL9_IERAT_INVR (1ull << (63-3)) /* Invalidate Radix */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) #define CXL_XSL9_IERAT_IALL (1ull << (63-8)) /* Invalidate All */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) #define CXL_XSL9_IERAT_IINPROG (1ull << (63-63)) /* Invalidate in progress */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) /* cxl_process_element->software_status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) #define CXL_PE_SOFTWARE_STATE_V (1ul << (31 - 0)) /* Valid */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) #define CXL_PE_SOFTWARE_STATE_C (1ul << (31 - 29)) /* Complete */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) #define CXL_PE_SOFTWARE_STATE_S (1ul << (31 - 30)) /* Suspend */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) #define CXL_PE_SOFTWARE_STATE_T (1ul << (31 - 31)) /* Terminate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) /****** CXL_PSL_RXCTL_An (Implementation Specific) **************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) * Controls AFU Hang Pulse, which sets the timeout for the AFU to respond to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) * the PSL for any response (except MMIO). Timeouts will occur between 1x to 2x
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) * of the hang pulse frequency.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) #define CXL_PSL_RXCTL_AFUHP_4S 0x7000000000000000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) /* SPA->sw_command_status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) #define CXL_SPA_SW_CMD_MASK 0xffff000000000000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) #define CXL_SPA_SW_CMD_TERMINATE 0x0001000000000000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) #define CXL_SPA_SW_CMD_REMOVE 0x0002000000000000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) #define CXL_SPA_SW_CMD_SUSPEND 0x0003000000000000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) #define CXL_SPA_SW_CMD_RESUME 0x0004000000000000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) #define CXL_SPA_SW_CMD_ADD 0x0005000000000000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) #define CXL_SPA_SW_CMD_UPDATE 0x0006000000000000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) #define CXL_SPA_SW_STATE_MASK 0x0000ffff00000000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) #define CXL_SPA_SW_STATE_TERMINATED 0x0000000100000000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) #define CXL_SPA_SW_STATE_REMOVED 0x0000000200000000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) #define CXL_SPA_SW_STATE_SUSPENDED 0x0000000300000000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) #define CXL_SPA_SW_STATE_RESUMED 0x0000000400000000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) #define CXL_SPA_SW_STATE_ADDED 0x0000000500000000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) #define CXL_SPA_SW_STATE_UPDATED 0x0000000600000000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) #define CXL_SPA_SW_PSL_ID_MASK 0x00000000ffff0000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) #define CXL_SPA_SW_LINK_MASK 0x000000000000ffffULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) #define CXL_MAX_SLICES 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) #define MAX_AFU_MMIO_REGS 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) #define CXL_MODE_TIME_SLICED 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) #define CXL_SUPPORTED_MODES (CXL_MODE_DEDICATED | CXL_MODE_DIRECTED)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) #define CXL_DEV_MINORS 13 /* 1 control + 4 AFUs * 3 (dedicated/master/shared) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) #define CXL_CARD_MINOR(adapter) (adapter->adapter_num * CXL_DEV_MINORS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) #define CXL_DEVT_ADAPTER(dev) (MINOR(dev) / CXL_DEV_MINORS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) #define CXL_PSL9_TRACEID_MAX 0xAU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) #define CXL_PSL9_TRACESTATE_FIN 0x3U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) enum cxl_context_status {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) CLOSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) OPENED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) STARTED
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) enum prefault_modes {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) CXL_PREFAULT_NONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) CXL_PREFAULT_WED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) CXL_PREFAULT_ALL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) enum cxl_attrs {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) CXL_ADAPTER_ATTRS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) CXL_AFU_MASTER_ATTRS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) CXL_AFU_ATTRS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) struct cxl_sste {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) __be64 esid_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) __be64 vsid_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) #define to_cxl_adapter(d) container_of(d, struct cxl, dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) #define to_cxl_afu(d) container_of(d, struct cxl_afu, dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) struct cxl_afu_native {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) void __iomem *p1n_mmio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) void __iomem *afu_desc_mmio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) irq_hw_number_t psl_hwirq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) unsigned int psl_virq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) struct mutex spa_mutex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) * Only the first part of the SPA is used for the process element
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) * linked list. The only other part that software needs to worry about
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) * is sw_command_status, which we store a separate pointer to.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) * Everything else in the SPA is only used by hardware
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) struct cxl_process_element *spa;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) __be64 *sw_command_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) unsigned int spa_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) int spa_order;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) int spa_max_procs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) u64 pp_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) struct cxl_afu_guest {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) struct cxl_afu *parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) u64 handle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) phys_addr_t p2n_phys;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) u64 p2n_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) int max_ints;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) bool handle_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) struct delayed_work work_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) int previous_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) struct cxl_afu {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) struct cxl_afu_native *native;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) struct cxl_afu_guest *guest;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) irq_hw_number_t serr_hwirq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) unsigned int serr_virq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) char *psl_irq_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) char *err_irq_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) void __iomem *p2n_mmio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) phys_addr_t psn_phys;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) u64 pp_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) struct cxl *adapter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) struct device dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) struct cdev afu_cdev_s, afu_cdev_m, afu_cdev_d;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) struct device *chardev_s, *chardev_m, *chardev_d;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) struct idr contexts_idr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) struct dentry *debugfs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) struct mutex contexts_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) spinlock_t afu_cntl_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) /* -1: AFU deconfigured/locked, >= 0: number of readers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) atomic_t configured_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) /* AFU error buffer fields and bin attribute for sysfs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) u64 eb_len, eb_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) struct bin_attribute attr_eb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) /* pointer to the vphb */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) struct pci_controller *phb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) int pp_irqs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) int irqs_max;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) int num_procs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) int max_procs_virtualised;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) int slice;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) int modes_supported;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) int current_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) int crs_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) u64 crs_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) u64 crs_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) struct list_head crs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) enum prefault_modes prefault_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) bool psa;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) bool pp_psa;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) bool enabled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) struct cxl_irq_name {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) struct list_head list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) struct irq_avail {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) irq_hw_number_t offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) irq_hw_number_t range;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) unsigned long *bitmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) * This is a cxl context. If the PSL is in dedicated mode, there will be one
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) * of these per AFU. If in AFU directed there can be lots of these.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) struct cxl_context {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) struct cxl_afu *afu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) /* Problem state MMIO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) phys_addr_t psn_phys;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) u64 psn_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) /* Used to unmap any mmaps when force detaching */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) struct address_space *mapping;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) struct mutex mapping_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) struct page *ff_page;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) bool mmio_err_ff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) bool kernelapi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) spinlock_t sste_lock; /* Protects segment table entries */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) struct cxl_sste *sstp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) u64 sstp0, sstp1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) unsigned int sst_size, sst_lru;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) wait_queue_head_t wq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) /* use mm context associated with this pid for ds faults */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) struct pid *pid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) spinlock_t lock; /* Protects pending_irq_mask, pending_fault and fault_addr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) /* Only used in PR mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) u64 process_token;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) /* driver private data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) void *priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) unsigned long *irq_bitmap; /* Accessed from IRQ context */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) struct cxl_irq_ranges irqs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) struct list_head irq_names;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) u64 fault_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) u64 fault_dsisr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) u64 afu_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) * This status and it's lock pretects start and detach context
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) * from racing. It also prevents detach from racing with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) * itself
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) enum cxl_context_status status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) struct mutex status_mutex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) /* XXX: Is it possible to need multiple work items at once? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) struct work_struct fault_work;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) u64 dsisr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) u64 dar;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) struct cxl_process_element *elem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) * pe is the process element handle, assigned by this driver when the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) * context is initialized.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) * external_pe is the PE shown outside of cxl.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) * On bare-metal, pe=external_pe, because we decide what the handle is.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) * In a guest, we only find out about the pe used by pHyp when the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) * context is attached, and that's the value we want to report outside
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) * of cxl.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) int pe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) int external_pe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) u32 irq_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) bool pe_inserted;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) bool master;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) bool kernel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) bool pending_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) bool pending_fault;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) bool pending_afu_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) /* Used by AFU drivers for driver specific event delivery */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) struct cxl_afu_driver_ops *afu_driver_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) atomic_t afu_driver_events;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) struct rcu_head rcu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) struct mm_struct *mm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) u16 tidr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) bool assign_tidr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) struct cxl_irq_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) struct cxl_service_layer_ops {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) int (*adapter_regs_init)(struct cxl *adapter, struct pci_dev *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) int (*invalidate_all)(struct cxl *adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) int (*afu_regs_init)(struct cxl_afu *afu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) int (*sanitise_afu_regs)(struct cxl_afu *afu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) int (*register_serr_irq)(struct cxl_afu *afu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) void (*release_serr_irq)(struct cxl_afu *afu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) irqreturn_t (*handle_interrupt)(int irq, struct cxl_context *ctx, struct cxl_irq_info *irq_info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) irqreturn_t (*fail_irq)(struct cxl_afu *afu, struct cxl_irq_info *irq_info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) int (*activate_dedicated_process)(struct cxl_afu *afu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) int (*attach_afu_directed)(struct cxl_context *ctx, u64 wed, u64 amr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) int (*attach_dedicated_process)(struct cxl_context *ctx, u64 wed, u64 amr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) void (*update_dedicated_ivtes)(struct cxl_context *ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) void (*debugfs_add_adapter_regs)(struct cxl *adapter, struct dentry *dir);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) void (*debugfs_add_afu_regs)(struct cxl_afu *afu, struct dentry *dir);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) void (*psl_irq_dump_registers)(struct cxl_context *ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) void (*err_irq_dump_registers)(struct cxl *adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) void (*debugfs_stop_trace)(struct cxl *adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) void (*write_timebase_ctrl)(struct cxl *adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) u64 (*timebase_read)(struct cxl *adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) int capi_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) bool needs_reset_before_disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) struct cxl_native {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) u64 afu_desc_off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) u64 afu_desc_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) void __iomem *p1_mmio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) void __iomem *p2_mmio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) irq_hw_number_t err_hwirq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) unsigned int err_virq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) u64 ps_off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) bool no_data_cache; /* set if no data cache on the card */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) const struct cxl_service_layer_ops *sl_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) struct cxl_guest {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) struct platform_device *pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) int irq_nranges;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) struct cdev cdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) irq_hw_number_t irq_base_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) struct irq_avail *irq_avail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) spinlock_t irq_alloc_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) u64 handle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) char *status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) u16 vendor;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) u16 device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) u16 subsystem_vendor;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) u16 subsystem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) struct cxl {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) struct cxl_native *native;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) struct cxl_guest *guest;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) spinlock_t afu_list_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) struct cxl_afu *afu[CXL_MAX_SLICES];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) struct device dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) struct dentry *trace;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) struct dentry *psl_err_chk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) struct dentry *debugfs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) char *irq_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) struct bin_attribute cxl_attr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) int adapter_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) int user_irqs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) u64 ps_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) u16 psl_rev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) u16 base_image;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) u8 vsec_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) u8 caia_major;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) u8 caia_minor;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) u8 slices;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) bool user_image_loaded;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) bool perst_loads_image;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) bool perst_select_user;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) bool perst_same_image;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) bool psl_timebase_synced;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) bool tunneled_ops_supported;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) * number of contexts mapped on to this card. Possible values are:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) * >0: Number of contexts mapped and new one can be mapped.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) * 0: No active contexts and new ones can be mapped.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) * -1: No contexts mapped and new ones cannot be mapped.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) atomic_t contexts_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) int cxl_pci_alloc_one_irq(struct cxl *adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) void cxl_pci_release_one_irq(struct cxl *adapter, int hwirq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) int cxl_pci_alloc_irq_ranges(struct cxl_irq_ranges *irqs, struct cxl *adapter, unsigned int num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) void cxl_pci_release_irq_ranges(struct cxl_irq_ranges *irqs, struct cxl *adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) int cxl_pci_setup_irq(struct cxl *adapter, unsigned int hwirq, unsigned int virq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) int cxl_update_image_control(struct cxl *adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) int cxl_pci_reset(struct cxl *adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) void cxl_pci_release_afu(struct device *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) ssize_t cxl_pci_read_adapter_vpd(struct cxl *adapter, void *buf, size_t len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) /* common == phyp + powernv - CAIA 1&2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) struct cxl_process_element_common {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) __be32 tid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) __be32 pid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) __be64 csrp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) __be64 aurp0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) __be64 aurp1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) __be64 sstp0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) __be64 sstp1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) } psl8; /* CAIA 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) u8 reserved2[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) u8 reserved3[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) u8 reserved4[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) u8 reserved5[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) } psl9; /* CAIA 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) } u;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) __be64 amr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) u8 reserved6[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) __be64 wed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) /* just powernv - CAIA 1&2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) struct cxl_process_element {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) __be64 sr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) __be64 SPOffset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) __be64 sdr; /* CAIA 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) u8 reserved1[8]; /* CAIA 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) } u;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) __be64 haurp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) __be32 ctxtime;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) __be16 ivte_offsets[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) __be16 ivte_ranges[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) __be32 lpid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) struct cxl_process_element_common common;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) __be32 software_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) static inline bool cxl_adapter_link_ok(struct cxl *cxl, struct cxl_afu *afu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) struct pci_dev *pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) if (cpu_has_feature(CPU_FTR_HVMODE)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) pdev = to_pci_dev(cxl->dev.parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) return !pci_channel_offline(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) static inline void __iomem *_cxl_p1_addr(struct cxl *cxl, cxl_p1_reg_t reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) WARN_ON(!cpu_has_feature(CPU_FTR_HVMODE));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) return cxl->native->p1_mmio + cxl_reg_off(reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) static inline void cxl_p1_write(struct cxl *cxl, cxl_p1_reg_t reg, u64 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) if (likely(cxl_adapter_link_ok(cxl, NULL)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) out_be64(_cxl_p1_addr(cxl, reg), val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) static inline u64 cxl_p1_read(struct cxl *cxl, cxl_p1_reg_t reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) if (likely(cxl_adapter_link_ok(cxl, NULL)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) return in_be64(_cxl_p1_addr(cxl, reg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) return ~0ULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) static inline void __iomem *_cxl_p1n_addr(struct cxl_afu *afu, cxl_p1n_reg_t reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) WARN_ON(!cpu_has_feature(CPU_FTR_HVMODE));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) return afu->native->p1n_mmio + cxl_reg_off(reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) static inline void cxl_p1n_write(struct cxl_afu *afu, cxl_p1n_reg_t reg, u64 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) if (likely(cxl_adapter_link_ok(afu->adapter, afu)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) out_be64(_cxl_p1n_addr(afu, reg), val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) static inline u64 cxl_p1n_read(struct cxl_afu *afu, cxl_p1n_reg_t reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) if (likely(cxl_adapter_link_ok(afu->adapter, afu)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) return in_be64(_cxl_p1n_addr(afu, reg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) return ~0ULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) static inline void __iomem *_cxl_p2n_addr(struct cxl_afu *afu, cxl_p2n_reg_t reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) return afu->p2n_mmio + cxl_reg_off(reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) static inline void cxl_p2n_write(struct cxl_afu *afu, cxl_p2n_reg_t reg, u64 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) if (likely(cxl_adapter_link_ok(afu->adapter, afu)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) out_be64(_cxl_p2n_addr(afu, reg), val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) static inline u64 cxl_p2n_read(struct cxl_afu *afu, cxl_p2n_reg_t reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) if (likely(cxl_adapter_link_ok(afu->adapter, afu)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) return in_be64(_cxl_p2n_addr(afu, reg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) return ~0ULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) static inline bool cxl_is_power8(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) if ((pvr_version_is(PVR_POWER8E)) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) (pvr_version_is(PVR_POWER8NVL)) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) (pvr_version_is(PVR_POWER8)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) static inline bool cxl_is_power9(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) if (pvr_version_is(PVR_POWER9))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) ssize_t cxl_pci_afu_read_err_buffer(struct cxl_afu *afu, char *buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) loff_t off, size_t count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) struct cxl_calls {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) void (*cxl_slbia)(struct mm_struct *mm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) struct module *owner;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) int register_cxl_calls(struct cxl_calls *calls);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) void unregister_cxl_calls(struct cxl_calls *calls);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) int cxl_update_properties(struct device_node *dn, struct property *new_prop);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) void cxl_remove_adapter_nr(struct cxl *adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) void cxl_release_spa(struct cxl_afu *afu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) dev_t cxl_get_dev(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) int cxl_file_init(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) void cxl_file_exit(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) int cxl_register_adapter(struct cxl *adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) int cxl_register_afu(struct cxl_afu *afu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) int cxl_chardev_d_afu_add(struct cxl_afu *afu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) int cxl_chardev_m_afu_add(struct cxl_afu *afu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) int cxl_chardev_s_afu_add(struct cxl_afu *afu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) void cxl_chardev_afu_remove(struct cxl_afu *afu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) void cxl_context_detach_all(struct cxl_afu *afu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) void cxl_context_free(struct cxl_context *ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) void cxl_context_detach(struct cxl_context *ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) int cxl_sysfs_adapter_add(struct cxl *adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) void cxl_sysfs_adapter_remove(struct cxl *adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) int cxl_sysfs_afu_add(struct cxl_afu *afu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) void cxl_sysfs_afu_remove(struct cxl_afu *afu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) int cxl_sysfs_afu_m_add(struct cxl_afu *afu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) void cxl_sysfs_afu_m_remove(struct cxl_afu *afu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) struct cxl *cxl_alloc_adapter(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) struct cxl_afu *cxl_alloc_afu(struct cxl *adapter, int slice);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) int cxl_afu_select_best_mode(struct cxl_afu *afu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) int cxl_native_register_psl_irq(struct cxl_afu *afu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) void cxl_native_release_psl_irq(struct cxl_afu *afu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) int cxl_native_register_psl_err_irq(struct cxl *adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) void cxl_native_release_psl_err_irq(struct cxl *adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) int cxl_native_register_serr_irq(struct cxl_afu *afu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) void cxl_native_release_serr_irq(struct cxl_afu *afu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) int afu_register_irqs(struct cxl_context *ctx, u32 count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) void afu_release_irqs(struct cxl_context *ctx, void *cookie);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) void afu_irq_name_free(struct cxl_context *ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) int cxl_attach_afu_directed_psl9(struct cxl_context *ctx, u64 wed, u64 amr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) int cxl_attach_afu_directed_psl8(struct cxl_context *ctx, u64 wed, u64 amr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) int cxl_activate_dedicated_process_psl9(struct cxl_afu *afu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) int cxl_activate_dedicated_process_psl8(struct cxl_afu *afu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) int cxl_attach_dedicated_process_psl9(struct cxl_context *ctx, u64 wed, u64 amr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) int cxl_attach_dedicated_process_psl8(struct cxl_context *ctx, u64 wed, u64 amr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) void cxl_update_dedicated_ivtes_psl9(struct cxl_context *ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) void cxl_update_dedicated_ivtes_psl8(struct cxl_context *ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) #ifdef CONFIG_DEBUG_FS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) void cxl_debugfs_init(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) void cxl_debugfs_exit(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) void cxl_debugfs_adapter_add(struct cxl *adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) void cxl_debugfs_adapter_remove(struct cxl *adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) void cxl_debugfs_afu_add(struct cxl_afu *afu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) void cxl_debugfs_afu_remove(struct cxl_afu *afu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) void cxl_debugfs_add_adapter_regs_psl9(struct cxl *adapter, struct dentry *dir);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) void cxl_debugfs_add_adapter_regs_psl8(struct cxl *adapter, struct dentry *dir);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) void cxl_debugfs_add_afu_regs_psl9(struct cxl_afu *afu, struct dentry *dir);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) void cxl_debugfs_add_afu_regs_psl8(struct cxl_afu *afu, struct dentry *dir);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) #else /* CONFIG_DEBUG_FS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) static inline void __init cxl_debugfs_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) static inline void cxl_debugfs_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) static inline void cxl_debugfs_adapter_add(struct cxl *adapter)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) static inline void cxl_debugfs_adapter_remove(struct cxl *adapter)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) static inline void cxl_debugfs_afu_add(struct cxl_afu *afu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) static inline void cxl_debugfs_afu_remove(struct cxl_afu *afu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) static inline void cxl_debugfs_add_adapter_regs_psl9(struct cxl *adapter,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) struct dentry *dir)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) static inline void cxl_debugfs_add_adapter_regs_psl8(struct cxl *adapter,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) struct dentry *dir)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) static inline void cxl_debugfs_add_afu_regs_psl9(struct cxl_afu *afu, struct dentry *dir)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) static inline void cxl_debugfs_add_afu_regs_psl8(struct cxl_afu *afu, struct dentry *dir)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) #endif /* CONFIG_DEBUG_FS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) void cxl_handle_fault(struct work_struct *work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) void cxl_prefault(struct cxl_context *ctx, u64 wed);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) int cxl_handle_mm_fault(struct mm_struct *mm, u64 dsisr, u64 dar);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) struct cxl *get_cxl_adapter(int num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) int cxl_alloc_sst(struct cxl_context *ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) void cxl_dump_debug_buffer(void *addr, size_t size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) void init_cxl_native(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) struct cxl_context *cxl_context_alloc(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) int cxl_context_init(struct cxl_context *ctx, struct cxl_afu *afu, bool master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) void cxl_context_set_mapping(struct cxl_context *ctx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) struct address_space *mapping);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) void cxl_context_free(struct cxl_context *ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) int cxl_context_iomap(struct cxl_context *ctx, struct vm_area_struct *vma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) unsigned int cxl_map_irq(struct cxl *adapter, irq_hw_number_t hwirq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) irq_handler_t handler, void *cookie, const char *name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) void cxl_unmap_irq(unsigned int virq, void *cookie);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) int __detach_context(struct cxl_context *ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) * This must match the layout of the H_COLLECT_CA_INT_INFO retbuf defined
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) * in PAPR.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) * Field pid_tid is now 'reserved' because it's no more used on bare-metal.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) * On a guest environment, PSL_PID_An is located on the upper 32 bits and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) * PSL_TID_An register in the lower 32 bits.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) struct cxl_irq_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) u64 dsisr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) u64 dar;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) u64 dsr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) u64 reserved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) u64 afu_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) u64 errstat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) u64 proc_handle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) u64 padding[2]; /* to match the expected retbuf size for plpar_hcall9 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) void cxl_assign_psn_space(struct cxl_context *ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) int cxl_invalidate_all_psl9(struct cxl *adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) int cxl_invalidate_all_psl8(struct cxl *adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) irqreturn_t cxl_irq_psl9(int irq, struct cxl_context *ctx, struct cxl_irq_info *irq_info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) irqreturn_t cxl_irq_psl8(int irq, struct cxl_context *ctx, struct cxl_irq_info *irq_info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) irqreturn_t cxl_fail_irq_psl(struct cxl_afu *afu, struct cxl_irq_info *irq_info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) int cxl_register_one_irq(struct cxl *adapter, irq_handler_t handler,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) void *cookie, irq_hw_number_t *dest_hwirq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) unsigned int *dest_virq, const char *name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) int cxl_check_error(struct cxl_afu *afu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) int cxl_afu_slbia(struct cxl_afu *afu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) int cxl_data_cache_flush(struct cxl *adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) int cxl_afu_disable(struct cxl_afu *afu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) int cxl_psl_purge(struct cxl_afu *afu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) int cxl_calc_capp_routing(struct pci_dev *dev, u64 *chipid,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) u32 *phb_index, u64 *capp_unit_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) int cxl_slot_is_switched(struct pci_dev *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) int cxl_get_xsl9_dsnctl(struct pci_dev *dev, u64 capp_unit_id, u64 *reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) u64 cxl_calculate_sr(bool master, bool kernel, bool real_mode, bool p9);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) void cxl_native_irq_dump_regs_psl9(struct cxl_context *ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) void cxl_native_irq_dump_regs_psl8(struct cxl_context *ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) void cxl_native_err_irq_dump_regs_psl8(struct cxl *adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) void cxl_native_err_irq_dump_regs_psl9(struct cxl *adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) int cxl_pci_vphb_add(struct cxl_afu *afu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) void cxl_pci_vphb_remove(struct cxl_afu *afu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) void cxl_release_mapping(struct cxl_context *ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) extern struct pci_driver cxl_pci_driver;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) extern struct platform_driver cxl_of_driver;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) int afu_allocate_irqs(struct cxl_context *ctx, u32 count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) int afu_open(struct inode *inode, struct file *file);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) int afu_release(struct inode *inode, struct file *file);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) long afu_ioctl(struct file *file, unsigned int cmd, unsigned long arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) int afu_mmap(struct file *file, struct vm_area_struct *vm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) __poll_t afu_poll(struct file *file, struct poll_table_struct *poll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) ssize_t afu_read(struct file *file, char __user *buf, size_t count, loff_t *off);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) extern const struct file_operations afu_fops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) struct cxl *cxl_guest_init_adapter(struct device_node *np, struct platform_device *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) void cxl_guest_remove_adapter(struct cxl *adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) int cxl_of_read_adapter_handle(struct cxl *adapter, struct device_node *np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) int cxl_of_read_adapter_properties(struct cxl *adapter, struct device_node *np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) ssize_t cxl_guest_read_adapter_vpd(struct cxl *adapter, void *buf, size_t len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) ssize_t cxl_guest_read_afu_vpd(struct cxl_afu *afu, void *buf, size_t len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) int cxl_guest_init_afu(struct cxl *adapter, int slice, struct device_node *afu_np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) void cxl_guest_remove_afu(struct cxl_afu *afu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) int cxl_of_read_afu_handle(struct cxl_afu *afu, struct device_node *afu_np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) int cxl_of_read_afu_properties(struct cxl_afu *afu, struct device_node *afu_np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) int cxl_guest_add_chardev(struct cxl *adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) void cxl_guest_remove_chardev(struct cxl *adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) void cxl_guest_reload_module(struct cxl *adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) int cxl_of_probe(struct platform_device *pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) struct cxl_backend_ops {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) struct module *module;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) int (*adapter_reset)(struct cxl *adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) int (*alloc_one_irq)(struct cxl *adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) void (*release_one_irq)(struct cxl *adapter, int hwirq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) int (*alloc_irq_ranges)(struct cxl_irq_ranges *irqs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) struct cxl *adapter, unsigned int num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) void (*release_irq_ranges)(struct cxl_irq_ranges *irqs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) struct cxl *adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) int (*setup_irq)(struct cxl *adapter, unsigned int hwirq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) unsigned int virq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) irqreturn_t (*handle_psl_slice_error)(struct cxl_context *ctx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) u64 dsisr, u64 errstat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) irqreturn_t (*psl_interrupt)(int irq, void *data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) int (*ack_irq)(struct cxl_context *ctx, u64 tfc, u64 psl_reset_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) void (*irq_wait)(struct cxl_context *ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) int (*attach_process)(struct cxl_context *ctx, bool kernel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) u64 wed, u64 amr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) int (*detach_process)(struct cxl_context *ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) void (*update_ivtes)(struct cxl_context *ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) bool (*support_attributes)(const char *attr_name, enum cxl_attrs type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) bool (*link_ok)(struct cxl *cxl, struct cxl_afu *afu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) void (*release_afu)(struct device *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) ssize_t (*afu_read_err_buffer)(struct cxl_afu *afu, char *buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) loff_t off, size_t count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) int (*afu_check_and_enable)(struct cxl_afu *afu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) int (*afu_activate_mode)(struct cxl_afu *afu, int mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) int (*afu_deactivate_mode)(struct cxl_afu *afu, int mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) int (*afu_reset)(struct cxl_afu *afu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) int (*afu_cr_read8)(struct cxl_afu *afu, int cr_idx, u64 offset, u8 *val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) int (*afu_cr_read16)(struct cxl_afu *afu, int cr_idx, u64 offset, u16 *val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) int (*afu_cr_read32)(struct cxl_afu *afu, int cr_idx, u64 offset, u32 *val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) int (*afu_cr_read64)(struct cxl_afu *afu, int cr_idx, u64 offset, u64 *val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) int (*afu_cr_write8)(struct cxl_afu *afu, int cr_idx, u64 offset, u8 val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) int (*afu_cr_write16)(struct cxl_afu *afu, int cr_idx, u64 offset, u16 val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) int (*afu_cr_write32)(struct cxl_afu *afu, int cr_idx, u64 offset, u32 val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) ssize_t (*read_adapter_vpd)(struct cxl *adapter, void *buf, size_t count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) extern const struct cxl_backend_ops cxl_native_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) extern const struct cxl_backend_ops cxl_guest_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) extern const struct cxl_backend_ops *cxl_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) /* check if the given pci_dev is on the the cxl vphb bus */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) bool cxl_pci_is_vphb_device(struct pci_dev *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) /* decode AFU error bits in the PSL register PSL_SERR_An */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) void cxl_afu_decode_psl_serr(struct cxl_afu *afu, u64 serr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) * Increments the number of attached contexts on an adapter.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) * In case an adapter_context_lock is taken the return -EBUSY.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) int cxl_adapter_context_get(struct cxl *adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) /* Decrements the number of attached contexts on an adapter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) void cxl_adapter_context_put(struct cxl *adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) /* If no active contexts then prevents contexts from being attached */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) int cxl_adapter_context_lock(struct cxl *adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) /* Unlock the contexts-lock if taken. Warn and force unlock otherwise */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) void cxl_adapter_context_unlock(struct cxl *adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) /* Increases the reference count to "struct mm_struct" */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) void cxl_context_mm_count_get(struct cxl_context *ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) /* Decrements the reference count to "struct mm_struct" */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) void cxl_context_mm_count_put(struct cxl_context *ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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