^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Driver for the CS5535/CS5536 Multi-Function General Purpose Timers (MFGPT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2006, Advanced Micro Devices, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) 2007 Andres Salomon <dilinger@debian.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Copyright (C) 2009 Andres Salomon <dilinger@collabora.co.uk>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * The MFGPTs are documented in AMD Geode CS5536 Companion Device Data Book.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/spinlock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/cs5535.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define DRV_NAME "cs5535-mfgpt"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) static int mfgpt_reset_timers;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) module_param_named(mfgptfix, mfgpt_reset_timers, int, 0644);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) MODULE_PARM_DESC(mfgptfix, "Try to reset the MFGPT timers during init; "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) "required by some broken BIOSes (ie, TinyBIOS < 0.99) or kexec "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) "(1 = reset the MFGPT using an undocumented bit, "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) "2 = perform a soft reset by unconfiguring all timers); "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) "use what works best for you.");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) struct cs5535_mfgpt_timer {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) struct cs5535_mfgpt_chip *chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) int nr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) static struct cs5535_mfgpt_chip {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) DECLARE_BITMAP(avail, MFGPT_MAX_TIMERS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) resource_size_t base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) struct platform_device *pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) spinlock_t lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) int initialized;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) } cs5535_mfgpt_chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) int cs5535_mfgpt_toggle_event(struct cs5535_mfgpt_timer *timer, int cmp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) int event, int enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) uint32_t msr, mask, value, dummy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) int shift = (cmp == MFGPT_CMP1) ? 0 : 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) if (!timer) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) WARN_ON(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) * The register maps for these are described in sections 6.17.1.x of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) * the AMD Geode CS5536 Companion Device Data Book.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) switch (event) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) case MFGPT_EVENT_RESET:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) * XXX: According to the docs, we cannot reset timers above
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) * 6; that is, resets for 7 and 8 will be ignored. Is this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) * a problem? -dilinger
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) msr = MSR_MFGPT_NR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) mask = 1 << (timer->nr + 24);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) case MFGPT_EVENT_NMI:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) msr = MSR_MFGPT_NR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) mask = 1 << (timer->nr + shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) case MFGPT_EVENT_IRQ:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) msr = MSR_MFGPT_IRQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) mask = 1 << (timer->nr + shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) rdmsr(msr, value, dummy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) if (enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) value |= mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) value &= ~mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) wrmsr(msr, value, dummy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) EXPORT_SYMBOL_GPL(cs5535_mfgpt_toggle_event);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) int cs5535_mfgpt_set_irq(struct cs5535_mfgpt_timer *timer, int cmp, int *irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) int enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) uint32_t zsel, lpc, dummy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) int shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) if (!timer) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) WARN_ON(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) * Unfortunately, MFGPTs come in pairs sharing their IRQ lines. If VSA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) * is using the same CMP of the timer's Siamese twin, the IRQ is set to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) * 2, and we mustn't use nor change it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) * XXX: Likewise, 2 Linux drivers might clash if the 2nd overwrites the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) * IRQ of the 1st. This can only happen if forcing an IRQ, calling this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) * with *irq==0 is safe. Currently there _are_ no 2 drivers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) rdmsr(MSR_PIC_ZSEL_LOW, zsel, dummy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) shift = ((cmp == MFGPT_CMP1 ? 0 : 4) + timer->nr % 4) * 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) if (((zsel >> shift) & 0xF) == 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) /* Choose IRQ: if none supplied, keep IRQ already set or use default */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) if (!*irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) *irq = (zsel >> shift) & 0xF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) if (!*irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) *irq = CONFIG_CS5535_MFGPT_DEFAULT_IRQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) /* Can't use IRQ if it's 0 (=disabled), 2, or routed to LPC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) if (*irq < 1 || *irq == 2 || *irq > 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) rdmsr(MSR_PIC_IRQM_LPC, lpc, dummy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) if (lpc & (1 << *irq))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) /* All chosen and checked - go for it */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) if (cs5535_mfgpt_toggle_event(timer, cmp, MFGPT_EVENT_IRQ, enable))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) if (enable) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) zsel = (zsel & ~(0xF << shift)) | (*irq << shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) wrmsr(MSR_PIC_ZSEL_LOW, zsel, dummy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) EXPORT_SYMBOL_GPL(cs5535_mfgpt_set_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) struct cs5535_mfgpt_timer *cs5535_mfgpt_alloc_timer(int timer_nr, int domain)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) struct cs5535_mfgpt_chip *mfgpt = &cs5535_mfgpt_chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) struct cs5535_mfgpt_timer *timer = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) int max;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) if (!mfgpt->initialized)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) goto done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) /* only allocate timers from the working domain if requested */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) if (domain == MFGPT_DOMAIN_WORKING)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) max = 6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) max = MFGPT_MAX_TIMERS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) if (timer_nr >= max) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) /* programmer error. silly programmers! */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) WARN_ON(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) goto done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) spin_lock_irqsave(&mfgpt->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) if (timer_nr < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) unsigned long t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) /* try to find any available timer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) t = find_first_bit(mfgpt->avail, max);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) /* set timer_nr to -1 if no timers available */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) timer_nr = t < max ? (int) t : -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) /* check if the requested timer's available */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) if (!test_bit(timer_nr, mfgpt->avail))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) timer_nr = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) if (timer_nr >= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) /* if timer_nr is not -1, it's an available timer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) __clear_bit(timer_nr, mfgpt->avail);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) spin_unlock_irqrestore(&mfgpt->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) if (timer_nr < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) goto done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) timer = kmalloc(sizeof(*timer), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) if (!timer) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) /* aw hell */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) spin_lock_irqsave(&mfgpt->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) __set_bit(timer_nr, mfgpt->avail);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) spin_unlock_irqrestore(&mfgpt->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) goto done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) timer->chip = mfgpt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) timer->nr = timer_nr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) dev_info(&mfgpt->pdev->dev, "registered timer %d\n", timer_nr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) done:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) return timer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) EXPORT_SYMBOL_GPL(cs5535_mfgpt_alloc_timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) * XXX: This frees the timer memory, but never resets the actual hardware
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) * timer. The old geode_mfgpt code did this; it would be good to figure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) * out a way to actually release the hardware timer. See comments below.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) void cs5535_mfgpt_free_timer(struct cs5535_mfgpt_timer *timer)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) uint16_t val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) /* timer can be made available again only if never set up */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) val = cs5535_mfgpt_read(timer, MFGPT_REG_SETUP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) if (!(val & MFGPT_SETUP_SETUP)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) spin_lock_irqsave(&timer->chip->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) __set_bit(timer->nr, timer->chip->avail);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) spin_unlock_irqrestore(&timer->chip->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) kfree(timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) EXPORT_SYMBOL_GPL(cs5535_mfgpt_free_timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) uint16_t cs5535_mfgpt_read(struct cs5535_mfgpt_timer *timer, uint16_t reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) return inw(timer->chip->base + reg + (timer->nr * 8));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) EXPORT_SYMBOL_GPL(cs5535_mfgpt_read);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) void cs5535_mfgpt_write(struct cs5535_mfgpt_timer *timer, uint16_t reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) uint16_t value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) outw(value, timer->chip->base + reg + (timer->nr * 8));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) EXPORT_SYMBOL_GPL(cs5535_mfgpt_write);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) * This is a sledgehammer that resets all MFGPT timers. This is required by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) * some broken BIOSes which leave the system in an unstable state
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) * (TinyBIOS 0.98, for example; fixed in 0.99). It's uncertain as to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) * whether or not this secret MSR can be used to release individual timers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) * Jordan tells me that he and Mitch once played w/ it, but it's unclear
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) * what the results of that were (and they experienced some instability).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) static void reset_all_timers(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) uint32_t val, dummy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) /* The following undocumented bit resets the MFGPT timers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) val = 0xFF; dummy = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) wrmsr(MSR_MFGPT_SETUP, val, dummy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) * This is another sledgehammer to reset all MFGPT timers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) * Instead of using the undocumented bit method it clears
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) * IRQ, NMI and RESET settings.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) static void soft_reset(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) struct cs5535_mfgpt_timer t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) for (i = 0; i < MFGPT_MAX_TIMERS; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) t.nr = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) cs5535_mfgpt_toggle_event(&t, MFGPT_CMP1, MFGPT_EVENT_RESET, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) cs5535_mfgpt_toggle_event(&t, MFGPT_CMP2, MFGPT_EVENT_RESET, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) cs5535_mfgpt_toggle_event(&t, MFGPT_CMP1, MFGPT_EVENT_NMI, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) cs5535_mfgpt_toggle_event(&t, MFGPT_CMP2, MFGPT_EVENT_NMI, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) cs5535_mfgpt_toggle_event(&t, MFGPT_CMP1, MFGPT_EVENT_IRQ, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) cs5535_mfgpt_toggle_event(&t, MFGPT_CMP2, MFGPT_EVENT_IRQ, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) * Check whether any MFGPTs are available for the kernel to use. In most
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) * cases, firmware that uses AMD's VSA code will claim all timers during
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) * bootup; we certainly don't want to take them if they're already in use.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) * In other cases (such as with VSAless OpenFirmware), the system firmware
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) * leaves timers available for us to use.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) static int scan_timers(struct cs5535_mfgpt_chip *mfgpt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) struct cs5535_mfgpt_timer timer = { .chip = mfgpt };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) int timers = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) uint16_t val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) /* bios workaround */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) if (mfgpt_reset_timers == 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) reset_all_timers();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) else if (mfgpt_reset_timers == 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) soft_reset();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) /* just to be safe, protect this section w/ lock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) spin_lock_irqsave(&mfgpt->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) for (i = 0; i < MFGPT_MAX_TIMERS; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) timer.nr = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) val = cs5535_mfgpt_read(&timer, MFGPT_REG_SETUP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) if (!(val & MFGPT_SETUP_SETUP) || mfgpt_reset_timers == 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) __set_bit(i, mfgpt->avail);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) timers++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) spin_unlock_irqrestore(&mfgpt->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) return timers;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) static int cs5535_mfgpt_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) int err = -EIO, t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) if (mfgpt_reset_timers < 0 || mfgpt_reset_timers > 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) dev_err(&pdev->dev, "Bad mfgpt_reset_timers value: %i\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) mfgpt_reset_timers);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) goto done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) /* There are two ways to get the MFGPT base address; one is by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) * fetching it from MSR_LBAR_MFGPT, the other is by reading the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) * PCI BAR info. The latter method is easier (especially across
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) * different architectures), so we'll stick with that for now. If
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) * it turns out to be unreliable in the face of crappy BIOSes, we
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) * can always go back to using MSRs.. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) res = platform_get_resource(pdev, IORESOURCE_IO, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) if (!res) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) dev_err(&pdev->dev, "can't fetch device resource info\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) goto done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) if (!request_region(res->start, resource_size(res), pdev->name)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) dev_err(&pdev->dev, "can't request region\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) goto done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) /* set up the driver-specific struct */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) cs5535_mfgpt_chip.base = res->start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) cs5535_mfgpt_chip.pdev = pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) spin_lock_init(&cs5535_mfgpt_chip.lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) dev_info(&pdev->dev, "reserved resource region %pR\n", res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) /* detect the available timers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) t = scan_timers(&cs5535_mfgpt_chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) dev_info(&pdev->dev, "%d MFGPT timers available\n", t);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) cs5535_mfgpt_chip.initialized = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) done:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) static struct platform_driver cs5535_mfgpt_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) .name = DRV_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) .probe = cs5535_mfgpt_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) static int __init cs5535_mfgpt_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) return platform_driver_register(&cs5535_mfgpt_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) module_init(cs5535_mfgpt_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) MODULE_AUTHOR("Andres Salomon <dilinger@queued.net>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) MODULE_DESCRIPTION("CS5535/CS5536 MFGPT timer driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) MODULE_ALIAS("platform:" DRV_NAME);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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