^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-or-later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /* Driver for Realtek PCI-Express card reader
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright(c) 2009-2013 Realtek Semiconductor Corp. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Author:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Wei WANG <wei_wang@realsil.com.cn>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #ifndef __RTSX_PCR_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define __RTSX_PCR_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/rtsx_pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define MIN_DIV_N_PCR 80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define MAX_DIV_N_PCR 208
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define RTS522A_PM_CTRL3 0xFF7E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define RTS524A_PME_FORCE_CTL 0xFF78
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define REG_EFUSE_BYPASS 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define REG_EFUSE_POR 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define REG_EFUSE_POWER_MASK 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define REG_EFUSE_POWERON 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define REG_EFUSE_POWEROFF 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define RTS5250_CLK_CFG3 0xFF79
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define RTS525A_CFG_MEM_PD 0xF0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define RTS524A_PM_CTRL3 0xFF7E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define RTS525A_BIOS_CFG 0xFF2D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define RTS525A_LOAD_BIOS_FLAG 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define RTS525A_CLEAR_BIOS_FLAG 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define RTS525A_EFUSE_CTL 0xFC32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define REG_EFUSE_ENABLE 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define REG_EFUSE_MODE 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define RTS525A_EFUSE_ADD 0xFC33
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define REG_EFUSE_ADD_MASK 0x3F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define RTS525A_EFUSE_DATA 0xFC35
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define LTR_ACTIVE_LATENCY_DEF 0x883C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define LTR_IDLE_LATENCY_DEF 0x892C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define LTR_L1OFF_LATENCY_DEF 0x9003
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define L1_SNOOZE_DELAY_DEF 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define LTR_L1OFF_SSPWRGATE_5249_DEF 0xAF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define LTR_L1OFF_SSPWRGATE_5250_DEF 0xFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define LTR_L1OFF_SNOOZE_SSPWRGATE_5249_DEF 0xAC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define LTR_L1OFF_SNOOZE_SSPWRGATE_5250_DEF 0xF8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define CMD_TIMEOUT_DEF 100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define MASK_8_BIT_DEF 0xFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define SSC_CLOCK_STABLE_WAIT 130
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define RTS524A_OCP_THD_800 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define RTS525A_OCP_THD_800 0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define RTS522A_OCP_THD_800 0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) int __rtsx_pci_write_phy_register(struct rtsx_pcr *pcr, u8 addr, u16 val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) int __rtsx_pci_read_phy_register(struct rtsx_pcr *pcr, u8 addr, u16 *val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) void rts5209_init_params(struct rtsx_pcr *pcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) void rts5229_init_params(struct rtsx_pcr *pcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) void rtl8411_init_params(struct rtsx_pcr *pcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) void rtl8402_init_params(struct rtsx_pcr *pcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) void rts5227_init_params(struct rtsx_pcr *pcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) void rts522a_init_params(struct rtsx_pcr *pcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) void rts5249_init_params(struct rtsx_pcr *pcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) void rts524a_init_params(struct rtsx_pcr *pcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) void rts525a_init_params(struct rtsx_pcr *pcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) void rtl8411b_init_params(struct rtsx_pcr *pcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) void rts5260_init_params(struct rtsx_pcr *pcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) void rts5261_init_params(struct rtsx_pcr *pcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) void rts5228_init_params(struct rtsx_pcr *pcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) static inline u8 map_sd_drive(int idx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) u8 sd_drive[4] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) 0x01, /* Type D */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) 0x02, /* Type C */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) 0x05, /* Type A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) 0x03 /* Type B */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) return sd_drive[idx];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define rtsx_vendor_setting_valid(reg) (!((reg) & 0x1000000))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define rts5209_vendor_setting1_valid(reg) (!((reg) & 0x80))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define rts5209_vendor_setting2_valid(reg) ((reg) & 0x80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define rtsx_check_mmc_support(reg) ((reg) & 0x10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define rtsx_reg_to_rtd3(reg) ((reg) & 0x02)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define rtsx_reg_to_aspm(reg) (((reg) >> 28) & 0x03)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define rtsx_reg_to_sd30_drive_sel_1v8(reg) (((reg) >> 26) & 0x03)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define rtsx_reg_to_sd30_drive_sel_3v3(reg) (((reg) >> 5) & 0x03)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define rtsx_reg_to_card_drive_sel(reg) ((((reg) >> 25) & 0x01) << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define rtsx_reg_check_reverse_socket(reg) ((reg) & 0x4000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define rts5209_reg_to_aspm(reg) (((reg) >> 5) & 0x03)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define rts5209_reg_check_ms_pmos(reg) (!((reg) & 0x08))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define rts5209_reg_to_sd30_drive_sel_1v8(reg) (((reg) >> 3) & 0x07)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define rts5209_reg_to_sd30_drive_sel_3v3(reg) ((reg) & 0x07)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define rts5209_reg_to_card_drive_sel(reg) ((reg) >> 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define rtl8411_reg_to_sd30_drive_sel_3v3(reg) (((reg) >> 5) & 0x07)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define rtl8411b_reg_to_sd30_drive_sel_3v3(reg) ((reg) & 0x03)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define set_pull_ctrl_tables(pcr, __device) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) do { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) pcr->sd_pull_ctl_enable_tbl = __device##_sd_pull_ctl_enable_tbl; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) pcr->sd_pull_ctl_disable_tbl = __device##_sd_pull_ctl_disable_tbl; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) pcr->ms_pull_ctl_enable_tbl = __device##_ms_pull_ctl_enable_tbl; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) pcr->ms_pull_ctl_disable_tbl = __device##_ms_pull_ctl_disable_tbl; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) } while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) /* generic operations */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) int rtsx_gops_pm_reset(struct rtsx_pcr *pcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) int rtsx_set_ltr_latency(struct rtsx_pcr *pcr, u32 latency);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) int rtsx_set_l1off_sub(struct rtsx_pcr *pcr, u8 val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) void rtsx_pci_init_ocp(struct rtsx_pcr *pcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) void rtsx_pci_disable_ocp(struct rtsx_pcr *pcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) void rtsx_pci_enable_ocp(struct rtsx_pcr *pcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) int rtsx_pci_get_ocpstat(struct rtsx_pcr *pcr, u8 *val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) void rtsx_pci_clear_ocpstat(struct rtsx_pcr *pcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) void rtsx_pci_enable_oobs_polling(struct rtsx_pcr *pcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) void rtsx_pci_disable_oobs_polling(struct rtsx_pcr *pcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) int rtsx_sd_power_off_card3v3(struct rtsx_pcr *pcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) int rtsx_ms_power_off_card3v3(struct rtsx_pcr *pcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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