^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /* Driver for Realtek PCI-Express card reader
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright(c) 2009-2013 Realtek Semiconductor Corp. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Author:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Wei WANG <wei_wang@realsil.com.cn>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/dma-mapping.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/highmem.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/idr.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/mfd/core.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/rtsx_pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/mmc/card.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <asm/unaligned.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include "rtsx_pcr.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include "rts5261.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include "rts5228.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) static bool msi_en = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) module_param(msi_en, bool, S_IRUGO | S_IWUSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) MODULE_PARM_DESC(msi_en, "Enable MSI");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) static DEFINE_IDR(rtsx_pci_idr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) static DEFINE_SPINLOCK(rtsx_pci_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) static struct mfd_cell rtsx_pcr_cells[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) [RTSX_SD_CARD] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) .name = DRV_NAME_RTSX_PCI_SDMMC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) static const struct pci_device_id rtsx_pci_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) { PCI_DEVICE(0x10EC, 0x5209), PCI_CLASS_OTHERS << 16, 0xFF0000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) { PCI_DEVICE(0x10EC, 0x5229), PCI_CLASS_OTHERS << 16, 0xFF0000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) { PCI_DEVICE(0x10EC, 0x5289), PCI_CLASS_OTHERS << 16, 0xFF0000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) { PCI_DEVICE(0x10EC, 0x5227), PCI_CLASS_OTHERS << 16, 0xFF0000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) { PCI_DEVICE(0x10EC, 0x522A), PCI_CLASS_OTHERS << 16, 0xFF0000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) { PCI_DEVICE(0x10EC, 0x5249), PCI_CLASS_OTHERS << 16, 0xFF0000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) { PCI_DEVICE(0x10EC, 0x5287), PCI_CLASS_OTHERS << 16, 0xFF0000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) { PCI_DEVICE(0x10EC, 0x5286), PCI_CLASS_OTHERS << 16, 0xFF0000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) { PCI_DEVICE(0x10EC, 0x524A), PCI_CLASS_OTHERS << 16, 0xFF0000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) { PCI_DEVICE(0x10EC, 0x525A), PCI_CLASS_OTHERS << 16, 0xFF0000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) { PCI_DEVICE(0x10EC, 0x5260), PCI_CLASS_OTHERS << 16, 0xFF0000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) { PCI_DEVICE(0x10EC, 0x5261), PCI_CLASS_OTHERS << 16, 0xFF0000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) { PCI_DEVICE(0x10EC, 0x5228), PCI_CLASS_OTHERS << 16, 0xFF0000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) { 0, }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) MODULE_DEVICE_TABLE(pci, rtsx_pci_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) static inline void rtsx_pci_disable_aspm(struct rtsx_pcr *pcr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) pcie_capability_clear_and_set_word(pcr->pci, PCI_EXP_LNKCTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) PCI_EXP_LNKCTL_ASPMC, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) static int rtsx_comm_set_ltr_latency(struct rtsx_pcr *pcr, u32 latency)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) rtsx_pci_write_register(pcr, MSGTXDATA0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) MASK_8_BIT_DEF, (u8) (latency & 0xFF));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) rtsx_pci_write_register(pcr, MSGTXDATA1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) MASK_8_BIT_DEF, (u8)((latency >> 8) & 0xFF));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) rtsx_pci_write_register(pcr, MSGTXDATA2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) MASK_8_BIT_DEF, (u8)((latency >> 16) & 0xFF));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) rtsx_pci_write_register(pcr, MSGTXDATA3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) MASK_8_BIT_DEF, (u8)((latency >> 24) & 0xFF));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) rtsx_pci_write_register(pcr, LTR_CTL, LTR_TX_EN_MASK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) LTR_LATENCY_MODE_MASK, LTR_TX_EN_1 | LTR_LATENCY_MODE_SW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) int rtsx_set_ltr_latency(struct rtsx_pcr *pcr, u32 latency)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) return rtsx_comm_set_ltr_latency(pcr, latency);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) static void rtsx_comm_set_aspm(struct rtsx_pcr *pcr, bool enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) if (pcr->aspm_enabled == enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) pcie_capability_clear_and_set_word(pcr->pci, PCI_EXP_LNKCTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) PCI_EXP_LNKCTL_ASPMC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) enable ? pcr->aspm_en : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) pcr->aspm_enabled = enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) static void rtsx_disable_aspm(struct rtsx_pcr *pcr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) if (pcr->ops->set_aspm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) pcr->ops->set_aspm(pcr, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) rtsx_comm_set_aspm(pcr, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) int rtsx_set_l1off_sub(struct rtsx_pcr *pcr, u8 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) rtsx_pci_write_register(pcr, L1SUB_CONFIG3, 0xFF, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) static void rtsx_set_l1off_sub_cfg_d0(struct rtsx_pcr *pcr, int active)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) if (pcr->ops->set_l1off_cfg_sub_d0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) pcr->ops->set_l1off_cfg_sub_d0(pcr, active);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) static void rtsx_comm_pm_full_on(struct rtsx_pcr *pcr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) struct rtsx_cr_option *option = &pcr->option;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) rtsx_disable_aspm(pcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) /* Fixes DMA transfer timout issue after disabling ASPM on RTS5260 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) msleep(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) if (option->ltr_enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) rtsx_set_ltr_latency(pcr, option->ltr_active_latency);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) if (rtsx_check_dev_flag(pcr, LTR_L1SS_PWR_GATE_EN))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) rtsx_set_l1off_sub_cfg_d0(pcr, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) static void rtsx_pm_full_on(struct rtsx_pcr *pcr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) rtsx_comm_pm_full_on(pcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) void rtsx_pci_start_run(struct rtsx_pcr *pcr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) /* If pci device removed, don't queue idle work any more */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) if (pcr->remove_pci)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) if (pcr->state != PDEV_STAT_RUN) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) pcr->state = PDEV_STAT_RUN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) if (pcr->ops->enable_auto_blink)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) pcr->ops->enable_auto_blink(pcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) rtsx_pm_full_on(pcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) mod_delayed_work(system_wq, &pcr->idle_work, msecs_to_jiffies(200));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) EXPORT_SYMBOL_GPL(rtsx_pci_start_run);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) int rtsx_pci_write_register(struct rtsx_pcr *pcr, u16 addr, u8 mask, u8 data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) u32 val = HAIMR_WRITE_START;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) val |= (u32)(addr & 0x3FFF) << 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) val |= (u32)mask << 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) val |= (u32)data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) rtsx_pci_writel(pcr, RTSX_HAIMR, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) for (i = 0; i < MAX_RW_REG_CNT; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) val = rtsx_pci_readl(pcr, RTSX_HAIMR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) if ((val & HAIMR_TRANS_END) == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) if (data != (u8)val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) EXPORT_SYMBOL_GPL(rtsx_pci_write_register);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) int rtsx_pci_read_register(struct rtsx_pcr *pcr, u16 addr, u8 *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) u32 val = HAIMR_READ_START;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) val |= (u32)(addr & 0x3FFF) << 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) rtsx_pci_writel(pcr, RTSX_HAIMR, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) for (i = 0; i < MAX_RW_REG_CNT; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) val = rtsx_pci_readl(pcr, RTSX_HAIMR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) if ((val & HAIMR_TRANS_END) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) if (i >= MAX_RW_REG_CNT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) if (data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) *data = (u8)(val & 0xFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) EXPORT_SYMBOL_GPL(rtsx_pci_read_register);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) int __rtsx_pci_write_phy_register(struct rtsx_pcr *pcr, u8 addr, u16 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) int err, i, finished = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) u8 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) rtsx_pci_write_register(pcr, PHYDATA0, 0xFF, (u8)val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) rtsx_pci_write_register(pcr, PHYDATA1, 0xFF, (u8)(val >> 8));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) rtsx_pci_write_register(pcr, PHYADDR, 0xFF, addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) rtsx_pci_write_register(pcr, PHYRWCTL, 0xFF, 0x81);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) for (i = 0; i < 100000; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) err = rtsx_pci_read_register(pcr, PHYRWCTL, &tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) if (!(tmp & 0x80)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) finished = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) if (!finished)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) int rtsx_pci_write_phy_register(struct rtsx_pcr *pcr, u8 addr, u16 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) if (pcr->ops->write_phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) return pcr->ops->write_phy(pcr, addr, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) return __rtsx_pci_write_phy_register(pcr, addr, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) EXPORT_SYMBOL_GPL(rtsx_pci_write_phy_register);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) int __rtsx_pci_read_phy_register(struct rtsx_pcr *pcr, u8 addr, u16 *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) int err, i, finished = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) u16 data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) u8 tmp, val1, val2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) rtsx_pci_write_register(pcr, PHYADDR, 0xFF, addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) rtsx_pci_write_register(pcr, PHYRWCTL, 0xFF, 0x80);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) for (i = 0; i < 100000; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) err = rtsx_pci_read_register(pcr, PHYRWCTL, &tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) if (!(tmp & 0x80)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) finished = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) if (!finished)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) rtsx_pci_read_register(pcr, PHYDATA0, &val1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) rtsx_pci_read_register(pcr, PHYDATA1, &val2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) data = val1 | (val2 << 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) if (val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) *val = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) int rtsx_pci_read_phy_register(struct rtsx_pcr *pcr, u8 addr, u16 *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) if (pcr->ops->read_phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) return pcr->ops->read_phy(pcr, addr, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) return __rtsx_pci_read_phy_register(pcr, addr, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) EXPORT_SYMBOL_GPL(rtsx_pci_read_phy_register);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) void rtsx_pci_stop_cmd(struct rtsx_pcr *pcr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) if (pcr->ops->stop_cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) return pcr->ops->stop_cmd(pcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) rtsx_pci_writel(pcr, RTSX_HCBCTLR, STOP_CMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) rtsx_pci_writel(pcr, RTSX_HDBCTLR, STOP_DMA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) rtsx_pci_write_register(pcr, DMACTL, 0x80, 0x80);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) rtsx_pci_write_register(pcr, RBCTL, 0x80, 0x80);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) EXPORT_SYMBOL_GPL(rtsx_pci_stop_cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) void rtsx_pci_add_cmd(struct rtsx_pcr *pcr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) u8 cmd_type, u16 reg_addr, u8 mask, u8 data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) u32 val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) u32 *ptr = (u32 *)(pcr->host_cmds_ptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) val |= (u32)(cmd_type & 0x03) << 30;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) val |= (u32)(reg_addr & 0x3FFF) << 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) val |= (u32)mask << 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) val |= (u32)data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) spin_lock_irqsave(&pcr->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) ptr += pcr->ci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) if (pcr->ci < (HOST_CMDS_BUF_LEN / 4)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) put_unaligned_le32(val, ptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) ptr++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) pcr->ci++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) spin_unlock_irqrestore(&pcr->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) EXPORT_SYMBOL_GPL(rtsx_pci_add_cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) void rtsx_pci_send_cmd_no_wait(struct rtsx_pcr *pcr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) u32 val = 1 << 31;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) rtsx_pci_writel(pcr, RTSX_HCBAR, pcr->host_cmds_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) val |= (u32)(pcr->ci * 4) & 0x00FFFFFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) /* Hardware Auto Response */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) val |= 0x40000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) rtsx_pci_writel(pcr, RTSX_HCBCTLR, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) EXPORT_SYMBOL_GPL(rtsx_pci_send_cmd_no_wait);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) int rtsx_pci_send_cmd(struct rtsx_pcr *pcr, int timeout)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) struct completion trans_done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) u32 val = 1 << 31;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) long timeleft;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) int err = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) spin_lock_irqsave(&pcr->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) /* set up data structures for the wakeup system */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) pcr->done = &trans_done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) pcr->trans_result = TRANS_NOT_READY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) init_completion(&trans_done);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) rtsx_pci_writel(pcr, RTSX_HCBAR, pcr->host_cmds_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) val |= (u32)(pcr->ci * 4) & 0x00FFFFFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) /* Hardware Auto Response */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) val |= 0x40000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) rtsx_pci_writel(pcr, RTSX_HCBCTLR, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) spin_unlock_irqrestore(&pcr->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) /* Wait for TRANS_OK_INT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) timeleft = wait_for_completion_interruptible_timeout(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) &trans_done, msecs_to_jiffies(timeout));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) if (timeleft <= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) pcr_dbg(pcr, "Timeout (%s %d)\n", __func__, __LINE__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) err = -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) goto finish_send_cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) spin_lock_irqsave(&pcr->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) if (pcr->trans_result == TRANS_RESULT_FAIL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) err = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) else if (pcr->trans_result == TRANS_RESULT_OK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) err = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) else if (pcr->trans_result == TRANS_NO_DEVICE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) err = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) spin_unlock_irqrestore(&pcr->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) finish_send_cmd:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) spin_lock_irqsave(&pcr->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) pcr->done = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) spin_unlock_irqrestore(&pcr->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) if ((err < 0) && (err != -ENODEV))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) rtsx_pci_stop_cmd(pcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) if (pcr->finish_me)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) complete(pcr->finish_me);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) EXPORT_SYMBOL_GPL(rtsx_pci_send_cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) static void rtsx_pci_add_sg_tbl(struct rtsx_pcr *pcr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) dma_addr_t addr, unsigned int len, int end)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) u64 *ptr = (u64 *)(pcr->host_sg_tbl_ptr) + pcr->sgi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) u64 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) u8 option = RTSX_SG_VALID | RTSX_SG_TRANS_DATA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) pcr_dbg(pcr, "DMA addr: 0x%x, Len: 0x%x\n", (unsigned int)addr, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) if (end)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) option |= RTSX_SG_END;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) if ((PCI_PID(pcr) == PID_5261) || (PCI_PID(pcr) == PID_5228)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) if (len > 0xFFFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) val = ((u64)addr << 32) | (((u64)len & 0xFFFF) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) | (((u64)len >> 16) << 6) | option;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) val = ((u64)addr << 32) | ((u64)len << 16) | option;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) val = ((u64)addr << 32) | ((u64)len << 12) | option;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) put_unaligned_le64(val, ptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) pcr->sgi++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) int rtsx_pci_transfer_data(struct rtsx_pcr *pcr, struct scatterlist *sglist,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) int num_sg, bool read, int timeout)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) int err = 0, count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) pcr_dbg(pcr, "--> %s: num_sg = %d\n", __func__, num_sg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) count = rtsx_pci_dma_map_sg(pcr, sglist, num_sg, read);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) if (count < 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) pcr_dbg(pcr, "DMA mapping count: %d\n", count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) err = rtsx_pci_dma_transfer(pcr, sglist, count, read, timeout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) rtsx_pci_dma_unmap_sg(pcr, sglist, num_sg, read);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) EXPORT_SYMBOL_GPL(rtsx_pci_transfer_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) int rtsx_pci_dma_map_sg(struct rtsx_pcr *pcr, struct scatterlist *sglist,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) int num_sg, bool read)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) enum dma_data_direction dir = read ? DMA_FROM_DEVICE : DMA_TO_DEVICE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) if (pcr->remove_pci)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) if ((sglist == NULL) || (num_sg <= 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) return dma_map_sg(&(pcr->pci->dev), sglist, num_sg, dir);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) EXPORT_SYMBOL_GPL(rtsx_pci_dma_map_sg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) void rtsx_pci_dma_unmap_sg(struct rtsx_pcr *pcr, struct scatterlist *sglist,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) int num_sg, bool read)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) enum dma_data_direction dir = read ? DMA_FROM_DEVICE : DMA_TO_DEVICE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) dma_unmap_sg(&(pcr->pci->dev), sglist, num_sg, dir);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) EXPORT_SYMBOL_GPL(rtsx_pci_dma_unmap_sg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) int rtsx_pci_dma_transfer(struct rtsx_pcr *pcr, struct scatterlist *sglist,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) int count, bool read, int timeout)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) struct completion trans_done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) struct scatterlist *sg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) dma_addr_t addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) long timeleft;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) unsigned int len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) int i, err = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) u8 dir = read ? DEVICE_TO_HOST : HOST_TO_DEVICE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) if (pcr->remove_pci)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) if ((sglist == NULL) || (count < 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) val = ((u32)(dir & 0x01) << 29) | TRIG_DMA | ADMA_MODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) pcr->sgi = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) for_each_sg(sglist, sg, count, i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) addr = sg_dma_address(sg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) len = sg_dma_len(sg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) rtsx_pci_add_sg_tbl(pcr, addr, len, i == count - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) spin_lock_irqsave(&pcr->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) pcr->done = &trans_done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) pcr->trans_result = TRANS_NOT_READY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) init_completion(&trans_done);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) rtsx_pci_writel(pcr, RTSX_HDBAR, pcr->host_sg_tbl_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) rtsx_pci_writel(pcr, RTSX_HDBCTLR, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) spin_unlock_irqrestore(&pcr->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) timeleft = wait_for_completion_interruptible_timeout(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) &trans_done, msecs_to_jiffies(timeout));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) if (timeleft <= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) pcr_dbg(pcr, "Timeout (%s %d)\n", __func__, __LINE__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) err = -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) spin_lock_irqsave(&pcr->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) if (pcr->trans_result == TRANS_RESULT_FAIL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) err = -EILSEQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) if (pcr->dma_error_count < RTS_MAX_TIMES_FREQ_REDUCTION)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) pcr->dma_error_count++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) else if (pcr->trans_result == TRANS_NO_DEVICE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) err = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) spin_unlock_irqrestore(&pcr->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) spin_lock_irqsave(&pcr->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) pcr->done = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) spin_unlock_irqrestore(&pcr->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) if ((err < 0) && (err != -ENODEV))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) rtsx_pci_stop_cmd(pcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) if (pcr->finish_me)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) complete(pcr->finish_me);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) EXPORT_SYMBOL_GPL(rtsx_pci_dma_transfer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) int rtsx_pci_read_ppbuf(struct rtsx_pcr *pcr, u8 *buf, int buf_len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) int i, j;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) u16 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) u8 *ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) if (buf_len > 512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) buf_len = 512;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) ptr = buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) reg = PPBUF_BASE2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) for (i = 0; i < buf_len / 256; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) rtsx_pci_init_cmd(pcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) for (j = 0; j < 256; j++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) rtsx_pci_add_cmd(pcr, READ_REG_CMD, reg++, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) err = rtsx_pci_send_cmd(pcr, 250);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) memcpy(ptr, rtsx_pci_get_cmd_data(pcr), 256);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) ptr += 256;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) if (buf_len % 256) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) rtsx_pci_init_cmd(pcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) for (j = 0; j < buf_len % 256; j++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) rtsx_pci_add_cmd(pcr, READ_REG_CMD, reg++, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) err = rtsx_pci_send_cmd(pcr, 250);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) memcpy(ptr, rtsx_pci_get_cmd_data(pcr), buf_len % 256);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) EXPORT_SYMBOL_GPL(rtsx_pci_read_ppbuf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) int rtsx_pci_write_ppbuf(struct rtsx_pcr *pcr, u8 *buf, int buf_len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) int i, j;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) u16 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) u8 *ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) if (buf_len > 512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) buf_len = 512;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) ptr = buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) reg = PPBUF_BASE2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) for (i = 0; i < buf_len / 256; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) rtsx_pci_init_cmd(pcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) for (j = 0; j < 256; j++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) rtsx_pci_add_cmd(pcr, WRITE_REG_CMD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) reg++, 0xFF, *ptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) ptr++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) err = rtsx_pci_send_cmd(pcr, 250);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) if (buf_len % 256) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) rtsx_pci_init_cmd(pcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) for (j = 0; j < buf_len % 256; j++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) rtsx_pci_add_cmd(pcr, WRITE_REG_CMD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) reg++, 0xFF, *ptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) ptr++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) err = rtsx_pci_send_cmd(pcr, 250);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) EXPORT_SYMBOL_GPL(rtsx_pci_write_ppbuf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) static int rtsx_pci_set_pull_ctl(struct rtsx_pcr *pcr, const u32 *tbl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) rtsx_pci_init_cmd(pcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) while (*tbl & 0xFFFF0000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) rtsx_pci_add_cmd(pcr, WRITE_REG_CMD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) (u16)(*tbl >> 16), 0xFF, (u8)(*tbl));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) tbl++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) return rtsx_pci_send_cmd(pcr, 100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) int rtsx_pci_card_pull_ctl_enable(struct rtsx_pcr *pcr, int card)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) const u32 *tbl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) if (card == RTSX_SD_CARD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) tbl = pcr->sd_pull_ctl_enable_tbl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) else if (card == RTSX_MS_CARD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) tbl = pcr->ms_pull_ctl_enable_tbl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) return rtsx_pci_set_pull_ctl(pcr, tbl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) EXPORT_SYMBOL_GPL(rtsx_pci_card_pull_ctl_enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) int rtsx_pci_card_pull_ctl_disable(struct rtsx_pcr *pcr, int card)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) const u32 *tbl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) if (card == RTSX_SD_CARD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) tbl = pcr->sd_pull_ctl_disable_tbl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) else if (card == RTSX_MS_CARD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) tbl = pcr->ms_pull_ctl_disable_tbl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) return rtsx_pci_set_pull_ctl(pcr, tbl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) EXPORT_SYMBOL_GPL(rtsx_pci_card_pull_ctl_disable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) static void rtsx_pci_enable_bus_int(struct rtsx_pcr *pcr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) struct rtsx_hw_param *hw_param = &pcr->hw_param;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) pcr->bier = TRANS_OK_INT_EN | TRANS_FAIL_INT_EN | SD_INT_EN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) | hw_param->interrupt_en;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) if (pcr->num_slots > 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) pcr->bier |= MS_INT_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) /* Enable Bus Interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) rtsx_pci_writel(pcr, RTSX_BIER, pcr->bier);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) pcr_dbg(pcr, "RTSX_BIER: 0x%08x\n", pcr->bier);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) static inline u8 double_ssc_depth(u8 depth)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) return ((depth > 1) ? (depth - 1) : depth);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) static u8 revise_ssc_depth(u8 ssc_depth, u8 div)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) if (div > CLK_DIV_1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) if (ssc_depth > (div - 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) ssc_depth -= (div - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) ssc_depth = SSC_DEPTH_4M;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) return ssc_depth;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) int rtsx_pci_switch_clock(struct rtsx_pcr *pcr, unsigned int card_clock,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) u8 ssc_depth, bool initial_mode, bool double_clk, bool vpclk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) int err, clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) u8 n, clk_divider, mcu_cnt, div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) static const u8 depth[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) [RTSX_SSC_DEPTH_4M] = SSC_DEPTH_4M,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) [RTSX_SSC_DEPTH_2M] = SSC_DEPTH_2M,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) [RTSX_SSC_DEPTH_1M] = SSC_DEPTH_1M,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) [RTSX_SSC_DEPTH_500K] = SSC_DEPTH_500K,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) [RTSX_SSC_DEPTH_250K] = SSC_DEPTH_250K,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) if (PCI_PID(pcr) == PID_5261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) return rts5261_pci_switch_clock(pcr, card_clock,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) ssc_depth, initial_mode, double_clk, vpclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) if (PCI_PID(pcr) == PID_5228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) return rts5228_pci_switch_clock(pcr, card_clock,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) ssc_depth, initial_mode, double_clk, vpclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) if (initial_mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) /* We use 250k(around) here, in initial stage */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) clk_divider = SD_CLK_DIVIDE_128;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) card_clock = 30000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) clk_divider = SD_CLK_DIVIDE_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) err = rtsx_pci_write_register(pcr, SD_CFG1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) SD_CLK_DIVIDE_MASK, clk_divider);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) /* Reduce card clock by 20MHz each time a DMA transfer error occurs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) if (card_clock == UHS_SDR104_MAX_DTR &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) pcr->dma_error_count &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) PCI_PID(pcr) == RTS5227_DEVICE_ID)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) card_clock = UHS_SDR104_MAX_DTR -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) (pcr->dma_error_count * 20000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) card_clock /= 1000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) pcr_dbg(pcr, "Switch card clock to %dMHz\n", card_clock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) clk = card_clock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) if (!initial_mode && double_clk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) clk = card_clock * 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) pcr_dbg(pcr, "Internal SSC clock: %dMHz (cur_clock = %d)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) clk, pcr->cur_clock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) if (clk == pcr->cur_clock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) if (pcr->ops->conv_clk_and_div_n)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) n = (u8)pcr->ops->conv_clk_and_div_n(clk, CLK_TO_DIV_N);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) n = (u8)(clk - 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) if ((clk <= 2) || (n > MAX_DIV_N_PCR))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) mcu_cnt = (u8)(125/clk + 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) if (mcu_cnt > 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) mcu_cnt = 15;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) /* Make sure that the SSC clock div_n is not less than MIN_DIV_N_PCR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) div = CLK_DIV_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) while ((n < MIN_DIV_N_PCR) && (div < CLK_DIV_8)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) if (pcr->ops->conv_clk_and_div_n) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) int dbl_clk = pcr->ops->conv_clk_and_div_n(n,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) DIV_N_TO_CLK) * 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) n = (u8)pcr->ops->conv_clk_and_div_n(dbl_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) CLK_TO_DIV_N);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) n = (n + 2) * 2 - 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) div++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) pcr_dbg(pcr, "n = %d, div = %d\n", n, div);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) ssc_depth = depth[ssc_depth];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) if (double_clk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) ssc_depth = double_ssc_depth(ssc_depth);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) ssc_depth = revise_ssc_depth(ssc_depth, div);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) pcr_dbg(pcr, "ssc_depth = %d\n", ssc_depth);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) rtsx_pci_init_cmd(pcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) CLK_LOW_FREQ, CLK_LOW_FREQ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_DIV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) 0xFF, (div << 4) | mcu_cnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL1, SSC_RSTB, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) SSC_DEPTH_MASK, ssc_depth);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_DIV_N_0, 0xFF, n);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL1, SSC_RSTB, SSC_RSTB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) if (vpclk) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_VPCLK0_CTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) PHASE_NOT_RESET, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_VPCLK0_CTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) PHASE_NOT_RESET, PHASE_NOT_RESET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) err = rtsx_pci_send_cmd(pcr, 2000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) /* Wait SSC clock stable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) udelay(SSC_CLOCK_STABLE_WAIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) err = rtsx_pci_write_register(pcr, CLK_CTL, CLK_LOW_FREQ, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) pcr->cur_clock = clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) EXPORT_SYMBOL_GPL(rtsx_pci_switch_clock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) int rtsx_pci_card_power_on(struct rtsx_pcr *pcr, int card)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) if (pcr->ops->card_power_on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) return pcr->ops->card_power_on(pcr, card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) EXPORT_SYMBOL_GPL(rtsx_pci_card_power_on);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) int rtsx_pci_card_power_off(struct rtsx_pcr *pcr, int card)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) if (pcr->ops->card_power_off)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) return pcr->ops->card_power_off(pcr, card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) EXPORT_SYMBOL_GPL(rtsx_pci_card_power_off);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) int rtsx_pci_card_exclusive_check(struct rtsx_pcr *pcr, int card)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) static const unsigned int cd_mask[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) [RTSX_SD_CARD] = SD_EXIST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) [RTSX_MS_CARD] = MS_EXIST
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) if (!(pcr->flags & PCR_MS_PMOS)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) /* When using single PMOS, accessing card is not permitted
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) * if the existing card is not the designated one.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) if (pcr->card_exist & (~cd_mask[card]))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) EXPORT_SYMBOL_GPL(rtsx_pci_card_exclusive_check);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) int rtsx_pci_switch_output_voltage(struct rtsx_pcr *pcr, u8 voltage)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) if (pcr->ops->switch_output_voltage)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) return pcr->ops->switch_output_voltage(pcr, voltage);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) EXPORT_SYMBOL_GPL(rtsx_pci_switch_output_voltage);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) unsigned int rtsx_pci_card_exist(struct rtsx_pcr *pcr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) unsigned int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) val = rtsx_pci_readl(pcr, RTSX_BIPR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) if (pcr->ops->cd_deglitch)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) val = pcr->ops->cd_deglitch(pcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) EXPORT_SYMBOL_GPL(rtsx_pci_card_exist);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) void rtsx_pci_complete_unfinished_transfer(struct rtsx_pcr *pcr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) struct completion finish;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) pcr->finish_me = &finish;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) init_completion(&finish);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) if (pcr->done)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) complete(pcr->done);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) if (!pcr->remove_pci)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) rtsx_pci_stop_cmd(pcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) wait_for_completion_interruptible_timeout(&finish,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) msecs_to_jiffies(2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) pcr->finish_me = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) EXPORT_SYMBOL_GPL(rtsx_pci_complete_unfinished_transfer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) static void rtsx_pci_card_detect(struct work_struct *work)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) struct delayed_work *dwork;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) struct rtsx_pcr *pcr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) unsigned int card_detect = 0, card_inserted, card_removed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) u32 irq_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) dwork = to_delayed_work(work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) pcr = container_of(dwork, struct rtsx_pcr, carddet_work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) pcr_dbg(pcr, "--> %s\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) mutex_lock(&pcr->pcr_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) spin_lock_irqsave(&pcr->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) irq_status = rtsx_pci_readl(pcr, RTSX_BIPR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) pcr_dbg(pcr, "irq_status: 0x%08x\n", irq_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) irq_status &= CARD_EXIST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) card_inserted = pcr->card_inserted & irq_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) card_removed = pcr->card_removed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) pcr->card_inserted = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) pcr->card_removed = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) spin_unlock_irqrestore(&pcr->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) if (card_inserted || card_removed) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) pcr_dbg(pcr, "card_inserted: 0x%x, card_removed: 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) card_inserted, card_removed);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) if (pcr->ops->cd_deglitch)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) card_inserted = pcr->ops->cd_deglitch(pcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) card_detect = card_inserted | card_removed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) pcr->card_exist |= card_inserted;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) pcr->card_exist &= ~card_removed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) mutex_unlock(&pcr->pcr_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) if ((card_detect & SD_EXIST) && pcr->slots[RTSX_SD_CARD].card_event)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) pcr->slots[RTSX_SD_CARD].card_event(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) pcr->slots[RTSX_SD_CARD].p_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) if ((card_detect & MS_EXIST) && pcr->slots[RTSX_MS_CARD].card_event)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) pcr->slots[RTSX_MS_CARD].card_event(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) pcr->slots[RTSX_MS_CARD].p_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) static void rtsx_pci_process_ocp(struct rtsx_pcr *pcr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) if (pcr->ops->process_ocp) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) pcr->ops->process_ocp(pcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) if (!pcr->option.ocp_en)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) rtsx_pci_get_ocpstat(pcr, &pcr->ocp_stat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) if (pcr->ocp_stat & (SD_OC_NOW | SD_OC_EVER)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) rtsx_pci_card_power_off(pcr, RTSX_SD_CARD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) rtsx_pci_write_register(pcr, CARD_OE, SD_OUTPUT_EN, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) rtsx_pci_clear_ocpstat(pcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) pcr->ocp_stat = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) static int rtsx_pci_process_ocp_interrupt(struct rtsx_pcr *pcr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) if (pcr->option.ocp_en)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) rtsx_pci_process_ocp(pcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) static irqreturn_t rtsx_pci_isr(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) struct rtsx_pcr *pcr = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) u32 int_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) if (!pcr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) spin_lock(&pcr->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) int_reg = rtsx_pci_readl(pcr, RTSX_BIPR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) /* Clear interrupt flag */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) rtsx_pci_writel(pcr, RTSX_BIPR, int_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) if ((int_reg & pcr->bier) == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) spin_unlock(&pcr->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) if (int_reg == 0xFFFFFFFF) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) spin_unlock(&pcr->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) int_reg &= (pcr->bier | 0x7FFFFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) if (int_reg & SD_OC_INT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) rtsx_pci_process_ocp_interrupt(pcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) if (int_reg & SD_INT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) if (int_reg & SD_EXIST) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) pcr->card_inserted |= SD_EXIST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) pcr->card_removed |= SD_EXIST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) pcr->card_inserted &= ~SD_EXIST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) pcr->dma_error_count = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) if (int_reg & MS_INT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) if (int_reg & MS_EXIST) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) pcr->card_inserted |= MS_EXIST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) pcr->card_removed |= MS_EXIST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) pcr->card_inserted &= ~MS_EXIST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) if (int_reg & (NEED_COMPLETE_INT | DELINK_INT)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) if (int_reg & (TRANS_FAIL_INT | DELINK_INT)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) pcr->trans_result = TRANS_RESULT_FAIL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) if (pcr->done)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) complete(pcr->done);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) } else if (int_reg & TRANS_OK_INT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) pcr->trans_result = TRANS_RESULT_OK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) if (pcr->done)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) complete(pcr->done);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) if ((pcr->card_inserted || pcr->card_removed) && !(int_reg & SD_OC_INT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) schedule_delayed_work(&pcr->carddet_work,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) msecs_to_jiffies(200));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) spin_unlock(&pcr->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) static int rtsx_pci_acquire_irq(struct rtsx_pcr *pcr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) pcr_dbg(pcr, "%s: pcr->msi_en = %d, pci->irq = %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) __func__, pcr->msi_en, pcr->pci->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) if (request_irq(pcr->pci->irq, rtsx_pci_isr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) pcr->msi_en ? 0 : IRQF_SHARED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) DRV_NAME_RTSX_PCI, pcr)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) dev_err(&(pcr->pci->dev),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) "rtsx_sdmmc: unable to grab IRQ %d, disabling device\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) pcr->pci->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) pcr->irq = pcr->pci->irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) pci_intx(pcr->pci, !pcr->msi_en);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) static void rtsx_enable_aspm(struct rtsx_pcr *pcr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) if (pcr->ops->set_aspm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) pcr->ops->set_aspm(pcr, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) rtsx_comm_set_aspm(pcr, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) static void rtsx_comm_pm_power_saving(struct rtsx_pcr *pcr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) struct rtsx_cr_option *option = &pcr->option;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) if (option->ltr_enabled) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) u32 latency = option->ltr_l1off_latency;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) if (rtsx_check_dev_flag(pcr, L1_SNOOZE_TEST_EN))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) mdelay(option->l1_snooze_delay);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) rtsx_set_ltr_latency(pcr, latency);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) if (rtsx_check_dev_flag(pcr, LTR_L1SS_PWR_GATE_EN))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) rtsx_set_l1off_sub_cfg_d0(pcr, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) rtsx_enable_aspm(pcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) static void rtsx_pm_power_saving(struct rtsx_pcr *pcr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) rtsx_comm_pm_power_saving(pcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) static void rtsx_pci_idle_work(struct work_struct *work)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) struct delayed_work *dwork = to_delayed_work(work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) struct rtsx_pcr *pcr = container_of(dwork, struct rtsx_pcr, idle_work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) pcr_dbg(pcr, "--> %s\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) mutex_lock(&pcr->pcr_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) pcr->state = PDEV_STAT_IDLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) if (pcr->ops->disable_auto_blink)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) pcr->ops->disable_auto_blink(pcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) if (pcr->ops->turn_off_led)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) pcr->ops->turn_off_led(pcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) rtsx_pm_power_saving(pcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) mutex_unlock(&pcr->pcr_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) static void rtsx_base_force_power_down(struct rtsx_pcr *pcr, u8 pm_state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) /* Set relink_time to 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) rtsx_pci_write_register(pcr, AUTOLOAD_CFG_BASE + 1, MASK_8_BIT_DEF, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) rtsx_pci_write_register(pcr, AUTOLOAD_CFG_BASE + 2, MASK_8_BIT_DEF, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) rtsx_pci_write_register(pcr, AUTOLOAD_CFG_BASE + 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) RELINK_TIME_MASK, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) rtsx_pci_write_register(pcr, pcr->reg_pm_ctrl3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) D3_DELINK_MODE_EN, D3_DELINK_MODE_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) rtsx_pci_write_register(pcr, FPDCTL, ALL_POWER_DOWN, ALL_POWER_DOWN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) static void __maybe_unused rtsx_pci_power_off(struct rtsx_pcr *pcr, u8 pm_state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) if (pcr->ops->turn_off_led)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) pcr->ops->turn_off_led(pcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) rtsx_pci_writel(pcr, RTSX_BIER, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) pcr->bier = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) rtsx_pci_write_register(pcr, PETXCFG, 0x08, 0x08);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) rtsx_pci_write_register(pcr, HOST_SLEEP_STATE, 0x03, pm_state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) if (pcr->ops->force_power_down)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) pcr->ops->force_power_down(pcr, pm_state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) rtsx_base_force_power_down(pcr, pm_state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) void rtsx_pci_enable_ocp(struct rtsx_pcr *pcr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) u8 val = SD_OCP_INT_EN | SD_DETECT_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) if (pcr->ops->enable_ocp) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) pcr->ops->enable_ocp(pcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) rtsx_pci_write_register(pcr, FPDCTL, OC_POWER_DOWN, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) rtsx_pci_write_register(pcr, REG_OCPCTL, 0xFF, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) void rtsx_pci_disable_ocp(struct rtsx_pcr *pcr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) u8 mask = SD_OCP_INT_EN | SD_DETECT_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) if (pcr->ops->disable_ocp) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) pcr->ops->disable_ocp(pcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) rtsx_pci_write_register(pcr, REG_OCPCTL, mask, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) rtsx_pci_write_register(pcr, FPDCTL, OC_POWER_DOWN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) OC_POWER_DOWN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) void rtsx_pci_init_ocp(struct rtsx_pcr *pcr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) if (pcr->ops->init_ocp) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) pcr->ops->init_ocp(pcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) struct rtsx_cr_option *option = &(pcr->option);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) if (option->ocp_en) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) u8 val = option->sd_800mA_ocp_thd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) rtsx_pci_write_register(pcr, FPDCTL, OC_POWER_DOWN, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) rtsx_pci_write_register(pcr, REG_OCPPARA1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) SD_OCP_TIME_MASK, SD_OCP_TIME_800);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) rtsx_pci_write_register(pcr, REG_OCPPARA2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) SD_OCP_THD_MASK, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) rtsx_pci_write_register(pcr, REG_OCPGLITCH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) SD_OCP_GLITCH_MASK, pcr->hw_param.ocp_glitch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) rtsx_pci_enable_ocp(pcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) int rtsx_pci_get_ocpstat(struct rtsx_pcr *pcr, u8 *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) if (pcr->ops->get_ocpstat)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) return pcr->ops->get_ocpstat(pcr, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) return rtsx_pci_read_register(pcr, REG_OCPSTAT, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) void rtsx_pci_clear_ocpstat(struct rtsx_pcr *pcr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) if (pcr->ops->clear_ocpstat) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) pcr->ops->clear_ocpstat(pcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) u8 mask = SD_OCP_INT_CLR | SD_OC_CLR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) u8 val = SD_OCP_INT_CLR | SD_OC_CLR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) rtsx_pci_write_register(pcr, REG_OCPCTL, mask, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) udelay(100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) rtsx_pci_write_register(pcr, REG_OCPCTL, mask, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) void rtsx_pci_enable_oobs_polling(struct rtsx_pcr *pcr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) u16 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) if ((PCI_PID(pcr) != PID_525A) && (PCI_PID(pcr) != PID_5260)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) rtsx_pci_read_phy_register(pcr, 0x01, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) val |= 1<<9;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) rtsx_pci_write_phy_register(pcr, 0x01, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) rtsx_pci_write_register(pcr, REG_CFG_OOBS_OFF_TIMER, 0xFF, 0x32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) rtsx_pci_write_register(pcr, REG_CFG_OOBS_ON_TIMER, 0xFF, 0x05);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) rtsx_pci_write_register(pcr, REG_CFG_VCM_ON_TIMER, 0xFF, 0x83);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) rtsx_pci_write_register(pcr, REG_CFG_OOBS_POLLING, 0xFF, 0xDE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) void rtsx_pci_disable_oobs_polling(struct rtsx_pcr *pcr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) u16 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) if ((PCI_PID(pcr) != PID_525A) && (PCI_PID(pcr) != PID_5260)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) rtsx_pci_read_phy_register(pcr, 0x01, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) val &= ~(1<<9);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) rtsx_pci_write_phy_register(pcr, 0x01, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) rtsx_pci_write_register(pcr, REG_CFG_VCM_ON_TIMER, 0xFF, 0x03);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) rtsx_pci_write_register(pcr, REG_CFG_OOBS_POLLING, 0xFF, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) int rtsx_sd_power_off_card3v3(struct rtsx_pcr *pcr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) rtsx_pci_write_register(pcr, CARD_CLK_EN, SD_CLK_EN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) MS_CLK_EN | SD40_CLK_EN, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) rtsx_pci_write_register(pcr, CARD_OE, SD_OUTPUT_EN, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) rtsx_pci_card_power_off(pcr, RTSX_SD_CARD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) msleep(50);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) rtsx_pci_card_pull_ctl_disable(pcr, RTSX_SD_CARD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) int rtsx_ms_power_off_card3v3(struct rtsx_pcr *pcr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) rtsx_pci_write_register(pcr, CARD_CLK_EN, SD_CLK_EN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) MS_CLK_EN | SD40_CLK_EN, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) rtsx_pci_card_pull_ctl_disable(pcr, RTSX_MS_CARD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) rtsx_pci_write_register(pcr, CARD_OE, MS_OUTPUT_EN, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) rtsx_pci_card_power_off(pcr, RTSX_MS_CARD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) static int rtsx_pci_init_hw(struct rtsx_pcr *pcr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) struct pci_dev *pdev = pcr->pci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) if (PCI_PID(pcr) == PID_5228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) rtsx_pci_write_register(pcr, RTS5228_LDO1_CFG1, RTS5228_LDO1_SR_TIME_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) RTS5228_LDO1_SR_0_5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) rtsx_pci_writel(pcr, RTSX_HCBAR, pcr->host_cmds_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) rtsx_pci_enable_bus_int(pcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) /* Power on SSC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) if (PCI_PID(pcr) == PID_5261) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) /* Gating real mcu clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) err = rtsx_pci_write_register(pcr, RTS5261_FW_CFG1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) RTS5261_MCU_CLOCK_GATING, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) err = rtsx_pci_write_register(pcr, RTS5261_REG_FPDCTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) SSC_POWER_DOWN, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) err = rtsx_pci_write_register(pcr, FPDCTL, SSC_POWER_DOWN, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) /* Wait SSC power stable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) udelay(200);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) rtsx_pci_disable_aspm(pcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) if (pcr->ops->optimize_phy) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) err = pcr->ops->optimize_phy(pcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) rtsx_pci_init_cmd(pcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) /* Set mcu_cnt to 7 to ensure data can be sampled properly */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_DIV, 0x07, 0x07);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, HOST_SLEEP_STATE, 0x03, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) /* Disable card clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_EN, 0x1E, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) /* Reset delink mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CHANGE_LINK_STATE, 0x0A, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) /* Card driving select */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_DRIVE_SEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) 0xFF, pcr->card_drive_sel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) /* Enable SSC Clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) 0xFF, SSC_8X_EN | SSC_SEL_4M);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) if (PCI_PID(pcr) == PID_5261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL2, 0xFF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) RTS5261_SSC_DEPTH_2M);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) else if (PCI_PID(pcr) == PID_5228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL2, 0xFF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) RTS5228_SSC_DEPTH_2M);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL2, 0xFF, 0x12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) /* Disable cd_pwr_save */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CHANGE_LINK_STATE, 0x16, 0x10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) /* Clear Link Ready Interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, IRQSTAT0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) LINK_RDY_INT, LINK_RDY_INT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) /* Enlarge the estimation window of PERST# glitch
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) * to reduce the chance of invalid card interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PERST_GLITCH_WIDTH, 0xFF, 0x80);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) /* Update RC oscillator to 400k
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) * bit[0] F_HIGH: for RC oscillator, Rst_value is 1'b1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) * 1: 2M 0: 400k
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, RCCTL, 0x01, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) /* Set interrupt write clear
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) * bit 1: U_elbi_if_rd_clr_en
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) * 1: Enable ELBI interrupt[31:22] & [7:0] flag read clear
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) * 0: ELBI interrupt flag[31:22] & [7:0] only can be write clear
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, NFTS_TX_CTRL, 0x02, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) err = rtsx_pci_send_cmd(pcr, 100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) switch (PCI_PID(pcr)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) case PID_5250:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) case PID_524A:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) case PID_525A:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) case PID_5260:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) case PID_5261:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) case PID_5228:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) rtsx_pci_write_register(pcr, PM_CLK_FORCE_CTL, 1, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) /*init ocp*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) rtsx_pci_init_ocp(pcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) /* Enable clk_request_n to enable clock power management */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) pcie_capability_write_word(pdev, PCI_EXP_LNKCTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) PCI_EXP_LNKCTL_CLKREQ_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) /* Enter L1 when host tx idle */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) pci_write_config_byte(pdev, 0x70F, 0x5B);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) if (pcr->ops->extra_init_hw) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) err = pcr->ops->extra_init_hw(pcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) /* No CD interrupt if probing driver with card inserted.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) * So we need to initialize pcr->card_exist here.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) if (pcr->ops->cd_deglitch)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) pcr->card_exist = pcr->ops->cd_deglitch(pcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) pcr->card_exist = rtsx_pci_readl(pcr, RTSX_BIPR) & CARD_EXIST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) static int rtsx_pci_init_chip(struct rtsx_pcr *pcr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) spin_lock_init(&pcr->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) mutex_init(&pcr->pcr_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) switch (PCI_PID(pcr)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) case 0x5209:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) rts5209_init_params(pcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) case 0x5229:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) rts5229_init_params(pcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) case 0x5289:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) rtl8411_init_params(pcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) case 0x5227:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) rts5227_init_params(pcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) case 0x522A:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) rts522a_init_params(pcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) case 0x5249:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) rts5249_init_params(pcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) case 0x524A:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) rts524a_init_params(pcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) case 0x525A:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) rts525a_init_params(pcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) case 0x5287:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) rtl8411b_init_params(pcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) case 0x5286:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) rtl8402_init_params(pcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) case 0x5260:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) rts5260_init_params(pcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) case 0x5261:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) rts5261_init_params(pcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) case 0x5228:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) rts5228_init_params(pcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) pcr_dbg(pcr, "PID: 0x%04x, IC version: 0x%02x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) PCI_PID(pcr), pcr->ic_version);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) pcr->slots = kcalloc(pcr->num_slots, sizeof(struct rtsx_slot),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) if (!pcr->slots)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) if (pcr->ops->fetch_vendor_settings)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) pcr->ops->fetch_vendor_settings(pcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) pcr_dbg(pcr, "pcr->aspm_en = 0x%x\n", pcr->aspm_en);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) pcr_dbg(pcr, "pcr->sd30_drive_sel_1v8 = 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) pcr->sd30_drive_sel_1v8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) pcr_dbg(pcr, "pcr->sd30_drive_sel_3v3 = 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) pcr->sd30_drive_sel_3v3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) pcr_dbg(pcr, "pcr->card_drive_sel = 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) pcr->card_drive_sel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) pcr_dbg(pcr, "pcr->flags = 0x%x\n", pcr->flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) pcr->state = PDEV_STAT_IDLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) err = rtsx_pci_init_hw(pcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) kfree(pcr->slots);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) static int rtsx_pci_probe(struct pci_dev *pcidev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) const struct pci_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) struct rtsx_pcr *pcr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) struct pcr_handle *handle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) u32 base, len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) int ret, i, bar = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) dev_dbg(&(pcidev->dev),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) ": Realtek PCI-E Card Reader found at %s [%04x:%04x] (rev %x)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) pci_name(pcidev), (int)pcidev->vendor, (int)pcidev->device,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) (int)pcidev->revision);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) ret = pci_set_dma_mask(pcidev, DMA_BIT_MASK(32));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) ret = pci_enable_device(pcidev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) ret = pci_request_regions(pcidev, DRV_NAME_RTSX_PCI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) goto disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) pcr = kzalloc(sizeof(*pcr), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) if (!pcr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) goto release_pci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) handle = kzalloc(sizeof(*handle), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) if (!handle) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) goto free_pcr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) handle->pcr = pcr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) idr_preload(GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) spin_lock(&rtsx_pci_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) ret = idr_alloc(&rtsx_pci_idr, pcr, 0, 0, GFP_NOWAIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) if (ret >= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) pcr->id = ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) spin_unlock(&rtsx_pci_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) idr_preload_end();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) goto free_handle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) pcr->pci = pcidev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) dev_set_drvdata(&pcidev->dev, handle);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) if (CHK_PCI_PID(pcr, 0x525A))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) bar = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) len = pci_resource_len(pcidev, bar);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) base = pci_resource_start(pcidev, bar);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) pcr->remap_addr = ioremap(base, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) if (!pcr->remap_addr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) goto free_handle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) pcr->rtsx_resv_buf = dma_alloc_coherent(&(pcidev->dev),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) RTSX_RESV_BUF_LEN, &(pcr->rtsx_resv_buf_addr),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) if (pcr->rtsx_resv_buf == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) ret = -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) goto unmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) pcr->host_cmds_ptr = pcr->rtsx_resv_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) pcr->host_cmds_addr = pcr->rtsx_resv_buf_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) pcr->host_sg_tbl_ptr = pcr->rtsx_resv_buf + HOST_CMDS_BUF_LEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) pcr->host_sg_tbl_addr = pcr->rtsx_resv_buf_addr + HOST_CMDS_BUF_LEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) pcr->card_inserted = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) pcr->card_removed = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549) INIT_DELAYED_WORK(&pcr->carddet_work, rtsx_pci_card_detect);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) INIT_DELAYED_WORK(&pcr->idle_work, rtsx_pci_idle_work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) pcr->msi_en = msi_en;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) if (pcr->msi_en) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) ret = pci_enable_msi(pcidev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) pcr->msi_en = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) ret = rtsx_pci_acquire_irq(pcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) goto disable_msi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) pci_set_master(pcidev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) synchronize_irq(pcr->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) ret = rtsx_pci_init_chip(pcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) goto disable_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) for (i = 0; i < ARRAY_SIZE(rtsx_pcr_cells); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) rtsx_pcr_cells[i].platform_data = handle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) rtsx_pcr_cells[i].pdata_size = sizeof(*handle);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574) ret = mfd_add_devices(&pcidev->dev, pcr->id, rtsx_pcr_cells,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) ARRAY_SIZE(rtsx_pcr_cells), NULL, 0, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) goto free_slots;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) schedule_delayed_work(&pcr->idle_work, msecs_to_jiffies(200));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) free_slots:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584) kfree(pcr->slots);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585) disable_irq:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) free_irq(pcr->irq, (void *)pcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) disable_msi:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) if (pcr->msi_en)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589) pci_disable_msi(pcr->pci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590) dma_free_coherent(&(pcr->pci->dev), RTSX_RESV_BUF_LEN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591) pcr->rtsx_resv_buf, pcr->rtsx_resv_buf_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) unmap:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593) iounmap(pcr->remap_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594) free_handle:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595) kfree(handle);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596) free_pcr:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597) kfree(pcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598) release_pci:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599) pci_release_regions(pcidev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) disable:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601) pci_disable_device(pcidev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606) static void rtsx_pci_remove(struct pci_dev *pcidev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608) struct pcr_handle *handle = pci_get_drvdata(pcidev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609) struct rtsx_pcr *pcr = handle->pcr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) pcr->remove_pci = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613) /* Disable interrupts at the pcr level */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614) spin_lock_irq(&pcr->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615) rtsx_pci_writel(pcr, RTSX_BIER, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616) pcr->bier = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617) spin_unlock_irq(&pcr->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619) cancel_delayed_work_sync(&pcr->carddet_work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620) cancel_delayed_work_sync(&pcr->idle_work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622) mfd_remove_devices(&pcidev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) dma_free_coherent(&(pcr->pci->dev), RTSX_RESV_BUF_LEN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625) pcr->rtsx_resv_buf, pcr->rtsx_resv_buf_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626) free_irq(pcr->irq, (void *)pcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627) if (pcr->msi_en)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628) pci_disable_msi(pcr->pci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629) iounmap(pcr->remap_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631) pci_release_regions(pcidev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632) pci_disable_device(pcidev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634) spin_lock(&rtsx_pci_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635) idr_remove(&rtsx_pci_idr, pcr->id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636) spin_unlock(&rtsx_pci_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638) kfree(pcr->slots);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639) kfree(pcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640) kfree(handle);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642) dev_dbg(&(pcidev->dev),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643) ": Realtek PCI-E Card Reader at %s [%04x:%04x] has been removed\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644) pci_name(pcidev), (int)pcidev->vendor, (int)pcidev->device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647) static int __maybe_unused rtsx_pci_suspend(struct device *dev_d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649) struct pci_dev *pcidev = to_pci_dev(dev_d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650) struct pcr_handle *handle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651) struct rtsx_pcr *pcr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653) dev_dbg(&(pcidev->dev), "--> %s\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655) handle = pci_get_drvdata(pcidev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656) pcr = handle->pcr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658) cancel_delayed_work(&pcr->carddet_work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659) cancel_delayed_work(&pcr->idle_work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661) mutex_lock(&pcr->pcr_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663) rtsx_pci_power_off(pcr, HOST_ENTER_S3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665) device_wakeup_disable(dev_d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667) mutex_unlock(&pcr->pcr_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671) static int __maybe_unused rtsx_pci_resume(struct device *dev_d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673) struct pci_dev *pcidev = to_pci_dev(dev_d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674) struct pcr_handle *handle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675) struct rtsx_pcr *pcr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678) dev_dbg(&(pcidev->dev), "--> %s\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680) handle = pci_get_drvdata(pcidev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681) pcr = handle->pcr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683) mutex_lock(&pcr->pcr_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685) ret = rtsx_pci_write_register(pcr, HOST_SLEEP_STATE, 0x03, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689) ret = rtsx_pci_init_hw(pcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693) schedule_delayed_work(&pcr->idle_work, msecs_to_jiffies(200));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696) mutex_unlock(&pcr->pcr_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700) #ifdef CONFIG_PM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702) static void rtsx_pci_shutdown(struct pci_dev *pcidev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704) struct pcr_handle *handle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705) struct rtsx_pcr *pcr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1707) dev_dbg(&(pcidev->dev), "--> %s\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1708)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1709) handle = pci_get_drvdata(pcidev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1710) pcr = handle->pcr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1711) rtsx_pci_power_off(pcr, HOST_ENTER_S1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1712)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1713) pci_disable_device(pcidev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1714) free_irq(pcr->irq, (void *)pcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1715) if (pcr->msi_en)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1716) pci_disable_msi(pcr->pci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1717) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1718)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1719) #else /* CONFIG_PM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1720)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1721) #define rtsx_pci_shutdown NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1722)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1723) #endif /* CONFIG_PM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1724)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1725) static SIMPLE_DEV_PM_OPS(rtsx_pci_pm_ops, rtsx_pci_suspend, rtsx_pci_resume);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1726)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1727) static struct pci_driver rtsx_pci_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1728) .name = DRV_NAME_RTSX_PCI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1729) .id_table = rtsx_pci_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1730) .probe = rtsx_pci_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1731) .remove = rtsx_pci_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1732) .driver.pm = &rtsx_pci_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1733) .shutdown = rtsx_pci_shutdown,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1734) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1735) module_pci_driver(rtsx_pci_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1736)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1737) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1738) MODULE_AUTHOR("Wei WANG <wei_wang@realsil.com.cn>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1739) MODULE_DESCRIPTION("Realtek PCI-E Card Reader Driver");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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