Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /* Driver for Realtek PCI-Express card reader
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  * Copyright(c) 2018-2019 Realtek Semiconductor Corp. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  * Author:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  *   Rui FENG <rui_feng@realsil.com.cn>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  *   Wei WANG <wei_wang@realsil.com.cn>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #ifndef RTS5261_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #define RTS5261_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) /*New add*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #define rts5261_vendor_setting_valid(reg)	((reg) & 0x010000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #define rts5261_reg_to_aspm(reg)		(((reg) >> 28) ^ 0x03)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #define rts5261_reg_check_reverse_socket(reg)	((reg) & 0x04)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #define rts5261_reg_to_card_drive_sel(reg)	((((reg) >> 6) & 0x01) << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #define rts5261_reg_to_sd30_drive_sel_1v8(reg)	(((reg) >> 22) ^ 0x03)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #define rts5261_reg_to_sd30_drive_sel_3v3(reg)	(((reg) >> 16) ^ 0x03)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #define RTS5261_AUTOLOAD_CFG0		0xFF7B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #define RTS5261_AUTOLOAD_CFG1		0xFF7C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #define RTS5261_AUTOLOAD_CFG2		0xFF7D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #define RTS5261_AUTOLOAD_CFG3		0xFF7E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define RTS5261_AUTOLOAD_CFG4		0xFF7F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #define RTS5261_FORCE_PRSNT_LOW		(1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define RTS5261_AUX_CLK_16M_EN		(1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define RTS5261_REG_VREF		0xFE97
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define RTS5261_PWD_SUSPND_EN		(1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define RTS5261_PAD_H3L1		0xFF79
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define PAD_GPIO_H3L1			(1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) /* SSC_CTL2 0xFC12 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define RTS5261_SSC_DEPTH_MASK		0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define RTS5261_SSC_DEPTH_DISALBE	0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #define RTS5261_SSC_DEPTH_8M		0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #define RTS5261_SSC_DEPTH_4M		0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #define RTS5261_SSC_DEPTH_2M		0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #define RTS5261_SSC_DEPTH_1M		0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #define RTS5261_SSC_DEPTH_512K		0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #define RTS5261_SSC_DEPTH_256K		0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) #define RTS5261_SSC_DEPTH_128K		0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) /* efuse control register*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) #define RTS5261_EFUSE_CTL		0xFC30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) #define RTS5261_EFUSE_ENABLE		0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) /* EFUSE_MODE: 0=READ 1=PROGRAM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) #define RTS5261_EFUSE_MODE_MASK		0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) #define RTS5261_EFUSE_PROGRAM		0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) #define RTS5261_EFUSE_ADDR		0xFC31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) #define	RTS5261_EFUSE_ADDR_MASK		0x3F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) #define RTS5261_EFUSE_WRITE_DATA	0xFC32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) #define RTS5261_EFUSE_READ_DATA		0xFC34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) /* DMACTL 0xFE2C */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) #define RTS5261_DMA_PACK_SIZE_MASK	0xF0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) /* FW config info register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) #define RTS5261_FW_CFG_INFO0		0xFF50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) #define RTS5261_FW_EXPRESS_TEST_MASK	(0x01<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) #define RTS5261_FW_EA_MODE_MASK		(0x01<<5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) /* FW config register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) #define RTS5261_FW_CFG0			0xFF54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) #define RTS5261_FW_ENTER_EXPRESS	(0x01<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) #define RTS5261_FW_CFG1			0xFF55
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) #define RTS5261_SYS_CLK_SEL_MCU_CLK	(0x01<<7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) #define RTS5261_CRC_CLK_SEL_MCU_CLK	(0x01<<6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) #define RTS5261_FAKE_MCU_CLOCK_GATING	(0x01<<5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) /*MCU_bus_mode_sel: 0=real 8051 1=fake mcu*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) #define RTS5261_MCU_BUS_SEL_MASK	(0x01<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) /*MCU_clock_sel:VerA 00=aux16M 01=aux400K 1x=REFCLK100M*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) /*MCU_clock_sel:VerB 00=aux400K 01=aux16M 10=REFCLK100M*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) #define RTS5261_MCU_CLOCK_SEL_MASK	(0x03<<2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) #define RTS5261_MCU_CLOCK_SEL_16M	(0x01<<2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) #define RTS5261_MCU_CLOCK_GATING	(0x01<<1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) #define RTS5261_DRIVER_ENABLE_FW	(0x01<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) /* FW status register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) #define RTS5261_FW_STATUS		0xFF56
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) #define RTS5261_EXPRESS_LINK_FAIL_MASK	(0x01<<7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) /* FW control register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) #define RTS5261_FW_CTL			0xFF5F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) #define RTS5261_INFORM_RTD3_COLD	(0x01<<5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) #define RTS5261_REG_FPDCTL		0xFF60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) #define RTS5261_REG_LDO12_CFG		0xFF6E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) #define RTS5261_LDO12_VO_TUNE_MASK	(0x07<<1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) #define RTS5261_LDO12_115		(0x03<<1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) #define RTS5261_LDO12_120		(0x04<<1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) #define RTS5261_LDO12_125		(0x05<<1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define RTS5261_LDO12_130		(0x06<<1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define RTS5261_LDO12_135		(0x07<<1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) /* LDO control register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define RTS5261_CARD_PWR_CTL		0xFD50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define RTS5261_SD_CLK_ISO		(0x01<<7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define RTS5261_PAD_SD_DAT_FW_CTRL	(0x01<<6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define RTS5261_PUPDC			(0x01<<5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define RTS5261_SD_CMD_ISO		(0x01<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define RTS5261_SD_DAT_ISO_MASK		(0x0F<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define RTS5261_LDO1233318_POW_CTL	0xFF70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define RTS5261_LDO3318_POWERON		(0x01<<3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define RTS5261_LDO3_POWERON		(0x01<<2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define RTS5261_LDO2_POWERON		(0x01<<1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define RTS5261_LDO1_POWERON		(0x01<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define RTS5261_LDO_POWERON_MASK	(0x0F<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define RTS5261_DV3318_CFG		0xFF71
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define RTS5261_DV3318_TUNE_MASK	(0x07<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define RTS5261_DV3318_18		(0x02<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define RTS5261_DV3318_19		(0x04<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define RTS5261_DV3318_33		(0x07<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define RTS5261_LDO1_CFG0		0xFF72
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define RTS5261_LDO1_OCP_THD_MASK	(0x07<<5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define RTS5261_LDO1_OCP_EN		(0x01<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define RTS5261_LDO1_OCP_LMT_THD_MASK	(0x03<<2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define RTS5261_LDO1_OCP_LMT_EN		(0x01<<1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) /* CRD6603-433 190319 request changed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define RTS5261_LDO1_OCP_THD_740	(0x00<<5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define RTS5261_LDO1_OCP_THD_800	(0x01<<5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define RTS5261_LDO1_OCP_THD_860	(0x02<<5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define RTS5261_LDO1_OCP_THD_920	(0x03<<5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define RTS5261_LDO1_OCP_THD_980	(0x04<<5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define RTS5261_LDO1_OCP_THD_1040	(0x05<<5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define RTS5261_LDO1_OCP_THD_1100	(0x06<<5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define RTS5261_LDO1_OCP_THD_1160	(0x07<<5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define RTS5261_LDO1_LMT_THD_450	(0x00<<2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define RTS5261_LDO1_LMT_THD_1000	(0x01<<2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define RTS5261_LDO1_LMT_THD_1500	(0x02<<2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define RTS5261_LDO1_LMT_THD_2000	(0x03<<2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define RTS5261_LDO1_CFG1		0xFF73
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define RTS5261_LDO1_TUNE_MASK		(0x07<<1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define RTS5261_LDO1_18			(0x05<<1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define RTS5261_LDO1_33			(0x07<<1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define RTS5261_LDO1_PWD_MASK		(0x01<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define RTS5261_LDO2_CFG0		0xFF74
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define RTS5261_LDO2_OCP_THD_MASK	(0x07<<5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define RTS5261_LDO2_OCP_EN		(0x01<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define RTS5261_LDO2_OCP_LMT_THD_MASK	(0x03<<2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define RTS5261_LDO2_OCP_LMT_EN		(0x01<<1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define RTS5261_LDO2_OCP_THD_620	(0x00<<5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define RTS5261_LDO2_OCP_THD_650	(0x01<<5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define RTS5261_LDO2_OCP_THD_680	(0x02<<5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define RTS5261_LDO2_OCP_THD_720	(0x03<<5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define RTS5261_LDO2_OCP_THD_750	(0x04<<5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define RTS5261_LDO2_OCP_THD_780	(0x05<<5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define RTS5261_LDO2_OCP_THD_810	(0x06<<5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define RTS5261_LDO2_OCP_THD_840	(0x07<<5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define RTS5261_LDO2_CFG1		0xFF75
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define RTS5261_LDO2_TUNE_MASK		(0x07<<1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define RTS5261_LDO2_18			(0x05<<1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define RTS5261_LDO2_33			(0x07<<1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define RTS5261_LDO2_PWD_MASK		(0x01<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define RTS5261_LDO3_CFG0		0xFF76
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define RTS5261_LDO3_OCP_THD_MASK	(0x07<<5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define RTS5261_LDO3_OCP_EN		(0x01<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define RTS5261_LDO3_OCP_LMT_THD_MASK	(0x03<<2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define RTS5261_LDO3_OCP_LMT_EN		(0x01<<1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define RTS5261_LDO3_OCP_THD_620	(0x00<<5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define RTS5261_LDO3_OCP_THD_650	(0x01<<5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define RTS5261_LDO3_OCP_THD_680	(0x02<<5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define RTS5261_LDO3_OCP_THD_720	(0x03<<5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define RTS5261_LDO3_OCP_THD_750	(0x04<<5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define RTS5261_LDO3_OCP_THD_780	(0x05<<5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define RTS5261_LDO3_OCP_THD_810	(0x06<<5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define RTS5261_LDO3_OCP_THD_840	(0x07<<5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define RTS5261_LDO3_CFG1		0xFF77
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define RTS5261_LDO3_TUNE_MASK		(0x07<<1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define RTS5261_LDO3_18			(0x05<<1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define RTS5261_LDO3_33			(0x07<<1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define RTS5261_LDO3_PWD_MASK		(0x01<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define RTS5261_REG_PME_FORCE_CTL	0xFF78
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define FORCE_PM_CONTROL		0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define FORCE_PM_VALUE			0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define REG_EFUSE_BYPASS		0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define REG_EFUSE_POR			0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define REG_EFUSE_POWER_MASK		0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define REG_EFUSE_POWERON		0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define REG_EFUSE_POWEROFF		0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) /* Single LUN, support SD/SD EXPRESS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define DEFAULT_SINGLE		0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define SD_LUN			1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define SD_EXPRESS_LUN		2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) /* For Change_FPGA_SSCClock Function */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define MULTIPLY_BY_1    0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define MULTIPLY_BY_2    0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #define MULTIPLY_BY_3    0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #define MULTIPLY_BY_4    0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #define MULTIPLY_BY_5    0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #define MULTIPLY_BY_6    0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #define MULTIPLY_BY_7    0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define MULTIPLY_BY_8    0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #define MULTIPLY_BY_9    0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) #define MULTIPLY_BY_10   0x09
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define DIVIDE_BY_2      0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #define DIVIDE_BY_3      0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define DIVIDE_BY_4      0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) #define DIVIDE_BY_5      0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #define DIVIDE_BY_6      0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #define DIVIDE_BY_7      0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #define DIVIDE_BY_8      0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) #define DIVIDE_BY_9      0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) #define DIVIDE_BY_10     0x09
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) int rts5261_pci_switch_clock(struct rtsx_pcr *pcr, unsigned int card_clock,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 		u8 ssc_depth, bool initial_mode, bool double_clk, bool vpclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) #endif /* RTS5261_H */