^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /* Driver for Realtek PCI-Express card reader
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright(c) 2018-2019 Realtek Semiconductor Corp. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Author:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Rui FENG <rui_feng@realsil.com.cn>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Wei WANG <wei_wang@realsil.com.cn>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/rtsx_pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include "rts5261.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include "rtsx_pcr.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) static u8 rts5261_get_ic_version(struct rtsx_pcr *pcr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) rtsx_pci_read_register(pcr, DUMMY_REG_RESET_0, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) return val & IC_VERSION_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) static void rts5261_fill_driving(struct rtsx_pcr *pcr, u8 voltage)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) u8 driving_3v3[4][3] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) {0x13, 0x13, 0x13},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) {0x96, 0x96, 0x96},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) {0x7F, 0x7F, 0x7F},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) {0x96, 0x96, 0x96},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) u8 driving_1v8[4][3] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) {0x99, 0x99, 0x99},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) {0x3A, 0x3A, 0x3A},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) {0xE6, 0xE6, 0xE6},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) {0xB3, 0xB3, 0xB3},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) u8 (*driving)[3], drive_sel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) if (voltage == OUTPUT_3V3) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) driving = driving_3v3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) drive_sel = pcr->sd30_drive_sel_3v3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) driving = driving_1v8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) drive_sel = pcr->sd30_drive_sel_1v8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) rtsx_pci_write_register(pcr, SD30_CLK_DRIVE_SEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) 0xFF, driving[drive_sel][0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) rtsx_pci_write_register(pcr, SD30_CMD_DRIVE_SEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) 0xFF, driving[drive_sel][1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) rtsx_pci_write_register(pcr, SD30_DAT_DRIVE_SEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) 0xFF, driving[drive_sel][2]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) static void rtsx5261_fetch_vendor_settings(struct rtsx_pcr *pcr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) struct pci_dev *pdev = pcr->pci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) /* 0x814~0x817 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) pci_read_config_dword(pdev, PCR_SETTING_REG2, ®);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) pcr_dbg(pcr, "Cfg 0x%x: 0x%x\n", PCR_SETTING_REG2, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) if (!rts5261_vendor_setting_valid(reg)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) pcr_dbg(pcr, "skip fetch vendor setting\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) pcr->card_drive_sel &= 0x3F;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) pcr->card_drive_sel |= rts5261_reg_to_card_drive_sel(reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) if (rts5261_reg_check_reverse_socket(reg))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) pcr->flags |= PCR_REVERSE_SOCKET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) /* 0x724~0x727 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) pci_read_config_dword(pdev, PCR_SETTING_REG1, ®);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) pcr_dbg(pcr, "Cfg 0x%x: 0x%x\n", PCR_SETTING_REG1, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) pcr->aspm_en = rts5261_reg_to_aspm(reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) pcr->sd30_drive_sel_1v8 = rts5261_reg_to_sd30_drive_sel_1v8(reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) pcr->sd30_drive_sel_3v3 = rts5261_reg_to_sd30_drive_sel_3v3(reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) static void rts5261_force_power_down(struct rtsx_pcr *pcr, u8 pm_state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) /* Set relink_time to 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) rtsx_pci_write_register(pcr, AUTOLOAD_CFG_BASE + 1, MASK_8_BIT_DEF, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) rtsx_pci_write_register(pcr, AUTOLOAD_CFG_BASE + 2, MASK_8_BIT_DEF, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) rtsx_pci_write_register(pcr, AUTOLOAD_CFG_BASE + 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) RELINK_TIME_MASK, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) if (pm_state == HOST_ENTER_S3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) rtsx_pci_write_register(pcr, pcr->reg_pm_ctrl3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) D3_DELINK_MODE_EN, D3_DELINK_MODE_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) rtsx_pci_write_register(pcr, RTS5261_REG_FPDCTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) SSC_POWER_DOWN, SSC_POWER_DOWN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) static int rts5261_enable_auto_blink(struct rtsx_pcr *pcr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) return rtsx_pci_write_register(pcr, OLT_LED_CTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) LED_SHINE_MASK, LED_SHINE_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) static int rts5261_disable_auto_blink(struct rtsx_pcr *pcr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) return rtsx_pci_write_register(pcr, OLT_LED_CTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) LED_SHINE_MASK, LED_SHINE_DISABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) static int rts5261_turn_on_led(struct rtsx_pcr *pcr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) return rtsx_pci_write_register(pcr, GPIO_CTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 0x02, 0x02);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) static int rts5261_turn_off_led(struct rtsx_pcr *pcr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) return rtsx_pci_write_register(pcr, GPIO_CTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 0x02, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) /* SD Pull Control Enable:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) * SD_DAT[3:0] ==> pull up
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) * SD_CD ==> pull up
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) * SD_WP ==> pull up
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) * SD_CMD ==> pull up
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) * SD_CLK ==> pull down
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) static const u32 rts5261_sd_pull_ctl_enable_tbl[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) RTSX_REG_PAIR(CARD_PULL_CTL2, 0xAA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) RTSX_REG_PAIR(CARD_PULL_CTL3, 0xE9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) /* SD Pull Control Disable:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) * SD_DAT[3:0] ==> pull down
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) * SD_CD ==> pull up
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) * SD_WP ==> pull down
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) * SD_CMD ==> pull down
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) * SD_CLK ==> pull down
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) static const u32 rts5261_sd_pull_ctl_disable_tbl[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) RTSX_REG_PAIR(CARD_PULL_CTL2, 0x55),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) RTSX_REG_PAIR(CARD_PULL_CTL3, 0xD5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) static int rts5261_sd_set_sample_push_timing_sd30(struct rtsx_pcr *pcr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) rtsx_pci_write_register(pcr, SD_CFG1, SD_MODE_SELECT_MASK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) | SD_ASYNC_FIFO_NOT_RST, SD_30_MODE | SD_ASYNC_FIFO_NOT_RST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) rtsx_pci_write_register(pcr, CLK_CTL, CLK_LOW_FREQ, CLK_LOW_FREQ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) rtsx_pci_write_register(pcr, CARD_CLK_SOURCE, 0xFF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) CRC_VAR_CLK0 | SD30_FIX_CLK | SAMPLE_VAR_CLK1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) rtsx_pci_write_register(pcr, CLK_CTL, CLK_LOW_FREQ, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) static int rts5261_card_power_on(struct rtsx_pcr *pcr, int card)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) struct rtsx_cr_option *option = &pcr->option;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) if (option->ocp_en)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) rtsx_pci_enable_ocp(pcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) rtsx_pci_write_register(pcr, RTS5261_LDO1_CFG1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) RTS5261_LDO1_TUNE_MASK, RTS5261_LDO1_33);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) rtsx_pci_write_register(pcr, RTS5261_LDO1233318_POW_CTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) RTS5261_LDO1_POWERON, RTS5261_LDO1_POWERON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) rtsx_pci_write_register(pcr, RTS5261_LDO1233318_POW_CTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) RTS5261_LDO3318_POWERON, RTS5261_LDO3318_POWERON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) msleep(20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) rtsx_pci_write_register(pcr, CARD_OE, SD_OUTPUT_EN, SD_OUTPUT_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) /* Initialize SD_CFG1 register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) rtsx_pci_write_register(pcr, SD_CFG1, 0xFF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) SD_CLK_DIVIDE_128 | SD_20_MODE | SD_BUS_WIDTH_1BIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) rtsx_pci_write_register(pcr, SD_SAMPLE_POINT_CTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 0xFF, SD20_RX_POS_EDGE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) rtsx_pci_write_register(pcr, SD_PUSH_POINT_CTL, 0xFF, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) rtsx_pci_write_register(pcr, CARD_STOP, SD_STOP | SD_CLR_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) SD_STOP | SD_CLR_ERR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) /* Reset SD_CFG3 register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) rtsx_pci_write_register(pcr, SD_CFG3, SD30_CLK_END_EN, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) rtsx_pci_write_register(pcr, REG_SD_STOP_SDCLK_CFG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) SD30_CLK_STOP_CFG_EN | SD30_CLK_STOP_CFG1 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) SD30_CLK_STOP_CFG0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) if (pcr->extra_caps & EXTRA_CAPS_SD_SDR50 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) pcr->extra_caps & EXTRA_CAPS_SD_SDR104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) rts5261_sd_set_sample_push_timing_sd30(pcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) static int rts5261_switch_output_voltage(struct rtsx_pcr *pcr, u8 voltage)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) u16 val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) rtsx_pci_write_register(pcr, RTS5261_CARD_PWR_CTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) RTS5261_PUPDC, RTS5261_PUPDC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) switch (voltage) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) case OUTPUT_3V3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) rtsx_pci_read_phy_register(pcr, PHY_TUNE, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) val |= PHY_TUNE_SDBUS_33;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) err = rtsx_pci_write_phy_register(pcr, PHY_TUNE, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) rtsx_pci_write_register(pcr, RTS5261_DV3318_CFG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) RTS5261_DV3318_TUNE_MASK, RTS5261_DV3318_33);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) rtsx_pci_write_register(pcr, SD_PAD_CTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) SD_IO_USING_1V8, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) case OUTPUT_1V8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) rtsx_pci_read_phy_register(pcr, PHY_TUNE, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) val &= ~PHY_TUNE_SDBUS_33;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) err = rtsx_pci_write_phy_register(pcr, PHY_TUNE, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) rtsx_pci_write_register(pcr, RTS5261_DV3318_CFG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) RTS5261_DV3318_TUNE_MASK, RTS5261_DV3318_18);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) rtsx_pci_write_register(pcr, SD_PAD_CTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) SD_IO_USING_1V8, SD_IO_USING_1V8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) /* set pad drive */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) rts5261_fill_driving(pcr, voltage);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) static void rts5261_stop_cmd(struct rtsx_pcr *pcr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) rtsx_pci_writel(pcr, RTSX_HCBCTLR, STOP_CMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) rtsx_pci_writel(pcr, RTSX_HDBCTLR, STOP_DMA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) rtsx_pci_write_register(pcr, RTS5260_DMA_RST_CTL_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) RTS5260_DMA_RST | RTS5260_ADMA3_RST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) RTS5260_DMA_RST | RTS5260_ADMA3_RST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) rtsx_pci_write_register(pcr, RBCTL, RB_FLUSH, RB_FLUSH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) static void rts5261_card_before_power_off(struct rtsx_pcr *pcr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) rts5261_stop_cmd(pcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) rts5261_switch_output_voltage(pcr, OUTPUT_3V3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) static void rts5261_enable_ocp(struct rtsx_pcr *pcr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) u8 val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) val = SD_OCP_INT_EN | SD_DETECT_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) rtsx_pci_write_register(pcr, REG_OCPCTL, 0xFF, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) static void rts5261_disable_ocp(struct rtsx_pcr *pcr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) u8 mask = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) mask = SD_OCP_INT_EN | SD_DETECT_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) rtsx_pci_write_register(pcr, REG_OCPCTL, mask, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) rtsx_pci_write_register(pcr, RTS5261_LDO1_CFG0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) RTS5261_LDO1_OCP_EN | RTS5261_LDO1_OCP_LMT_EN, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) static int rts5261_card_power_off(struct rtsx_pcr *pcr, int card)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) int err = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) rts5261_card_before_power_off(pcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) err = rtsx_pci_write_register(pcr, RTS5261_LDO1233318_POW_CTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) RTS5261_LDO_POWERON_MASK, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) if (pcr->option.ocp_en)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) rtsx_pci_disable_ocp(pcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) static void rts5261_init_ocp(struct rtsx_pcr *pcr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) struct rtsx_cr_option *option = &pcr->option;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) if (option->ocp_en) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) u8 mask, val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) rtsx_pci_write_register(pcr, RTS5261_LDO1_CFG0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) RTS5261_LDO1_OCP_EN | RTS5261_LDO1_OCP_LMT_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) RTS5261_LDO1_OCP_EN | RTS5261_LDO1_OCP_LMT_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) rtsx_pci_write_register(pcr, RTS5261_LDO1_CFG0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) RTS5261_LDO1_OCP_THD_MASK, option->sd_800mA_ocp_thd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) rtsx_pci_write_register(pcr, RTS5261_LDO1_CFG0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) RTS5261_LDO1_OCP_LMT_THD_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) RTS5261_LDO1_LMT_THD_2000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) mask = SD_OCP_GLITCH_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) val = pcr->hw_param.ocp_glitch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) rtsx_pci_write_register(pcr, REG_OCPGLITCH, mask, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) rts5261_enable_ocp(pcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) rtsx_pci_write_register(pcr, RTS5261_LDO1_CFG0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) RTS5261_LDO1_OCP_EN | RTS5261_LDO1_OCP_LMT_EN, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) static void rts5261_clear_ocpstat(struct rtsx_pcr *pcr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) u8 mask = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) u8 val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) mask = SD_OCP_INT_CLR | SD_OC_CLR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) val = SD_OCP_INT_CLR | SD_OC_CLR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) rtsx_pci_write_register(pcr, REG_OCPCTL, mask, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) udelay(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) rtsx_pci_write_register(pcr, REG_OCPCTL, mask, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) static void rts5261_process_ocp(struct rtsx_pcr *pcr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) if (!pcr->option.ocp_en)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) rtsx_pci_get_ocpstat(pcr, &pcr->ocp_stat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) if (pcr->ocp_stat & (SD_OC_NOW | SD_OC_EVER)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) rts5261_card_power_off(pcr, RTSX_SD_CARD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) rtsx_pci_write_register(pcr, CARD_OE, SD_OUTPUT_EN, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) rts5261_clear_ocpstat(pcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) pcr->ocp_stat = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) static int rts5261_init_from_hw(struct rtsx_pcr *pcr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) struct pci_dev *pdev = pcr->pci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) int retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) u32 lval, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) u8 valid, efuse_valid, tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) rtsx_pci_write_register(pcr, RTS5261_REG_PME_FORCE_CTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) REG_EFUSE_POR | REG_EFUSE_POWER_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) REG_EFUSE_POR | REG_EFUSE_POWERON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) rtsx_pci_write_register(pcr, RTS5261_EFUSE_ADDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) RTS5261_EFUSE_ADDR_MASK, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) rtsx_pci_write_register(pcr, RTS5261_EFUSE_CTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) RTS5261_EFUSE_ENABLE | RTS5261_EFUSE_MODE_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) RTS5261_EFUSE_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) /* Wait transfer end */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) for (i = 0; i < MAX_RW_REG_CNT; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) rtsx_pci_read_register(pcr, RTS5261_EFUSE_CTL, &tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) if ((tmp & 0x80) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) rtsx_pci_read_register(pcr, RTS5261_EFUSE_READ_DATA, &tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) efuse_valid = ((tmp & 0x0C) >> 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) pcr_dbg(pcr, "Load efuse valid: 0x%x\n", efuse_valid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) if (efuse_valid == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) retval = pci_read_config_dword(pdev, PCR_SETTING_REG2, &lval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) if (retval != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) pcr_dbg(pcr, "read 0x814 DW fail\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) pcr_dbg(pcr, "DW from 0x814: 0x%x\n", lval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) /* 0x816 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) valid = (u8)((lval >> 16) & 0x03);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) pcr_dbg(pcr, "0x816: %d\n", valid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) rtsx_pci_write_register(pcr, RTS5261_REG_PME_FORCE_CTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) REG_EFUSE_POR, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) pcr_dbg(pcr, "Disable efuse por!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) pci_read_config_dword(pdev, PCR_SETTING_REG2, &lval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) lval = lval & 0x00FFFFFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) retval = pci_write_config_dword(pdev, PCR_SETTING_REG2, lval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) if (retval != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) pcr_dbg(pcr, "write config fail\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) return retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) static void rts5261_init_from_cfg(struct rtsx_pcr *pcr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) struct pci_dev *pdev = pcr->pci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) int l1ss;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) u32 lval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) struct rtsx_cr_option *option = &pcr->option;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) l1ss = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_L1SS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) if (!l1ss)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) pci_read_config_dword(pdev, l1ss + PCI_L1SS_CTL1, &lval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) if (lval & PCI_L1SS_CTL1_ASPM_L1_1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) rtsx_set_dev_flag(pcr, ASPM_L1_1_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) rtsx_clear_dev_flag(pcr, ASPM_L1_1_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) if (lval & PCI_L1SS_CTL1_ASPM_L1_2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) rtsx_set_dev_flag(pcr, ASPM_L1_2_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) rtsx_clear_dev_flag(pcr, ASPM_L1_2_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) if (lval & PCI_L1SS_CTL1_PCIPM_L1_1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) rtsx_set_dev_flag(pcr, PM_L1_1_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) rtsx_clear_dev_flag(pcr, PM_L1_1_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) if (lval & PCI_L1SS_CTL1_PCIPM_L1_2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) rtsx_set_dev_flag(pcr, PM_L1_2_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) rtsx_clear_dev_flag(pcr, PM_L1_2_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) rtsx_pci_write_register(pcr, ASPM_FORCE_CTL, 0xFF, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) if (option->ltr_en) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) u16 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) pcie_capability_read_word(pdev, PCI_EXP_DEVCTL2, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) if (val & PCI_EXP_DEVCTL2_LTR_EN) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) option->ltr_enabled = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) option->ltr_active = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) rtsx_set_ltr_latency(pcr, option->ltr_active_latency);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) option->ltr_enabled = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) if (rtsx_check_dev_flag(pcr, ASPM_L1_1_EN | ASPM_L1_2_EN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) | PM_L1_1_EN | PM_L1_2_EN))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) option->force_clkreq_0 = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) option->force_clkreq_0 = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) static int rts5261_extra_init_hw(struct rtsx_pcr *pcr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) struct rtsx_cr_option *option = &pcr->option;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) rtsx_pci_write_register(pcr, RTS5261_AUTOLOAD_CFG1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) CD_RESUME_EN_MASK, CD_RESUME_EN_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) rts5261_init_from_cfg(pcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) rts5261_init_from_hw(pcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) /* power off efuse */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) rtsx_pci_write_register(pcr, RTS5261_REG_PME_FORCE_CTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) REG_EFUSE_POWER_MASK, REG_EFUSE_POWEROFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) rtsx_pci_write_register(pcr, L1SUB_CONFIG1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) AUX_CLK_ACTIVE_SEL_MASK, MAC_CKSW_DONE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) rtsx_pci_write_register(pcr, L1SUB_CONFIG3, 0xFF, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) rtsx_pci_write_register(pcr, RTS5261_AUTOLOAD_CFG4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) RTS5261_AUX_CLK_16M_EN, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) /* Release PRSNT# */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) rtsx_pci_write_register(pcr, RTS5261_AUTOLOAD_CFG4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) RTS5261_FORCE_PRSNT_LOW, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) rtsx_pci_write_register(pcr, FUNC_FORCE_CTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) FUNC_FORCE_UPME_XMT_DBG, FUNC_FORCE_UPME_XMT_DBG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) rtsx_pci_write_register(pcr, PCLK_CTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) PCLK_MODE_SEL, PCLK_MODE_SEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) rtsx_pci_write_register(pcr, PM_EVENT_DEBUG, PME_DEBUG_0, PME_DEBUG_0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) rtsx_pci_write_register(pcr, PM_CLK_FORCE_CTL, CLK_PM_EN, CLK_PM_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) /* LED shine disabled, set initial shine cycle period */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) rtsx_pci_write_register(pcr, OLT_LED_CTL, 0x0F, 0x02);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) /* Configure driving */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) rts5261_fill_driving(pcr, OUTPUT_3V3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) * If u_force_clkreq_0 is enabled, CLKREQ# PIN will be forced
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) * to drive low, and we forcibly request clock.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) if (option->force_clkreq_0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) rtsx_pci_write_register(pcr, PETXCFG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) FORCE_CLKREQ_DELINK_MASK, FORCE_CLKREQ_LOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) rtsx_pci_write_register(pcr, PETXCFG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) FORCE_CLKREQ_DELINK_MASK, FORCE_CLKREQ_HIGH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) rtsx_pci_write_register(pcr, pcr->reg_pm_ctrl3, 0x10, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) rtsx_pci_write_register(pcr, RTS5261_REG_PME_FORCE_CTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) FORCE_PM_CONTROL | FORCE_PM_VALUE, FORCE_PM_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) /* Clear Enter RTD3_cold Information*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) rtsx_pci_write_register(pcr, RTS5261_FW_CTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) RTS5261_INFORM_RTD3_COLD, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) static void rts5261_enable_aspm(struct rtsx_pcr *pcr, bool enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) if (pcr->aspm_enabled == enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) pcie_capability_clear_and_set_word(pcr->pci, PCI_EXP_LNKCTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) PCI_EXP_LNKCTL_ASPMC, pcr->aspm_en);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) pcr->aspm_enabled = enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) static void rts5261_disable_aspm(struct rtsx_pcr *pcr, bool enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) if (pcr->aspm_enabled == enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) pcie_capability_clear_and_set_word(pcr->pci, PCI_EXP_LNKCTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) PCI_EXP_LNKCTL_ASPMC, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) rtsx_pci_write_register(pcr, SD_CFG1, SD_ASYNC_FIFO_NOT_RST, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) udelay(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) pcr->aspm_enabled = enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) static void rts5261_set_aspm(struct rtsx_pcr *pcr, bool enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) if (enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) rts5261_enable_aspm(pcr, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) rts5261_disable_aspm(pcr, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) static void rts5261_set_l1off_cfg_sub_d0(struct rtsx_pcr *pcr, int active)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) struct rtsx_cr_option *option = &pcr->option;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) int aspm_L1_1, aspm_L1_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) u8 val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) aspm_L1_1 = rtsx_check_dev_flag(pcr, ASPM_L1_1_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) aspm_L1_2 = rtsx_check_dev_flag(pcr, ASPM_L1_2_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) if (active) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) /* run, latency: 60us */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) if (aspm_L1_1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) val = option->ltr_l1off_snooze_sspwrgate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) /* l1off, latency: 300us */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) if (aspm_L1_2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) val = option->ltr_l1off_sspwrgate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) rtsx_set_l1off_sub(pcr, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) static const struct pcr_ops rts5261_pcr_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) .fetch_vendor_settings = rtsx5261_fetch_vendor_settings,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) .turn_on_led = rts5261_turn_on_led,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) .turn_off_led = rts5261_turn_off_led,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) .extra_init_hw = rts5261_extra_init_hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) .enable_auto_blink = rts5261_enable_auto_blink,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) .disable_auto_blink = rts5261_disable_auto_blink,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) .card_power_on = rts5261_card_power_on,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) .card_power_off = rts5261_card_power_off,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) .switch_output_voltage = rts5261_switch_output_voltage,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) .force_power_down = rts5261_force_power_down,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) .stop_cmd = rts5261_stop_cmd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) .set_aspm = rts5261_set_aspm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) .set_l1off_cfg_sub_d0 = rts5261_set_l1off_cfg_sub_d0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) .enable_ocp = rts5261_enable_ocp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) .disable_ocp = rts5261_disable_ocp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) .init_ocp = rts5261_init_ocp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) .process_ocp = rts5261_process_ocp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) .clear_ocpstat = rts5261_clear_ocpstat,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) static inline u8 double_ssc_depth(u8 depth)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) return ((depth > 1) ? (depth - 1) : depth);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) int rts5261_pci_switch_clock(struct rtsx_pcr *pcr, unsigned int card_clock,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) u8 ssc_depth, bool initial_mode, bool double_clk, bool vpclk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) int err, clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) u16 n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) u8 clk_divider, mcu_cnt, div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) static const u8 depth[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) [RTSX_SSC_DEPTH_4M] = RTS5261_SSC_DEPTH_4M,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) [RTSX_SSC_DEPTH_2M] = RTS5261_SSC_DEPTH_2M,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) [RTSX_SSC_DEPTH_1M] = RTS5261_SSC_DEPTH_1M,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) [RTSX_SSC_DEPTH_500K] = RTS5261_SSC_DEPTH_512K,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) if (initial_mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) /* We use 250k(around) here, in initial stage */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) if (is_version(pcr, PID_5261, IC_VER_D)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) clk_divider = SD_CLK_DIVIDE_256;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) card_clock = 60000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) clk_divider = SD_CLK_DIVIDE_128;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) card_clock = 30000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) clk_divider = SD_CLK_DIVIDE_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) err = rtsx_pci_write_register(pcr, SD_CFG1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) SD_CLK_DIVIDE_MASK, clk_divider);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) card_clock /= 1000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) pcr_dbg(pcr, "Switch card clock to %dMHz\n", card_clock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) clk = card_clock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) if (!initial_mode && double_clk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) clk = card_clock * 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) pcr_dbg(pcr, "Internal SSC clock: %dMHz (cur_clock = %d)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) clk, pcr->cur_clock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) if (clk == pcr->cur_clock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) if (pcr->ops->conv_clk_and_div_n)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) n = pcr->ops->conv_clk_and_div_n(clk, CLK_TO_DIV_N);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) n = clk - 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) if ((clk <= 4) || (n > 396))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) mcu_cnt = 125/clk + 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) if (mcu_cnt > 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) mcu_cnt = 15;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) div = CLK_DIV_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) while ((n < MIN_DIV_N_PCR - 4) && (div < CLK_DIV_8)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) if (pcr->ops->conv_clk_and_div_n) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) int dbl_clk = pcr->ops->conv_clk_and_div_n(n,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) DIV_N_TO_CLK) * 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) n = pcr->ops->conv_clk_and_div_n(dbl_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) CLK_TO_DIV_N);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) n = (n + 4) * 2 - 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) div++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) n = (n / 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) pcr_dbg(pcr, "n = %d, div = %d\n", n, div);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) ssc_depth = depth[ssc_depth];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) if (double_clk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) ssc_depth = double_ssc_depth(ssc_depth);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) if (ssc_depth) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) if (div == CLK_DIV_2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) if (ssc_depth > 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) ssc_depth -= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) ssc_depth = RTS5261_SSC_DEPTH_8M;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) } else if (div == CLK_DIV_4) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) if (ssc_depth > 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) ssc_depth -= 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) ssc_depth = RTS5261_SSC_DEPTH_8M;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) } else if (div == CLK_DIV_8) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) if (ssc_depth > 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) ssc_depth -= 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) ssc_depth = RTS5261_SSC_DEPTH_8M;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) ssc_depth = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) pcr_dbg(pcr, "ssc_depth = %d\n", ssc_depth);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) rtsx_pci_init_cmd(pcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) CLK_LOW_FREQ, CLK_LOW_FREQ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_DIV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) 0xFF, (div << 4) | mcu_cnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL1, SSC_RSTB, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) SSC_DEPTH_MASK, ssc_depth);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_DIV_N_0, 0xFF, n);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL1, SSC_RSTB, SSC_RSTB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) if (vpclk) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_VPCLK0_CTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) PHASE_NOT_RESET, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_VPCLK1_CTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) PHASE_NOT_RESET, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_VPCLK0_CTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) PHASE_NOT_RESET, PHASE_NOT_RESET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_VPCLK1_CTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) PHASE_NOT_RESET, PHASE_NOT_RESET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) err = rtsx_pci_send_cmd(pcr, 2000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) /* Wait SSC clock stable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) udelay(SSC_CLOCK_STABLE_WAIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) err = rtsx_pci_write_register(pcr, CLK_CTL, CLK_LOW_FREQ, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) pcr->cur_clock = clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) void rts5261_init_params(struct rtsx_pcr *pcr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) struct rtsx_cr_option *option = &pcr->option;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) struct rtsx_hw_param *hw_param = &pcr->hw_param;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) pcr->extra_caps = EXTRA_CAPS_SD_SDR50 | EXTRA_CAPS_SD_SDR104;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) pcr->num_slots = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) pcr->ops = &rts5261_pcr_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) pcr->flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) pcr->card_drive_sel = RTSX_CARD_DRIVE_DEFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) pcr->sd30_drive_sel_1v8 = CFG_DRIVER_TYPE_B;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) pcr->sd30_drive_sel_3v3 = CFG_DRIVER_TYPE_B;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) pcr->aspm_en = ASPM_L1_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) pcr->tx_initial_phase = SET_CLOCK_PHASE(27, 27, 11);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) pcr->rx_initial_phase = SET_CLOCK_PHASE(24, 6, 5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) pcr->ic_version = rts5261_get_ic_version(pcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) pcr->sd_pull_ctl_enable_tbl = rts5261_sd_pull_ctl_enable_tbl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) pcr->sd_pull_ctl_disable_tbl = rts5261_sd_pull_ctl_disable_tbl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) pcr->reg_pm_ctrl3 = RTS5261_AUTOLOAD_CFG3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) option->dev_flags = (LTR_L1SS_PWR_GATE_CHECK_CARD_EN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) | LTR_L1SS_PWR_GATE_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) option->ltr_en = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) /* init latency of active, idle, L1OFF to 60us, 300us, 3ms */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) option->ltr_active_latency = LTR_ACTIVE_LATENCY_DEF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) option->ltr_idle_latency = LTR_IDLE_LATENCY_DEF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) option->ltr_l1off_latency = LTR_L1OFF_LATENCY_DEF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) option->l1_snooze_delay = L1_SNOOZE_DELAY_DEF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) option->ltr_l1off_sspwrgate = 0x7F;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) option->ltr_l1off_snooze_sspwrgate = 0x78;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) option->ocp_en = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) hw_param->interrupt_en |= SD_OC_INT_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) hw_param->ocp_glitch = SD_OCP_GLITCH_800U;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) option->sd_800mA_ocp_thd = RTS5261_LDO1_OCP_THD_1040;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags