Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) #ifndef __RTS5260_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) #define __RTS5260_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4) #define RTS5260_DVCC_CTRL		0xFF73
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) #define RTS5260_DVCC_OCP_EN		(0x01 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) #define RTS5260_DVCC_OCP_THD_MASK	(0x07 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) #define RTS5260_DVCC_POWERON		(0x01 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) #define RTS5260_DVCC_OCP_CL_EN		(0x01 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define RTS5260_DVIO_CTRL		0xFF75
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define RTS5260_DVIO_OCP_EN		(0x01 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define RTS5260_DVIO_OCP_THD_MASK	(0x07 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define RTS5260_DVIO_POWERON		(0x01 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define RTS5260_DVIO_OCP_CL_EN		(0x01 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define RTS5260_DV331812_CFG		0xFF71
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define RTS5260_DV331812_OCP_EN		(0x01 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define RTS5260_DV331812_OCP_THD_MASK	(0x07 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define RTS5260_DV331812_POWERON	(0x01 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define RTS5260_DV331812_SEL		(0x01 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define RTS5260_DV331812_VDD1		(0x01 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define RTS5260_DV331812_VDD2		(0x00 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define RTS5260_DV331812_OCP_THD_120	(0x00 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define RTS5260_DV331812_OCP_THD_140	(0x01 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define RTS5260_DV331812_OCP_THD_160	(0x02 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define RTS5260_DV331812_OCP_THD_180	(0x03 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define RTS5260_DV331812_OCP_THD_210	(0x04 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define RTS5260_DV331812_OCP_THD_240	(0x05 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define RTS5260_DV331812_OCP_THD_270	(0x06 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define RTS5260_DV331812_OCP_THD_300	(0x07 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define RTS5260_DVIO_OCP_THD_250	(0x00 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define RTS5260_DVIO_OCP_THD_300	(0x01 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define RTS5260_DVIO_OCP_THD_350	(0x02 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define RTS5260_DVIO_OCP_THD_400	(0x03 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define RTS5260_DVIO_OCP_THD_450	(0x04 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define RTS5260_DVIO_OCP_THD_500	(0x05 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define RTS5260_DVIO_OCP_THD_550	(0x06 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define RTS5260_DVIO_OCP_THD_600	(0x07 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define RTS5260_DVCC_OCP_THD_550	(0x00 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define RTS5260_DVCC_OCP_THD_970	(0x05 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #endif