Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /* Driver for Realtek PCI-Express card reader
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  * Copyright(c) 2016-2017 Realtek Semiconductor Corp. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  * Author:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  *   Steven FENG <steven_feng@realsil.com.cn>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  *   Rui FENG <rui_feng@realsil.com.cn>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  *   Wei WANG <wei_wang@realsil.com.cn>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/rtsx_pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include "rts5260.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include "rtsx_pcr.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) static u8 rts5260_get_ic_version(struct rtsx_pcr *pcr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) 	u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) 	rtsx_pci_read_register(pcr, DUMMY_REG_RESET_0, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) 	return val & IC_VERSION_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) static void rts5260_fill_driving(struct rtsx_pcr *pcr, u8 voltage)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 	u8 driving_3v3[4][3] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 		{0x11, 0x11, 0x11},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 		{0x22, 0x22, 0x22},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 		{0x55, 0x55, 0x55},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 		{0x33, 0x33, 0x33},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 	u8 driving_1v8[4][3] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 		{0x35, 0x33, 0x33},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 		{0x8A, 0x88, 0x88},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 		{0xBD, 0xBB, 0xBB},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 		{0x9B, 0x99, 0x99},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 	u8 (*driving)[3], drive_sel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 	if (voltage == OUTPUT_3V3) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 		driving = driving_3v3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 		drive_sel = pcr->sd30_drive_sel_3v3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 		driving = driving_1v8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 		drive_sel = pcr->sd30_drive_sel_1v8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 	rtsx_pci_write_register(pcr, SD30_CLK_DRIVE_SEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 			 0xFF, driving[drive_sel][0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 	rtsx_pci_write_register(pcr, SD30_CMD_DRIVE_SEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 			 0xFF, driving[drive_sel][1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 	rtsx_pci_write_register(pcr, SD30_DAT_DRIVE_SEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 			 0xFF, driving[drive_sel][2]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) static void rtsx_base_fetch_vendor_settings(struct rtsx_pcr *pcr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 	struct pci_dev *pdev = pcr->pci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 	pci_read_config_dword(pdev, PCR_SETTING_REG1, &reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 	pcr_dbg(pcr, "Cfg 0x%x: 0x%x\n", PCR_SETTING_REG1, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	if (!rtsx_vendor_setting_valid(reg)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 		pcr_dbg(pcr, "skip fetch vendor setting\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	pcr->aspm_en = rtsx_reg_to_aspm(reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	pcr->sd30_drive_sel_1v8 = rtsx_reg_to_sd30_drive_sel_1v8(reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	pcr->card_drive_sel &= 0x3F;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	pcr->card_drive_sel |= rtsx_reg_to_card_drive_sel(reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	pci_read_config_dword(pdev, PCR_SETTING_REG2, &reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	pcr_dbg(pcr, "Cfg 0x%x: 0x%x\n", PCR_SETTING_REG2, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	if (rtsx_check_mmc_support(reg))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 		pcr->extra_caps |= EXTRA_CAPS_NO_MMC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	pcr->sd30_drive_sel_3v3 = rtsx_reg_to_sd30_drive_sel_3v3(reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	if (rtsx_reg_check_reverse_socket(reg))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 		pcr->flags |= PCR_REVERSE_SOCKET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) static int rtsx_base_enable_auto_blink(struct rtsx_pcr *pcr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	return rtsx_pci_write_register(pcr, OLT_LED_CTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 		LED_SHINE_MASK, LED_SHINE_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) static int rtsx_base_disable_auto_blink(struct rtsx_pcr *pcr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	return rtsx_pci_write_register(pcr, OLT_LED_CTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 		LED_SHINE_MASK, LED_SHINE_DISABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) static int rts5260_turn_on_led(struct rtsx_pcr *pcr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	return rtsx_pci_write_register(pcr, RTS5260_REG_GPIO_CTL0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 		RTS5260_REG_GPIO_MASK, RTS5260_REG_GPIO_ON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) static int rts5260_turn_off_led(struct rtsx_pcr *pcr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	return rtsx_pci_write_register(pcr, RTS5260_REG_GPIO_CTL0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 		RTS5260_REG_GPIO_MASK, RTS5260_REG_GPIO_OFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) /* SD Pull Control Enable:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)  *     SD_DAT[3:0] ==> pull up
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)  *     SD_CD       ==> pull up
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)  *     SD_WP       ==> pull up
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)  *     SD_CMD      ==> pull up
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)  *     SD_CLK      ==> pull down
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) static const u32 rts5260_sd_pull_ctl_enable_tbl[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	RTSX_REG_PAIR(CARD_PULL_CTL1, 0x66),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	RTSX_REG_PAIR(CARD_PULL_CTL2, 0xAA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	RTSX_REG_PAIR(CARD_PULL_CTL3, 0xE9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	RTSX_REG_PAIR(CARD_PULL_CTL4, 0xAA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) /* SD Pull Control Disable:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)  *     SD_DAT[3:0] ==> pull down
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)  *     SD_CD       ==> pull up
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)  *     SD_WP       ==> pull down
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)  *     SD_CMD      ==> pull down
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)  *     SD_CLK      ==> pull down
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) static const u32 rts5260_sd_pull_ctl_disable_tbl[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	RTSX_REG_PAIR(CARD_PULL_CTL1, 0x66),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	RTSX_REG_PAIR(CARD_PULL_CTL2, 0x55),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	RTSX_REG_PAIR(CARD_PULL_CTL3, 0xD5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	RTSX_REG_PAIR(CARD_PULL_CTL4, 0x55),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) /* MS Pull Control Enable:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)  *     MS CD       ==> pull up
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)  *     others      ==> pull down
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) static const u32 rts5260_ms_pull_ctl_enable_tbl[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	RTSX_REG_PAIR(CARD_PULL_CTL4, 0x55),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	RTSX_REG_PAIR(CARD_PULL_CTL5, 0x55),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	RTSX_REG_PAIR(CARD_PULL_CTL6, 0x15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) /* MS Pull Control Disable:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)  *     MS CD       ==> pull up
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)  *     others      ==> pull down
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) static const u32 rts5260_ms_pull_ctl_disable_tbl[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	RTSX_REG_PAIR(CARD_PULL_CTL4, 0x55),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	RTSX_REG_PAIR(CARD_PULL_CTL5, 0x55),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	RTSX_REG_PAIR(CARD_PULL_CTL6, 0x15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) static int sd_set_sample_push_timing_sd30(struct rtsx_pcr *pcr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	rtsx_pci_write_register(pcr, SD_CFG1, SD_MODE_SELECT_MASK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 		| SD_ASYNC_FIFO_NOT_RST, SD_30_MODE | SD_ASYNC_FIFO_NOT_RST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	rtsx_pci_write_register(pcr, CLK_CTL, CLK_LOW_FREQ, CLK_LOW_FREQ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	rtsx_pci_write_register(pcr, CARD_CLK_SOURCE, 0xFF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 			CRC_VAR_CLK0 | SD30_FIX_CLK | SAMPLE_VAR_CLK1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	rtsx_pci_write_register(pcr, CLK_CTL, CLK_LOW_FREQ, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) static int rts5260_card_power_on(struct rtsx_pcr *pcr, int card)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	struct rtsx_cr_option *option = &pcr->option;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	if (option->ocp_en)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 		rtsx_pci_enable_ocp(pcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	rtsx_pci_write_register(pcr, LDO_CONFIG2, DV331812_VDD1, DV331812_VDD1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	rtsx_pci_write_register(pcr, LDO_VCC_CFG0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 			 RTS5260_DVCC_TUNE_MASK, RTS5260_DVCC_33);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	rtsx_pci_write_register(pcr, LDO_VCC_CFG1, LDO_POW_SDVDD1_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 			LDO_POW_SDVDD1_ON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	rtsx_pci_write_register(pcr, LDO_CONFIG2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 			 DV331812_POWERON, DV331812_POWERON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	msleep(20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	if (pcr->extra_caps & EXTRA_CAPS_SD_SDR50 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	    pcr->extra_caps & EXTRA_CAPS_SD_SDR104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 		sd_set_sample_push_timing_sd30(pcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	/* Initialize SD_CFG1 register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	rtsx_pci_write_register(pcr, SD_CFG1, 0xFF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 				SD_CLK_DIVIDE_128 | SD_20_MODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 	rtsx_pci_write_register(pcr, SD_SAMPLE_POINT_CTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 				0xFF, SD20_RX_POS_EDGE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	rtsx_pci_write_register(pcr, SD_PUSH_POINT_CTL, 0xFF, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 	rtsx_pci_write_register(pcr, CARD_STOP, SD_STOP | SD_CLR_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 				SD_STOP | SD_CLR_ERR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	/* Reset SD_CFG3 register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	rtsx_pci_write_register(pcr, SD_CFG3, SD30_CLK_END_EN, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	rtsx_pci_write_register(pcr, REG_SD_STOP_SDCLK_CFG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 			SD30_CLK_STOP_CFG_EN | SD30_CLK_STOP_CFG1 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 			SD30_CLK_STOP_CFG0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 	rtsx_pci_write_register(pcr, REG_PRE_RW_MODE, EN_INFINITE_MODE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) static int rts5260_switch_output_voltage(struct rtsx_pcr *pcr, u8 voltage)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 	switch (voltage) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 	case OUTPUT_3V3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 		rtsx_pci_write_register(pcr, LDO_CONFIG2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 					DV331812_VDD1, DV331812_VDD1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 		rtsx_pci_write_register(pcr, LDO_DV18_CFG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 					DV331812_MASK, DV331812_33);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 		rtsx_pci_write_register(pcr, SD_PAD_CTL, SD_IO_USING_1V8, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 	case OUTPUT_1V8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 		rtsx_pci_write_register(pcr, LDO_CONFIG2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 					DV331812_VDD1, DV331812_VDD1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 		rtsx_pci_write_register(pcr, LDO_DV18_CFG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 					DV331812_MASK, DV331812_17);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 		rtsx_pci_write_register(pcr, SD_PAD_CTL, SD_IO_USING_1V8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 					SD_IO_USING_1V8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 	/* set pad drive */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 	rts5260_fill_driving(pcr, voltage);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) static void rts5260_stop_cmd(struct rtsx_pcr *pcr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 	rtsx_pci_writel(pcr, RTSX_HCBCTLR, STOP_CMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 	rtsx_pci_writel(pcr, RTSX_HDBCTLR, STOP_DMA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 	rtsx_pci_write_register(pcr, RTS5260_DMA_RST_CTL_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 				RTS5260_DMA_RST | RTS5260_ADMA3_RST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 				RTS5260_DMA_RST | RTS5260_ADMA3_RST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 	rtsx_pci_write_register(pcr, RBCTL, RB_FLUSH, RB_FLUSH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) static void rts5260_card_before_power_off(struct rtsx_pcr *pcr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 	rts5260_stop_cmd(pcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 	rts5260_switch_output_voltage(pcr, OUTPUT_3V3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) static int rts5260_card_power_off(struct rtsx_pcr *pcr, int card)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 	int err = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 	rts5260_card_before_power_off(pcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 	err = rtsx_pci_write_register(pcr, LDO_VCC_CFG1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 			 LDO_POW_SDVDD1_MASK, LDO_POW_SDVDD1_OFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 	err = rtsx_pci_write_register(pcr, LDO_CONFIG2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 			 DV331812_POWERON, DV331812_POWEROFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 	if (pcr->option.ocp_en)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 		rtsx_pci_disable_ocp(pcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 	return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) static void rts5260_init_ocp(struct rtsx_pcr *pcr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 	struct rtsx_cr_option *option = &pcr->option;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 	if (option->ocp_en) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 		u8 mask, val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 		rtsx_pci_write_register(pcr, RTS5260_DVCC_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 				RTS5260_DVCC_OCP_THD_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 				option->sd_800mA_ocp_thd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 		rtsx_pci_write_register(pcr, RTS5260_DV331812_CFG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 				RTS5260_DV331812_OCP_THD_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 				RTS5260_DV331812_OCP_THD_270);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 		mask = SD_OCP_GLITCH_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 		val = pcr->hw_param.ocp_glitch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 		rtsx_pci_write_register(pcr, REG_OCPGLITCH, mask, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 		rtsx_pci_write_register(pcr, RTS5260_DVCC_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 					RTS5260_DVCC_OCP_EN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 					RTS5260_DVCC_OCP_CL_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 					RTS5260_DVCC_OCP_EN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 					RTS5260_DVCC_OCP_CL_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 		rtsx_pci_enable_ocp(pcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 		rtsx_pci_write_register(pcr, RTS5260_DVCC_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 					RTS5260_DVCC_OCP_EN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 					RTS5260_DVCC_OCP_CL_EN, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) static void rts5260_enable_ocp(struct rtsx_pcr *pcr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 	u8 val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 	val = SD_OCP_INT_EN | SD_DETECT_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 	rtsx_pci_write_register(pcr, REG_OCPCTL, 0xFF, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) static void rts5260_disable_ocp(struct rtsx_pcr *pcr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 	u8 mask = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 	mask = SD_OCP_INT_EN | SD_DETECT_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 	rtsx_pci_write_register(pcr, REG_OCPCTL, mask, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) static int rts5260_get_ocpstat(struct rtsx_pcr *pcr, u8 *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 	return rtsx_pci_read_register(pcr, REG_OCPSTAT, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) static int rts5260_get_ocpstat2(struct rtsx_pcr *pcr, u8 *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 	return rtsx_pci_read_register(pcr, REG_DV3318_OCPSTAT, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) static void rts5260_clear_ocpstat(struct rtsx_pcr *pcr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 	u8 mask = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 	u8 val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 	mask = SD_OCP_INT_CLR | SD_OC_CLR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 	val = SD_OCP_INT_CLR | SD_OC_CLR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 	rtsx_pci_write_register(pcr, REG_OCPCTL, mask, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 	rtsx_pci_write_register(pcr, REG_DV3318_OCPCTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 				DV3318_OCP_INT_CLR | DV3318_OCP_CLR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 				DV3318_OCP_INT_CLR | DV3318_OCP_CLR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) 	udelay(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 	rtsx_pci_write_register(pcr, REG_OCPCTL, mask, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 	rtsx_pci_write_register(pcr, REG_DV3318_OCPCTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 				DV3318_OCP_INT_CLR | DV3318_OCP_CLR, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) static void rts5260_process_ocp(struct rtsx_pcr *pcr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) 	if (!pcr->option.ocp_en)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) 	rtsx_pci_get_ocpstat(pcr, &pcr->ocp_stat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) 	rts5260_get_ocpstat2(pcr, &pcr->ocp_stat2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) 	if ((pcr->ocp_stat & (SD_OC_NOW | SD_OC_EVER)) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) 		(pcr->ocp_stat2 & (DV3318_OCP_NOW | DV3318_OCP_EVER))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) 		rtsx_pci_card_power_off(pcr, RTSX_SD_CARD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) 		rtsx_pci_write_register(pcr, CARD_OE, SD_OUTPUT_EN, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) 		rtsx_pci_clear_ocpstat(pcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) 		pcr->ocp_stat = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) 		pcr->ocp_stat2 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) static int rts5260_init_hw(struct rtsx_pcr *pcr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) 	int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) 	rtsx_pci_init_cmd(pcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) 	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, L1SUB_CONFIG1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) 			 AUX_CLK_ACTIVE_SEL_MASK, MAC_CKSW_DONE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) 	/* Rest L1SUB Config */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) 	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, L1SUB_CONFIG3, 0xFF, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) 	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PM_CLK_FORCE_CTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) 			 CLK_PM_EN, CLK_PM_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) 	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PWD_SUSPEND_EN, 0xFF, 0xFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) 	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PWR_GATE_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) 			 PWR_GATE_EN, PWR_GATE_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) 	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, REG_VREF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) 			 PWD_SUSPND_EN, PWD_SUSPND_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) 	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, RBCTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) 			 U_AUTO_DMA_EN_MASK, U_AUTO_DMA_DISABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) 	if (pcr->flags & PCR_REVERSE_SOCKET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) 		rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PETXCFG, 0xB0, 0xB0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) 		rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PETXCFG, 0xB0, 0x80);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) 	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, OBFF_CFG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) 			 OBFF_EN_MASK, OBFF_DISABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) 	err = rtsx_pci_send_cmd(pcr, CMD_TIMEOUT_DEF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) 	if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) 		return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) 	rtsx_pci_init_ocp(pcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) static void rts5260_pwr_saving_setting(struct rtsx_pcr *pcr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) 	int lss_l1_1, lss_l1_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) 	lss_l1_1 = rtsx_check_dev_flag(pcr, ASPM_L1_1_EN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) 			| rtsx_check_dev_flag(pcr, PM_L1_1_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) 	lss_l1_2 = rtsx_check_dev_flag(pcr, ASPM_L1_2_EN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) 			| rtsx_check_dev_flag(pcr, PM_L1_2_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) 	rtsx_pci_write_register(pcr, ASPM_FORCE_CTL, 0xFF, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) 	if (lss_l1_2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) 		pcr_dbg(pcr, "Set parameters for L1.2.");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) 		rtsx_pci_write_register(pcr, PWR_GLOBAL_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) 					0xFF, PCIE_L1_2_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) 		rtsx_pci_write_register(pcr, RTS5260_DVCC_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) 					RTS5260_DVCC_OCP_EN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) 					RTS5260_DVCC_OCP_CL_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) 					RTS5260_DVCC_OCP_EN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) 					RTS5260_DVCC_OCP_CL_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) 		rtsx_pci_write_register(pcr, PWR_FE_CTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) 					0xFF, PCIE_L1_2_PD_FE_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) 	} else if (lss_l1_1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) 		pcr_dbg(pcr, "Set parameters for L1.1.");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) 		rtsx_pci_write_register(pcr, PWR_GLOBAL_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) 					0xFF, PCIE_L1_1_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) 		rtsx_pci_write_register(pcr, PWR_FE_CTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) 					0xFF, PCIE_L1_1_PD_FE_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) 		pcr_dbg(pcr, "Set parameters for L1.");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) 		rtsx_pci_write_register(pcr, PWR_GLOBAL_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) 					0xFF, PCIE_L1_0_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) 		rtsx_pci_write_register(pcr, PWR_FE_CTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) 					0xFF, PCIE_L1_0_PD_FE_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) 	rtsx_pci_write_register(pcr, CFG_L1_0_PCIE_DPHY_RET_VALUE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) 				0xFF, CFG_L1_0_RET_VALUE_DEFAULT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) 	rtsx_pci_write_register(pcr, CFG_L1_0_PCIE_MAC_RET_VALUE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) 				0xFF, CFG_L1_0_RET_VALUE_DEFAULT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) 	rtsx_pci_write_register(pcr, CFG_L1_0_CRC_SD30_RET_VALUE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) 				0xFF, CFG_L1_0_RET_VALUE_DEFAULT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) 	rtsx_pci_write_register(pcr, CFG_L1_0_CRC_SD40_RET_VALUE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) 				0xFF, CFG_L1_0_RET_VALUE_DEFAULT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) 	rtsx_pci_write_register(pcr, CFG_L1_0_SYS_RET_VALUE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) 				0xFF, CFG_L1_0_RET_VALUE_DEFAULT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) 	/*Option cut APHY*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) 	rtsx_pci_write_register(pcr, CFG_PCIE_APHY_OFF_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) 				0xFF, CFG_PCIE_APHY_OFF_0_DEFAULT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) 	rtsx_pci_write_register(pcr, CFG_PCIE_APHY_OFF_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) 				0xFF, CFG_PCIE_APHY_OFF_1_DEFAULT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) 	rtsx_pci_write_register(pcr, CFG_PCIE_APHY_OFF_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) 				0xFF, CFG_PCIE_APHY_OFF_2_DEFAULT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) 	rtsx_pci_write_register(pcr, CFG_PCIE_APHY_OFF_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) 				0xFF, CFG_PCIE_APHY_OFF_3_DEFAULT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) 	/*CDR DEC*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) 	rtsx_pci_write_register(pcr, PWC_CDR, 0xFF, PWC_CDR_DEFAULT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) 	/*PWMPFM*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) 	rtsx_pci_write_register(pcr, CFG_LP_FPWM_VALUE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) 				0xFF, CFG_LP_FPWM_VALUE_DEFAULT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) 	/*No Power Saving WA*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) 	rtsx_pci_write_register(pcr, CFG_L1_0_CRC_MISC_RET_VALUE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) 				0xFF, CFG_L1_0_CRC_MISC_RET_VALUE_DEFAULT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) static void rts5260_init_from_cfg(struct rtsx_pcr *pcr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) 	struct pci_dev *pdev = pcr->pci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) 	int l1ss;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) 	struct rtsx_cr_option *option = &pcr->option;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) 	u32 lval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) 	l1ss = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_L1SS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) 	if (!l1ss)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) 	pci_read_config_dword(pdev, l1ss + PCI_L1SS_CTL1, &lval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) 	if (lval & PCI_L1SS_CTL1_ASPM_L1_1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) 		rtsx_set_dev_flag(pcr, ASPM_L1_1_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) 	if (lval & PCI_L1SS_CTL1_ASPM_L1_2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) 		rtsx_set_dev_flag(pcr, ASPM_L1_2_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) 	if (lval & PCI_L1SS_CTL1_PCIPM_L1_1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) 		rtsx_set_dev_flag(pcr, PM_L1_1_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) 	if (lval & PCI_L1SS_CTL1_PCIPM_L1_2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) 		rtsx_set_dev_flag(pcr, PM_L1_2_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) 	rts5260_pwr_saving_setting(pcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) 	if (option->ltr_en) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) 		u16 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) 		pcie_capability_read_word(pdev, PCI_EXP_DEVCTL2, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) 		if (val & PCI_EXP_DEVCTL2_LTR_EN) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) 			option->ltr_enabled = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) 			option->ltr_active = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) 			rtsx_set_ltr_latency(pcr, option->ltr_active_latency);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) 		} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) 			option->ltr_enabled = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) 	if (rtsx_check_dev_flag(pcr, ASPM_L1_1_EN | ASPM_L1_2_EN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) 				| PM_L1_1_EN | PM_L1_2_EN))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) 		option->force_clkreq_0 = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) 		option->force_clkreq_0 = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) static int rts5260_extra_init_hw(struct rtsx_pcr *pcr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) 	struct rtsx_cr_option *option = &pcr->option;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) 	/* Set mcu_cnt to 7 to ensure data can be sampled properly */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) 	rtsx_pci_write_register(pcr, 0xFC03, 0x7F, 0x07);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) 	rtsx_pci_write_register(pcr, SSC_DIV_N_0, 0xFF, 0x5D);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) 	rts5260_init_from_cfg(pcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) 	/* force no MDIO*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) 	rtsx_pci_write_register(pcr, RTS5260_AUTOLOAD_CFG4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) 				0xFF, RTS5260_MIMO_DISABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) 	/*Modify SDVCC Tune Default Parameters!*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) 	rtsx_pci_write_register(pcr, LDO_VCC_CFG0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) 				RTS5260_DVCC_TUNE_MASK, RTS5260_DVCC_33);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) 	rtsx_pci_write_register(pcr, PCLK_CTL, PCLK_MODE_SEL, PCLK_MODE_SEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) 	rts5260_init_hw(pcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) 	 * If u_force_clkreq_0 is enabled, CLKREQ# PIN will be forced
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) 	 * to drive low, and we forcibly request clock.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) 	if (option->force_clkreq_0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) 		rtsx_pci_write_register(pcr, PETXCFG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) 				 FORCE_CLKREQ_DELINK_MASK, FORCE_CLKREQ_LOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) 		rtsx_pci_write_register(pcr, PETXCFG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) 				 FORCE_CLKREQ_DELINK_MASK, FORCE_CLKREQ_HIGH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) 	rtsx_pci_write_register(pcr, pcr->reg_pm_ctrl3, 0x10, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) static void rts5260_set_l1off_cfg_sub_d0(struct rtsx_pcr *pcr, int active)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) 	struct rtsx_cr_option *option = &pcr->option;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) 	u32 interrupt = rtsx_pci_readl(pcr, RTSX_BIPR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) 	int card_exist = (interrupt & SD_EXIST) | (interrupt & MS_EXIST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) 	int aspm_L1_1, aspm_L1_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) 	u8 val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) 	aspm_L1_1 = rtsx_check_dev_flag(pcr, ASPM_L1_1_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) 	aspm_L1_2 = rtsx_check_dev_flag(pcr, ASPM_L1_2_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) 	if (active) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) 		/* run, latency: 60us */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) 		if (aspm_L1_1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) 			val = option->ltr_l1off_snooze_sspwrgate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) 		/* l1off, latency: 300us */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) 		if (aspm_L1_2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) 			val = option->ltr_l1off_sspwrgate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) 	if (aspm_L1_1 || aspm_L1_2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) 		if (rtsx_check_dev_flag(pcr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) 					LTR_L1SS_PWR_GATE_CHECK_CARD_EN)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) 			if (card_exist)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) 				val &= ~L1OFF_MBIAS2_EN_5250;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) 			else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) 				val |= L1OFF_MBIAS2_EN_5250;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) 	rtsx_set_l1off_sub(pcr, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) static const struct pcr_ops rts5260_pcr_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) 	.fetch_vendor_settings = rtsx_base_fetch_vendor_settings,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) 	.turn_on_led = rts5260_turn_on_led,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) 	.turn_off_led = rts5260_turn_off_led,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) 	.extra_init_hw = rts5260_extra_init_hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) 	.enable_auto_blink = rtsx_base_enable_auto_blink,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) 	.disable_auto_blink = rtsx_base_disable_auto_blink,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) 	.card_power_on = rts5260_card_power_on,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) 	.card_power_off = rts5260_card_power_off,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) 	.switch_output_voltage = rts5260_switch_output_voltage,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) 	.stop_cmd = rts5260_stop_cmd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) 	.set_l1off_cfg_sub_d0 = rts5260_set_l1off_cfg_sub_d0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) 	.enable_ocp = rts5260_enable_ocp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) 	.disable_ocp = rts5260_disable_ocp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) 	.init_ocp = rts5260_init_ocp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) 	.process_ocp = rts5260_process_ocp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) 	.get_ocpstat = rts5260_get_ocpstat,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) 	.clear_ocpstat = rts5260_clear_ocpstat,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) void rts5260_init_params(struct rtsx_pcr *pcr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) 	struct rtsx_cr_option *option = &pcr->option;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) 	struct rtsx_hw_param *hw_param = &pcr->hw_param;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) 	pcr->extra_caps = EXTRA_CAPS_SD_SDR50 | EXTRA_CAPS_SD_SDR104;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) 	pcr->num_slots = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) 	pcr->flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) 	pcr->card_drive_sel = RTSX_CARD_DRIVE_DEFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) 	pcr->sd30_drive_sel_1v8 = CFG_DRIVER_TYPE_B;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) 	pcr->sd30_drive_sel_3v3 = CFG_DRIVER_TYPE_B;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) 	pcr->aspm_en = ASPM_L1_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) 	pcr->tx_initial_phase = SET_CLOCK_PHASE(27, 29, 11);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) 	pcr->rx_initial_phase = SET_CLOCK_PHASE(24, 6, 5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) 	pcr->ic_version = rts5260_get_ic_version(pcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) 	pcr->sd_pull_ctl_enable_tbl = rts5260_sd_pull_ctl_enable_tbl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) 	pcr->sd_pull_ctl_disable_tbl = rts5260_sd_pull_ctl_disable_tbl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) 	pcr->ms_pull_ctl_enable_tbl = rts5260_ms_pull_ctl_enable_tbl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) 	pcr->ms_pull_ctl_disable_tbl = rts5260_ms_pull_ctl_disable_tbl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) 	pcr->reg_pm_ctrl3 = RTS524A_PM_CTRL3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) 	pcr->ops = &rts5260_pcr_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) 	option->dev_flags = (LTR_L1SS_PWR_GATE_CHECK_CARD_EN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) 				| LTR_L1SS_PWR_GATE_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) 	option->ltr_en = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) 	/* init latency of active, idle, L1OFF to 60us, 300us, 3ms */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) 	option->ltr_active_latency = LTR_ACTIVE_LATENCY_DEF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) 	option->ltr_idle_latency = LTR_IDLE_LATENCY_DEF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) 	option->ltr_l1off_latency = LTR_L1OFF_LATENCY_DEF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) 	option->l1_snooze_delay = L1_SNOOZE_DELAY_DEF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) 	option->ltr_l1off_sspwrgate = LTR_L1OFF_SSPWRGATE_5250_DEF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) 	option->ltr_l1off_snooze_sspwrgate =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) 		LTR_L1OFF_SNOOZE_SSPWRGATE_5250_DEF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) 	option->ocp_en = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) 	if (option->ocp_en)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) 		hw_param->interrupt_en |= SD_OC_INT_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) 	hw_param->ocp_glitch =  SD_OCP_GLITCH_100U | SDVIO_OCP_GLITCH_800U;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) 	option->sd_400mA_ocp_thd = RTS5260_DVCC_OCP_THD_550;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) 	option->sd_800mA_ocp_thd = RTS5260_DVCC_OCP_THD_970;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) }